4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef _RTE_MEMORY_H_
35 #define _RTE_MEMORY_H_
40 * Memory-related RTE API.
51 #include <rte_common.h>
55 RTE_PGSIZE_4K = 1ULL << 12,
56 RTE_PGSIZE_64K = 1ULL << 16,
57 RTE_PGSIZE_256K = 1ULL << 18,
58 RTE_PGSIZE_2M = 1ULL << 21,
59 RTE_PGSIZE_16M = 1ULL << 24,
60 RTE_PGSIZE_256M = 1ULL << 28,
61 RTE_PGSIZE_512M = 1ULL << 29,
62 RTE_PGSIZE_1G = 1ULL << 30,
63 RTE_PGSIZE_4G = 1ULL << 32,
64 RTE_PGSIZE_16G = 1ULL << 34,
67 #define SOCKET_ID_ANY -1 /**< Any NUMA socket. */
68 #define RTE_CACHE_LINE_MASK (RTE_CACHE_LINE_SIZE-1) /**< Cache line mask. */
70 #define RTE_CACHE_LINE_ROUNDUP(size) \
71 (RTE_CACHE_LINE_SIZE * ((size + RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE))
72 /**< Return the first cache-aligned value greater or equal to size. */
74 /**< Cache line size in terms of log2 */
75 #if RTE_CACHE_LINE_SIZE == 64
76 #define RTE_CACHE_LINE_SIZE_LOG2 6
77 #elif RTE_CACHE_LINE_SIZE == 128
78 #define RTE_CACHE_LINE_SIZE_LOG2 7
80 #error "Unsupported cache line size"
83 #define RTE_CACHE_LINE_MIN_SIZE 64 /**< Minimum Cache line size. */
86 * Force alignment to cache line.
88 #define __rte_cache_aligned __rte_aligned(RTE_CACHE_LINE_SIZE)
91 * Force minimum cache line alignment.
93 #define __rte_cache_min_aligned __rte_aligned(RTE_CACHE_LINE_MIN_SIZE)
95 typedef uint64_t phys_addr_t; /**< Physical address definition. */
96 #define RTE_BAD_PHYS_ADDR ((phys_addr_t)-1)
99 * Physical memory segment descriptor.
102 phys_addr_t phys_addr; /**< Start physical address. */
105 void *addr; /**< Start virtual address. */
106 uint64_t addr_64; /**< Makes sure addr is always 64 bits */
108 size_t len; /**< Length of the segment. */
109 uint64_t hugepage_sz; /**< The pagesize of underlying memory */
110 int32_t socket_id; /**< NUMA socket ID. */
111 uint32_t nchannel; /**< Number of channels. */
112 uint32_t nrank; /**< Number of ranks. */
116 * Lock page in physical memory and prevent from swapping.
119 * The virtual address.
121 * 0 on success, negative on error.
123 int rte_mem_lock_page(const void *virt);
126 * Get physical address of any mapped virtual address in the current process.
127 * It is found by browsing the /proc/self/pagemap special file.
128 * The page must be locked.
131 * The virtual address.
133 * The physical address or RTE_BAD_PHYS_ADDR on error.
135 phys_addr_t rte_mem_virt2phy(const void *virt);
138 * Get the layout of the available physical memory.
140 * It can be useful for an application to have the full physical
141 * memory layout to decide the size of a memory zone to reserve. This
142 * table is stored in rte_config (see rte_eal_get_configuration()).
145 * - On success, return a pointer to a read-only table of struct
146 * rte_physmem_desc elements, containing the layout of all
147 * addressable physical memory. The last element of the table
148 * contains a NULL address.
149 * - On error, return NULL. This should not happen since it is a fatal
150 * error that will probably cause the entire system to panic.
152 const struct rte_memseg *rte_eal_get_physmem_layout(void);
155 * Dump the physical memory layout to a file.
158 * A pointer to a file for output
160 void rte_dump_physmem_layout(FILE *f);
163 * Get the total amount of available physical memory.
166 * The total amount of available physical memory in bytes.
168 uint64_t rte_eal_get_physmem_size(void);
171 * Get the number of memory channels.
174 * The number of memory channels on the system. The value is 0 if unknown
175 * or not the same on all devices.
177 unsigned rte_memory_get_nchannel(void);
180 * Get the number of memory ranks.
183 * The number of memory ranks on the system. The value is 0 if unknown or
184 * not the same on all devices.
186 unsigned rte_memory_get_nrank(void);
189 * Drivers based on uio will not load unless physical
190 * addresses are obtainable. It is only possible to get
191 * physical addresses when running as a privileged user.
194 * 1 if the system is able to obtain physical addresses.
195 * 0 if using DMA addresses through an IOMMU.
197 int rte_eal_using_phys_addrs(void);
203 #endif /* _RTE_MEMORY_H_ */