1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Cavium, Inc
3 * Copyright(c) 2019 Arm Limited
12 * CPU pause operation.
18 #include <rte_common.h>
19 #include <rte_atomic.h>
20 #include <rte_compat.h>
23 * Pause CPU execution for a short while
25 * This call is intended for tight loops which poll a shared resource or wait
26 * for an event. A short pause within the loop may reduce the power consumption.
28 static inline void rte_pause(void);
31 * Wait for *addr to be updated with a 16-bit expected value, with a relaxed
32 * memory ordering model meaning the loads around this API can be reordered.
35 * A pointer to the memory location.
37 * A 16-bit expected value to be in the memory location.
39 * Two different memory orders that can be specified:
40 * __ATOMIC_ACQUIRE and __ATOMIC_RELAXED. These map to
41 * C++11 memory orders with the same names, see the C++11 standard or
42 * the GCC wiki on atomic synchronization for detailed definition.
44 static __rte_always_inline void
45 rte_wait_until_equal_16(volatile uint16_t *addr, uint16_t expected,
49 * Wait for *addr to be updated with a 32-bit expected value, with a relaxed
50 * memory ordering model meaning the loads around this API can be reordered.
53 * A pointer to the memory location.
55 * A 32-bit expected value to be in the memory location.
57 * Two different memory orders that can be specified:
58 * __ATOMIC_ACQUIRE and __ATOMIC_RELAXED. These map to
59 * C++11 memory orders with the same names, see the C++11 standard or
60 * the GCC wiki on atomic synchronization for detailed definition.
62 static __rte_always_inline void
63 rte_wait_until_equal_32(volatile uint32_t *addr, uint32_t expected,
67 * Wait for *addr to be updated with a 64-bit expected value, with a relaxed
68 * memory ordering model meaning the loads around this API can be reordered.
71 * A pointer to the memory location.
73 * A 64-bit expected value to be in the memory location.
75 * Two different memory orders that can be specified:
76 * __ATOMIC_ACQUIRE and __ATOMIC_RELAXED. These map to
77 * C++11 memory orders with the same names, see the C++11 standard or
78 * the GCC wiki on atomic synchronization for detailed definition.
80 static __rte_always_inline void
81 rte_wait_until_equal_64(volatile uint64_t *addr, uint64_t expected,
84 #ifndef RTE_WAIT_UNTIL_EQUAL_ARCH_DEFINED
85 static __rte_always_inline void
86 rte_wait_until_equal_16(volatile uint16_t *addr, uint16_t expected,
89 assert(memorder == __ATOMIC_ACQUIRE || memorder == __ATOMIC_RELAXED);
91 while (__atomic_load_n(addr, memorder) != expected)
95 static __rte_always_inline void
96 rte_wait_until_equal_32(volatile uint32_t *addr, uint32_t expected,
99 assert(memorder == __ATOMIC_ACQUIRE || memorder == __ATOMIC_RELAXED);
101 while (__atomic_load_n(addr, memorder) != expected)
105 static __rte_always_inline void
106 rte_wait_until_equal_64(volatile uint64_t *addr, uint64_t expected,
109 assert(memorder == __ATOMIC_ACQUIRE || memorder == __ATOMIC_RELAXED);
111 while (__atomic_load_n(addr, memorder) != expected)
116 #endif /* _RTE_PAUSE_H_ */