1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2016 6WIND S.A.
10 * SIMD vector types and control
12 * This file defines types to use vector instructions with generic C code
13 * and APIs to enable the code using them.
18 #include <rte_compat.h>
20 /* Unsigned vector types */
23 * 64 bits vector size to use with unsigned 8 bits elements.
25 * a = (rte_v64u8_t){ a0, a1, a2, a3, a4, a5, a6, a7 }
27 typedef uint8_t rte_v64u8_t __attribute__((vector_size(8), aligned(8)));
30 * 64 bits vector size to use with unsigned 16 bits elements.
32 * a = (rte_v64u16_t){ a0, a1, a2, a3 }
34 typedef uint16_t rte_v64u16_t __attribute__((vector_size(8), aligned(8)));
37 * 64 bits vector size to use with unsigned 32 bits elements.
39 * a = (rte_v64u32_t){ a0, a1 }
41 typedef uint32_t rte_v64u32_t __attribute__((vector_size(8), aligned(8)));
44 * 128 bits vector size to use with unsigned 8 bits elements.
46 * a = (rte_v128u8_t){ a00, a01, a02, a03, a04, a05, a06, a07,
47 * a08, a09, a10, a11, a12, a13, a14, a15 }
49 typedef uint8_t rte_v128u8_t __attribute__((vector_size(16), aligned(16)));
52 * 128 bits vector size to use with unsigned 16 bits elements.
54 * a = (rte_v128u16_t){ a0, a1, a2, a3, a4, a5, a6, a7 }
56 typedef uint16_t rte_v128u16_t __attribute__((vector_size(16), aligned(16)));
59 * 128 bits vector size to use with unsigned 32 bits elements.
61 * a = (rte_v128u32_t){ a0, a1, a2, a3 }
63 typedef uint32_t rte_v128u32_t __attribute__((vector_size(16), aligned(16)));
66 * 128 bits vector size to use with unsigned 64 bits elements.
68 * a = (rte_v128u64_t){ a0, a1 }
70 typedef uint64_t rte_v128u64_t __attribute__((vector_size(16), aligned(16)));
73 * 256 bits vector size to use with unsigned 8 bits elements.
75 * a = (rte_v256u8_t){ a00, a01, a02, a03, a04, a05, a06, a07,
76 * a08, a09, a10, a11, a12, a13, a14, a15,
77 * a16, a17, a18, a19, a20, a21, a22, a23,
78 * a24, a25, a26, a27, a28, a29, a30, a31 }
80 typedef uint8_t rte_v256u8_t __attribute__((vector_size(32), aligned(32)));
83 * 256 bits vector size to use with unsigned 16 bits elements.
85 * a = (rte_v256u16_t){ a00, a01, a02, a03, a04, a05, a06, a07,
86 * a08, a09, a10, a11, a12, a13, a14, a15 }
88 typedef uint16_t rte_v256u16_t __attribute__((vector_size(32), aligned(32)));
91 * 256 bits vector size to use with unsigned 32 bits elements.
93 * a = (rte_v256u32_t){ a0, a1, a2, a3, a4, a5, a6, a7 }
95 typedef uint32_t rte_v256u32_t __attribute__((vector_size(32), aligned(32)));
98 * 256 bits vector size to use with unsigned 64 bits elements.
100 * a = (rte_v256u64_t){ a0, a1, a2, a3 }
102 typedef uint64_t rte_v256u64_t __attribute__((vector_size(32), aligned(32)));
105 /* Signed vector types */
108 * 64 bits vector size to use with 8 bits elements.
110 * a = (rte_v64s8_t){ a0, a1, a2, a3, a4, a5, a6, a7 }
112 typedef int8_t rte_v64s8_t __attribute__((vector_size(8), aligned(8)));
115 * 64 bits vector size to use with 16 bits elements.
117 * a = (rte_v64s16_t){ a0, a1, a2, a3 }
119 typedef int16_t rte_v64s16_t __attribute__((vector_size(8), aligned(8)));
122 * 64 bits vector size to use with 32 bits elements.
124 * a = (rte_v64s32_t){ a0, a1 }
126 typedef int32_t rte_v64s32_t __attribute__((vector_size(8), aligned(8)));
129 * 128 bits vector size to use with 8 bits elements.
131 * a = (rte_v128s8_t){ a00, a01, a02, a03, a04, a05, a06, a07,
132 * a08, a09, a10, a11, a12, a13, a14, a15 }
134 typedef int8_t rte_v128s8_t __attribute__((vector_size(16), aligned(16)));
137 * 128 bits vector size to use with 16 bits elements.
139 * a = (rte_v128s16_t){ a0, a1, a2, a3, a4, a5, a6, a7 }
141 typedef int16_t rte_v128s16_t __attribute__((vector_size(16), aligned(16)));
144 * 128 bits vector size to use with 32 bits elements.
146 * a = (rte_v128s32_t){ a0, a1, a2, a3 }
148 typedef int32_t rte_v128s32_t __attribute__((vector_size(16), aligned(16)));
151 * 128 bits vector size to use with 64 bits elements.
153 * a = (rte_v128s64_t){ a1, a2 }
155 typedef int64_t rte_v128s64_t __attribute__((vector_size(16), aligned(16)));
158 * 256 bits vector size to use with 8 bits elements.
160 * a = (rte_v256s8_t){ a00, a01, a02, a03, a04, a05, a06, a07,
161 * a08, a09, a10, a11, a12, a13, a14, a15,
162 * a16, a17, a18, a19, a20, a21, a22, a23,
163 * a24, a25, a26, a27, a28, a29, a30, a31 }
165 typedef int8_t rte_v256s8_t __attribute__((vector_size(32), aligned(32)));
168 * 256 bits vector size to use with 16 bits elements.
170 * a = (rte_v256s16_t){ a00, a01, a02, a03, a04, a05, a06, a07,
171 * a08, a09, a10, a11, a12, a13, a14, a15 }
173 typedef int16_t rte_v256s16_t __attribute__((vector_size(32), aligned(32)));
176 * 256 bits vector size to use with 32 bits elements.
178 * a = (rte_v256s32_t){ a0, a1, a2, a3, a4, a5, a6, a7 }
180 typedef int32_t rte_v256s32_t __attribute__((vector_size(32), aligned(32)));
183 * 256 bits vector size to use with 64 bits elements.
185 * a = (rte_v256s64_t){ a0, a1, a2, a3 }
187 typedef int64_t rte_v256s64_t __attribute__((vector_size(32), aligned(32)));
190 * The max SIMD bitwidth value to limit vector path selection.
192 enum rte_vect_max_simd {
193 RTE_VECT_SIMD_DISABLED = 64,
194 /**< Limits path selection to scalar, disables all vector paths. */
195 RTE_VECT_SIMD_128 = 128,
196 /**< Limits path selection to SSE/NEON/Altivec or below. */
197 RTE_VECT_SIMD_256 = 256, /**< Limits path selection to AVX2 or below. */
198 RTE_VECT_SIMD_512 = 512, /**< Limits path selection to AVX512 or below. */
199 RTE_VECT_SIMD_MAX = INT16_MAX + 1,
201 * Disables limiting by max SIMD bitwidth, allows all suitable paths.
202 * This value is used as it is a large number and a power of 2.
208 * @b EXPERIMENTAL: this API may change, or be removed, without prior notice
210 * Get the supported SIMD bitwidth.
216 uint16_t rte_vect_get_max_simd_bitwidth(void);
220 * @b EXPERIMENTAL: this API may change, or be removed, without prior notice
222 * Set the supported SIMD bitwidth.
223 * This API should only be called once at initialization, before EAL init.
229 * - -EINVAL on invalid bitwidth parameter.
230 * - -EPERM if bitwidth is forced.
233 int rte_vect_set_max_simd_bitwidth(uint16_t bitwidth);
235 #endif /* _RTE_VECT_H_ */