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36 #include <linux/pci_regs.h>
37 #include <sys/eventfd.h>
38 #include <sys/socket.h>
39 #include <sys/ioctl.h>
45 #include <rte_eal_memconfig.h>
46 #include <rte_malloc.h>
48 #include "eal_filesystem.h"
49 #include "eal_pci_init.h"
51 #include "eal_private.h"
55 * PCI probing under linux (VFIO version)
57 * This code tries to determine if the PCI device is bound to VFIO driver,
58 * and initialize it (map BARs, set up interrupts) if that's the case.
60 * This file is only compiled if CONFIG_RTE_EAL_VFIO is set to "y".
65 #define PAGE_SIZE (sysconf(_SC_PAGESIZE))
66 #define PAGE_MASK (~(PAGE_SIZE - 1))
68 static struct rte_tailq_elem rte_vfio_tailq = {
69 .name = "VFIO_RESOURCE_LIST",
71 EAL_REGISTER_TAILQ(rte_vfio_tailq)
74 pci_vfio_read_config(const struct rte_intr_handle *intr_handle,
75 void *buf, size_t len, off_t offs)
77 return pread64(intr_handle->vfio_dev_fd, buf, len,
78 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + offs);
82 pci_vfio_write_config(const struct rte_intr_handle *intr_handle,
83 const void *buf, size_t len, off_t offs)
85 return pwrite64(intr_handle->vfio_dev_fd, buf, len,
86 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + offs);
89 /* get PCI BAR number where MSI-X interrupts are */
91 pci_vfio_get_msix_bar(int fd, int *msix_bar, uint32_t *msix_table_offset,
92 uint32_t *msix_table_size)
97 uint8_t cap_id, cap_offset;
99 /* read PCI capability pointer from config space */
100 ret = pread64(fd, ®, sizeof(reg),
101 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
102 PCI_CAPABILITY_LIST);
103 if (ret != sizeof(reg)) {
104 RTE_LOG(ERR, EAL, "Cannot read capability pointer from PCI "
109 /* we need first byte */
110 cap_offset = reg & 0xFF;
114 /* read PCI capability ID */
115 ret = pread64(fd, ®, sizeof(reg),
116 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
118 if (ret != sizeof(reg)) {
119 RTE_LOG(ERR, EAL, "Cannot read capability ID from PCI "
124 /* we need first byte */
127 /* if we haven't reached MSI-X, check next capability */
128 if (cap_id != PCI_CAP_ID_MSIX) {
129 ret = pread64(fd, ®, sizeof(reg),
130 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
132 if (ret != sizeof(reg)) {
133 RTE_LOG(ERR, EAL, "Cannot read capability pointer from PCI "
138 /* we need second byte */
139 cap_offset = (reg & 0xFF00) >> 8;
143 /* else, read table offset */
145 /* table offset resides in the next 4 bytes */
146 ret = pread64(fd, ®, sizeof(reg),
147 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
149 if (ret != sizeof(reg)) {
150 RTE_LOG(ERR, EAL, "Cannot read table offset from PCI config "
155 ret = pread64(fd, &flags, sizeof(flags),
156 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
158 if (ret != sizeof(flags)) {
159 RTE_LOG(ERR, EAL, "Cannot read table flags from PCI config "
164 *msix_bar = reg & RTE_PCI_MSIX_TABLE_BIR;
165 *msix_table_offset = reg & RTE_PCI_MSIX_TABLE_OFFSET;
166 *msix_table_size = 16 * (1 + (flags & RTE_PCI_MSIX_FLAGS_QSIZE));
174 /* set PCI bus mastering */
176 pci_vfio_set_bus_master(int dev_fd, bool op)
181 ret = pread64(dev_fd, ®, sizeof(reg),
182 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
184 if (ret != sizeof(reg)) {
185 RTE_LOG(ERR, EAL, "Cannot read command from PCI config space!\n");
190 /* set the master bit */
191 reg |= PCI_COMMAND_MASTER;
193 reg &= ~(PCI_COMMAND_MASTER);
195 ret = pwrite64(dev_fd, ®, sizeof(reg),
196 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
199 if (ret != sizeof(reg)) {
200 RTE_LOG(ERR, EAL, "Cannot write command to PCI config space!\n");
207 /* set up interrupt support (but not enable interrupts) */
209 pci_vfio_setup_interrupts(struct rte_pci_device *dev, int vfio_dev_fd)
211 int i, ret, intr_idx;
213 /* default to invalid index */
214 intr_idx = VFIO_PCI_NUM_IRQS;
216 /* get interrupt type from internal config (MSI-X by default, can be
217 * overriden from the command line
219 switch (internal_config.vfio_intr_mode) {
220 case RTE_INTR_MODE_MSIX:
221 intr_idx = VFIO_PCI_MSIX_IRQ_INDEX;
223 case RTE_INTR_MODE_MSI:
224 intr_idx = VFIO_PCI_MSI_IRQ_INDEX;
226 case RTE_INTR_MODE_LEGACY:
227 intr_idx = VFIO_PCI_INTX_IRQ_INDEX;
229 /* don't do anything if we want to automatically determine interrupt type */
230 case RTE_INTR_MODE_NONE:
233 RTE_LOG(ERR, EAL, " unknown default interrupt type!\n");
237 /* start from MSI-X interrupt type */
238 for (i = VFIO_PCI_MSIX_IRQ_INDEX; i >= 0; i--) {
239 struct vfio_irq_info irq = { .argsz = sizeof(irq) };
242 /* skip interrupt modes we don't want */
243 if (internal_config.vfio_intr_mode != RTE_INTR_MODE_NONE &&
249 ret = ioctl(vfio_dev_fd, VFIO_DEVICE_GET_IRQ_INFO, &irq);
251 RTE_LOG(ERR, EAL, " cannot get IRQ info, "
252 "error %i (%s)\n", errno, strerror(errno));
256 /* if this vector cannot be used with eventfd, fail if we explicitly
257 * specified interrupt type, otherwise continue */
258 if ((irq.flags & VFIO_IRQ_INFO_EVENTFD) == 0) {
259 if (internal_config.vfio_intr_mode != RTE_INTR_MODE_NONE) {
261 " interrupt vector does not support eventfd!\n");
267 /* set up an eventfd for interrupts */
268 fd = eventfd(0, EFD_NONBLOCK | EFD_CLOEXEC);
270 RTE_LOG(ERR, EAL, " cannot set up eventfd, "
271 "error %i (%s)\n", errno, strerror(errno));
275 dev->intr_handle.fd = fd;
276 dev->intr_handle.vfio_dev_fd = vfio_dev_fd;
279 case VFIO_PCI_MSIX_IRQ_INDEX:
280 internal_config.vfio_intr_mode = RTE_INTR_MODE_MSIX;
281 dev->intr_handle.type = RTE_INTR_HANDLE_VFIO_MSIX;
283 case VFIO_PCI_MSI_IRQ_INDEX:
284 internal_config.vfio_intr_mode = RTE_INTR_MODE_MSI;
285 dev->intr_handle.type = RTE_INTR_HANDLE_VFIO_MSI;
287 case VFIO_PCI_INTX_IRQ_INDEX:
288 internal_config.vfio_intr_mode = RTE_INTR_MODE_LEGACY;
289 dev->intr_handle.type = RTE_INTR_HANDLE_VFIO_LEGACY;
292 RTE_LOG(ERR, EAL, " unknown interrupt type!\n");
299 /* if we're here, we haven't found a suitable interrupt vector */
304 * map the PCI resources of a PCI device in virtual memory (VFIO version).
305 * primary and secondary processes follow almost exactly the same path
308 pci_vfio_map_resource(struct rte_pci_device *dev)
310 struct vfio_device_info device_info = { .argsz = sizeof(device_info) };
311 char pci_addr[PATH_MAX] = {0};
313 struct rte_pci_addr *loc = &dev->addr;
314 int i, ret, msix_bar;
315 struct mapped_pci_resource *vfio_res = NULL;
316 struct mapped_pci_res_list *vfio_res_list = RTE_TAILQ_CAST(rte_vfio_tailq.head, mapped_pci_res_list);
318 struct pci_map *maps;
319 uint32_t msix_table_offset = 0;
320 uint32_t msix_table_size = 0;
323 dev->intr_handle.fd = -1;
324 dev->intr_handle.type = RTE_INTR_HANDLE_UNKNOWN;
326 /* store PCI address string */
327 snprintf(pci_addr, sizeof(pci_addr), PCI_PRI_FMT,
328 loc->domain, loc->bus, loc->devid, loc->function);
330 if ((ret = vfio_setup_device(pci_get_sysfs_path(), pci_addr,
331 &vfio_dev_fd, &device_info)))
334 /* get MSI-X BAR, if any (we have to know where it is because we can't
335 * easily mmap it when using VFIO) */
337 ret = pci_vfio_get_msix_bar(vfio_dev_fd, &msix_bar,
338 &msix_table_offset, &msix_table_size);
340 RTE_LOG(ERR, EAL, " %s cannot get MSI-X BAR number!\n", pci_addr);
345 /* if we're in a primary process, allocate vfio_res and get region info */
346 if (internal_config.process_type == RTE_PROC_PRIMARY) {
347 vfio_res = rte_zmalloc("VFIO_RES", sizeof(*vfio_res), 0);
348 if (vfio_res == NULL) {
350 "%s(): cannot store uio mmap details\n", __func__);
354 memcpy(&vfio_res->pci_addr, &dev->addr, sizeof(vfio_res->pci_addr));
356 /* get number of registers (up to BAR5) */
357 vfio_res->nb_maps = RTE_MIN((int) device_info.num_regions,
358 VFIO_PCI_BAR5_REGION_INDEX + 1);
360 /* if we're in a secondary process, just find our tailq entry */
361 TAILQ_FOREACH(vfio_res, vfio_res_list, next) {
362 if (memcmp(&vfio_res->pci_addr, &dev->addr, sizeof(dev->addr)))
366 /* if we haven't found our tailq entry, something's wrong */
367 if (vfio_res == NULL) {
368 RTE_LOG(ERR, EAL, " %s cannot find TAILQ entry for PCI device!\n",
376 maps = vfio_res->maps;
378 for (i = 0; i < (int) vfio_res->nb_maps; i++) {
379 struct vfio_region_info reg = { .argsz = sizeof(reg) };
382 unsigned long offset, size;
387 ret = ioctl(vfio_dev_fd, VFIO_DEVICE_GET_REGION_INFO, ®);
390 RTE_LOG(ERR, EAL, " %s cannot get device region info "
391 "error %i (%s)\n", pci_addr, errno, strerror(errno));
393 if (internal_config.process_type == RTE_PROC_PRIMARY)
398 /* chk for io port region */
399 ret = pread64(vfio_dev_fd, &ioport_bar, sizeof(ioport_bar),
400 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX)
401 + PCI_BASE_ADDRESS_0 + i*4);
403 if (ret != sizeof(ioport_bar)) {
405 "Cannot read command (%x) from config space!\n",
406 PCI_BASE_ADDRESS_0 + i*4);
410 if (ioport_bar & PCI_BASE_ADDRESS_SPACE_IO) {
412 "Ignore mapping IO port bar(%d) addr: %x\n",
417 /* skip non-mmapable BARs */
418 if ((reg.flags & VFIO_REGION_INFO_FLAG_MMAP) == 0)
423 * VFIO will not let us map the MSI-X table,
424 * but we can map around it.
426 uint32_t table_start = msix_table_offset;
427 uint32_t table_end = table_start + msix_table_size;
428 table_end = (table_end + ~PAGE_MASK) & PAGE_MASK;
429 table_start &= PAGE_MASK;
431 if (table_start == 0 && table_end >= reg.size) {
432 /* Cannot map this BAR */
433 RTE_LOG(DEBUG, EAL, "Skipping BAR %d\n", i);
436 memreg[0].offset = reg.offset;
437 memreg[0].size = table_start;
438 memreg[1].offset = reg.offset + table_end;
439 memreg[1].size = reg.size - table_end;
442 "Trying to map BAR %d that contains the MSI-X "
443 "table. Trying offsets: "
444 "0x%04lx:0x%04lx, 0x%04lx:0x%04lx\n", i,
445 memreg[0].offset, memreg[0].size,
446 memreg[1].offset, memreg[1].size);
449 memreg[0].offset = reg.offset;
450 memreg[0].size = reg.size;
453 /* try to figure out an address */
454 if (internal_config.process_type == RTE_PROC_PRIMARY) {
455 /* try mapping somewhere close to the end of hugepages */
456 if (pci_map_addr == NULL)
457 pci_map_addr = pci_find_max_end_va();
459 bar_addr = pci_map_addr;
460 pci_map_addr = RTE_PTR_ADD(bar_addr, (size_t) reg.size);
462 bar_addr = maps[i].addr;
465 /* reserve the address using an inaccessible mapping */
466 bar_addr = mmap(bar_addr, reg.size, 0, MAP_PRIVATE |
467 MAP_ANONYMOUS, -1, 0);
468 if (bar_addr != MAP_FAILED) {
469 void *map_addr = NULL;
470 if (memreg[0].size) {
471 /* actual map of first part */
472 map_addr = pci_map_resource(bar_addr, vfio_dev_fd,
478 /* if there's a second part, try to map it */
479 if (map_addr != MAP_FAILED
480 && memreg[1].offset && memreg[1].size) {
481 void *second_addr = RTE_PTR_ADD(bar_addr,
483 (uintptr_t)reg.offset);
484 map_addr = pci_map_resource(second_addr,
485 vfio_dev_fd, memreg[1].offset,
490 if (map_addr == MAP_FAILED || !map_addr) {
491 munmap(bar_addr, reg.size);
492 bar_addr = MAP_FAILED;
496 if (bar_addr == MAP_FAILED ||
497 (internal_config.process_type == RTE_PROC_SECONDARY &&
498 bar_addr != maps[i].addr)) {
499 RTE_LOG(ERR, EAL, " %s mapping BAR%i failed: %s\n", pci_addr, i,
502 if (internal_config.process_type == RTE_PROC_PRIMARY)
507 maps[i].addr = bar_addr;
508 maps[i].offset = reg.offset;
509 maps[i].size = reg.size;
510 maps[i].path = NULL; /* vfio doesn't have per-resource paths */
511 dev->mem_resource[i].addr = bar_addr;
514 /* if secondary process, do not set up interrupts */
515 if (internal_config.process_type == RTE_PROC_PRIMARY) {
516 if (pci_vfio_setup_interrupts(dev, vfio_dev_fd) != 0) {
517 RTE_LOG(ERR, EAL, " %s error setting up interrupts!\n", pci_addr);
523 /* set bus mastering for the device */
524 if (pci_vfio_set_bus_master(vfio_dev_fd, true)) {
525 RTE_LOG(ERR, EAL, " %s cannot set up bus mastering!\n", pci_addr);
531 /* Reset the device */
532 ioctl(vfio_dev_fd, VFIO_DEVICE_RESET);
535 if (internal_config.process_type == RTE_PROC_PRIMARY)
536 TAILQ_INSERT_TAIL(vfio_res_list, vfio_res, next);
542 pci_vfio_unmap_resource(struct rte_pci_device *dev)
544 char pci_addr[PATH_MAX] = {0};
545 struct rte_pci_addr *loc = &dev->addr;
547 struct mapped_pci_resource *vfio_res = NULL;
548 struct mapped_pci_res_list *vfio_res_list;
550 struct pci_map *maps;
552 /* store PCI address string */
553 snprintf(pci_addr, sizeof(pci_addr), PCI_PRI_FMT,
554 loc->domain, loc->bus, loc->devid, loc->function);
557 if (close(dev->intr_handle.fd) < 0) {
558 RTE_LOG(INFO, EAL, "Error when closing eventfd file descriptor for %s\n",
563 if (pci_vfio_set_bus_master(dev->intr_handle.vfio_dev_fd, false)) {
564 RTE_LOG(ERR, EAL, " %s cannot unset bus mastering for PCI device!\n",
569 ret = vfio_release_device(pci_get_sysfs_path(), pci_addr,
570 dev->intr_handle.vfio_dev_fd);
573 "%s(): cannot release device\n", __func__);
577 vfio_res_list = RTE_TAILQ_CAST(rte_vfio_tailq.head, mapped_pci_res_list);
579 TAILQ_FOREACH(vfio_res, vfio_res_list, next) {
580 if (memcmp(&vfio_res->pci_addr, &dev->addr, sizeof(dev->addr)))
584 /* if we haven't found our tailq entry, something's wrong */
585 if (vfio_res == NULL) {
586 RTE_LOG(ERR, EAL, " %s cannot find TAILQ entry for PCI device!\n",
592 maps = vfio_res->maps;
594 RTE_LOG(INFO, EAL, "Releasing pci mapped resource for %s\n",
596 for (i = 0; i < (int) vfio_res->nb_maps; i++) {
599 * We do not need to be aware of MSI-X table BAR mappings as
600 * when mapping. Just using current maps array is enough
603 RTE_LOG(INFO, EAL, "Calling pci_unmap_resource for %s at %p\n",
604 pci_addr, maps[i].addr);
605 pci_unmap_resource(maps[i].addr, maps[i].size);
609 TAILQ_REMOVE(vfio_res_list, vfio_res, next);
615 pci_vfio_ioport_map(struct rte_pci_device *dev, int bar,
616 struct rte_pci_ioport *p)
618 if (bar < VFIO_PCI_BAR0_REGION_INDEX ||
619 bar > VFIO_PCI_BAR5_REGION_INDEX) {
620 RTE_LOG(ERR, EAL, "invalid bar (%d)!\n", bar);
625 p->base = VFIO_GET_REGION_ADDR(bar);
630 pci_vfio_ioport_read(struct rte_pci_ioport *p,
631 void *data, size_t len, off_t offset)
633 const struct rte_intr_handle *intr_handle = &p->dev->intr_handle;
635 if (pread64(intr_handle->vfio_dev_fd, data,
636 len, p->base + offset) <= 0)
638 "Can't read from PCI bar (%" PRIu64 ") : offset (%x)\n",
639 VFIO_GET_REGION_IDX(p->base), (int)offset);
643 pci_vfio_ioport_write(struct rte_pci_ioport *p,
644 const void *data, size_t len, off_t offset)
646 const struct rte_intr_handle *intr_handle = &p->dev->intr_handle;
648 if (pwrite64(intr_handle->vfio_dev_fd, data,
649 len, p->base + offset) <= 0)
651 "Can't write to PCI bar (%" PRIu64 ") : offset (%x)\n",
652 VFIO_GET_REGION_IDX(p->base), (int)offset);
656 pci_vfio_ioport_unmap(struct rte_pci_ioport *p)
663 pci_vfio_enable(void)
665 return vfio_enable("vfio_pci");
669 pci_vfio_is_enabled(void)
671 return vfio_is_enabled("vfio_pci");