4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * The full GNU General Public License is included in this distribution
19 * in the file called LICENSE.GPL.
21 * Contact Information:
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27 #include <linux/device.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/uio_driver.h>
32 #include <linux/msi.h>
33 #include <linux/version.h>
34 #include <linux/slab.h>
36 #ifdef CONFIG_XEN_DOM0
39 #include <rte_pci_dev_features.h>
44 * A structure describing the private information for a uio device.
46 struct rte_uio_pci_dev {
49 enum rte_intr_mode mode;
52 static char *intr_mode;
53 static enum rte_intr_mode igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
57 show_max_vfs(struct device *dev, struct device_attribute *attr,
60 return snprintf(buf, 10, "%u\n", dev_num_vf(dev));
64 store_max_vfs(struct device *dev, struct device_attribute *attr,
65 const char *buf, size_t count)
68 unsigned long max_vfs;
69 struct pci_dev *pdev = to_pci_dev(dev);
71 if (0 != kstrtoul(buf, 0, &max_vfs))
75 pci_disable_sriov(pdev);
76 else if (0 == pci_num_vf(pdev))
77 err = pci_enable_sriov(pdev, max_vfs);
78 else /* do nothing if change max_vfs number */
81 return err ? err : count;
84 static DEVICE_ATTR(max_vfs, S_IRUGO | S_IWUSR, show_max_vfs, store_max_vfs);
86 static struct attribute *dev_attrs[] = {
87 &dev_attr_max_vfs.attr,
91 static const struct attribute_group dev_attr_grp = {
95 * It masks the msix on/off of generating MSI-X messages.
98 igbuio_msix_mask_irq(struct msi_desc *desc, int32_t state)
100 u32 mask_bits = desc->masked;
101 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
102 PCI_MSIX_ENTRY_VECTOR_CTRL;
105 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
107 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
109 if (mask_bits != desc->masked) {
110 writel(mask_bits, desc->mask_base + offset);
111 readl(desc->mask_base);
112 desc->masked = mask_bits;
117 * This is the irqcontrol callback to be registered to uio_info.
118 * It can be used to disable/enable interrupt from user space processes.
121 * pointer to uio_info.
123 * state value. 1 to enable interrupt, 0 to disable interrupt.
127 * - On failure, a negative value.
130 igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
132 struct rte_uio_pci_dev *udev = info->priv;
133 struct pci_dev *pdev = udev->pdev;
135 pci_cfg_access_lock(pdev);
136 if (udev->mode == RTE_INTR_MODE_LEGACY)
137 pci_intx(pdev, !!irq_state);
139 else if (udev->mode == RTE_INTR_MODE_MSIX) {
140 struct msi_desc *desc;
142 #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 3, 0))
143 list_for_each_entry(desc, &pdev->msi_list, list)
144 igbuio_msix_mask_irq(desc, irq_state);
146 list_for_each_entry(desc, &pdev->dev.msi_list, list)
147 igbuio_msix_mask_irq(desc, irq_state);
150 pci_cfg_access_unlock(pdev);
156 * This is interrupt handler which will check if the interrupt is for the right device.
157 * If yes, disable it here and will be enable later.
160 igbuio_pci_irqhandler(int irq, struct uio_info *info)
162 struct rte_uio_pci_dev *udev = info->priv;
164 /* Legacy mode need to mask in hardware */
165 if (udev->mode == RTE_INTR_MODE_LEGACY &&
166 !pci_check_and_mask_intx(udev->pdev))
169 /* Message signal mode, no share IRQ and automasked */
174 * This gets called while opening uio device file.
177 igbuio_pci_open(struct uio_info *info, struct inode *inode)
179 struct rte_uio_pci_dev *udev = info->priv;
180 struct pci_dev *dev = udev->pdev;
182 pci_reset_function(dev);
184 /* set bus master, which was cleared by the reset function */
191 igbuio_pci_release(struct uio_info *info, struct inode *inode)
193 struct rte_uio_pci_dev *udev = info->priv;
194 struct pci_dev *dev = udev->pdev;
196 /* stop the device from further DMA */
197 pci_clear_master(dev);
199 pci_reset_function(dev);
204 #ifdef CONFIG_XEN_DOM0
206 igbuio_dom0_mmap_phys(struct uio_info *info, struct vm_area_struct *vma)
210 idx = (int)vma->vm_pgoff;
211 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
212 #ifdef HAVE_PTE_MASK_PAGE_IOMAP
213 vma->vm_page_prot.pgprot |= _PAGE_IOMAP;
216 return remap_pfn_range(vma,
218 info->mem[idx].addr >> PAGE_SHIFT,
219 vma->vm_end - vma->vm_start,
224 * This is uio device mmap method which will use igbuio mmap for Xen
228 igbuio_dom0_pci_mmap(struct uio_info *info, struct vm_area_struct *vma)
232 if (vma->vm_pgoff >= MAX_UIO_MAPS)
235 if (info->mem[vma->vm_pgoff].size == 0)
238 idx = (int)vma->vm_pgoff;
239 switch (info->mem[idx].memtype) {
241 return igbuio_dom0_mmap_phys(info, vma);
242 case UIO_MEM_LOGICAL:
243 case UIO_MEM_VIRTUAL:
250 /* Remap pci resources described by bar #pci_bar in uio resource n. */
252 igbuio_pci_setup_iomem(struct pci_dev *dev, struct uio_info *info,
253 int n, int pci_bar, const char *name)
255 unsigned long addr, len;
258 if (n >= ARRAY_SIZE(info->mem))
261 addr = pci_resource_start(dev, pci_bar);
262 len = pci_resource_len(dev, pci_bar);
263 if (addr == 0 || len == 0)
265 internal_addr = ioremap(addr, len);
266 if (internal_addr == NULL)
268 info->mem[n].name = name;
269 info->mem[n].addr = addr;
270 info->mem[n].internal_addr = internal_addr;
271 info->mem[n].size = len;
272 info->mem[n].memtype = UIO_MEM_PHYS;
276 /* Get pci port io resources described by bar #pci_bar in uio resource n. */
278 igbuio_pci_setup_ioport(struct pci_dev *dev, struct uio_info *info,
279 int n, int pci_bar, const char *name)
281 unsigned long addr, len;
283 if (n >= ARRAY_SIZE(info->port))
286 addr = pci_resource_start(dev, pci_bar);
287 len = pci_resource_len(dev, pci_bar);
288 if (addr == 0 || len == 0)
291 info->port[n].name = name;
292 info->port[n].start = addr;
293 info->port[n].size = len;
294 info->port[n].porttype = UIO_PORT_X86;
299 /* Unmap previously ioremap'd resources */
301 igbuio_pci_release_iomem(struct uio_info *info)
305 for (i = 0; i < MAX_UIO_MAPS; i++) {
306 if (info->mem[i].internal_addr)
307 iounmap(info->mem[i].internal_addr);
312 igbuio_setup_bars(struct pci_dev *dev, struct uio_info *info)
314 int i, iom, iop, ret;
316 static const char *bar_names[PCI_STD_RESOURCE_END + 1] = {
328 for (i = 0; i < ARRAY_SIZE(bar_names); i++) {
329 if (pci_resource_len(dev, i) != 0 &&
330 pci_resource_start(dev, i) != 0) {
331 flags = pci_resource_flags(dev, i);
332 if (flags & IORESOURCE_MEM) {
333 ret = igbuio_pci_setup_iomem(dev, info, iom,
338 } else if (flags & IORESOURCE_IO) {
339 ret = igbuio_pci_setup_ioport(dev, info, iop,
348 return (iom != 0 || iop != 0) ? ret : -ENOENT;
351 #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)
356 igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
358 struct rte_uio_pci_dev *udev;
359 #ifdef HAVE_PCI_ENABLE_MSIX
360 struct msix_entry msix_entry;
362 dma_addr_t map_dma_addr;
366 udev = kzalloc(sizeof(struct rte_uio_pci_dev), GFP_KERNEL);
371 * enable device: ask low-level code to enable I/O and
374 err = pci_enable_device(dev);
376 dev_err(&dev->dev, "Cannot enable PCI device\n");
380 /* enable bus mastering on the device */
383 /* remap IO memory */
384 err = igbuio_setup_bars(dev, &udev->info);
386 goto fail_release_iomem;
388 /* set 64-bit DMA mask */
389 err = pci_set_dma_mask(dev, DMA_BIT_MASK(64));
391 dev_err(&dev->dev, "Cannot set DMA mask\n");
392 goto fail_release_iomem;
395 err = pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64));
397 dev_err(&dev->dev, "Cannot set consistent DMA mask\n");
398 goto fail_release_iomem;
402 udev->info.name = "igb_uio";
403 udev->info.version = "0.1";
404 udev->info.handler = igbuio_pci_irqhandler;
405 udev->info.irqcontrol = igbuio_pci_irqcontrol;
406 udev->info.open = igbuio_pci_open;
407 udev->info.release = igbuio_pci_release;
408 #ifdef CONFIG_XEN_DOM0
409 /* check if the driver run on Xen Dom0 */
410 if (xen_initial_domain())
411 udev->info.mmap = igbuio_dom0_pci_mmap;
413 udev->info.priv = udev;
416 switch (igbuio_intr_mode_preferred) {
417 case RTE_INTR_MODE_MSIX:
418 /* Only 1 msi-x vector needed */
419 #ifdef HAVE_PCI_ENABLE_MSIX
420 msix_entry.entry = 0;
421 if (pci_enable_msix(dev, &msix_entry, 1) == 0) {
422 dev_dbg(&dev->dev, "using MSI-X");
423 udev->info.irq_flags = IRQF_NO_THREAD;
424 udev->info.irq = msix_entry.vector;
425 udev->mode = RTE_INTR_MODE_MSIX;
429 if (pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_MSIX) == 1) {
430 dev_dbg(&dev->dev, "using MSI-X");
431 udev->info.irq = pci_irq_vector(dev, 0);
432 udev->mode = RTE_INTR_MODE_MSIX;
436 /* fall back to INTX */
437 case RTE_INTR_MODE_LEGACY:
438 if (pci_intx_mask_supported(dev)) {
439 dev_dbg(&dev->dev, "using INTX");
440 udev->info.irq_flags = IRQF_SHARED | IRQF_NO_THREAD;
441 udev->info.irq = dev->irq;
442 udev->mode = RTE_INTR_MODE_LEGACY;
445 dev_notice(&dev->dev, "PCI INTX mask not supported\n");
446 /* fall back to no IRQ */
447 case RTE_INTR_MODE_NONE:
448 udev->mode = RTE_INTR_MODE_NONE;
453 dev_err(&dev->dev, "invalid IRQ mode %u",
454 igbuio_intr_mode_preferred);
456 goto fail_release_iomem;
459 err = sysfs_create_group(&dev->dev.kobj, &dev_attr_grp);
461 goto fail_release_iomem;
463 /* register uio driver */
464 err = uio_register_device(&dev->dev, &udev->info);
466 goto fail_remove_group;
468 pci_set_drvdata(dev, udev);
470 dev_info(&dev->dev, "uio device registered with irq %lx\n",
474 * Doing a harmless dma mapping for attaching the device to
475 * the iommu identity mapping if kernel boots with iommu=pt.
476 * Note this is not a problem if no IOMMU at all.
478 map_addr = dma_alloc_coherent(&dev->dev, 1024, &map_dma_addr,
481 memset(map_addr, 0, 1024);
484 dev_info(&dev->dev, "dma mapping failed\n");
486 dev_info(&dev->dev, "mapping 1K dma=%#llx host=%p\n",
487 (unsigned long long)map_dma_addr, map_addr);
489 dma_free_coherent(&dev->dev, 1024, map_addr, map_dma_addr);
490 dev_info(&dev->dev, "unmapping 1K dma=%#llx host=%p\n",
491 (unsigned long long)map_dma_addr, map_addr);
497 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
499 igbuio_pci_release_iomem(&udev->info);
500 if (udev->mode == RTE_INTR_MODE_MSIX)
501 pci_disable_msix(udev->pdev);
502 pci_disable_device(dev);
510 igbuio_pci_remove(struct pci_dev *dev)
512 struct rte_uio_pci_dev *udev = pci_get_drvdata(dev);
514 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
515 uio_unregister_device(&udev->info);
516 igbuio_pci_release_iomem(&udev->info);
517 if (udev->mode == RTE_INTR_MODE_MSIX)
518 pci_disable_msix(dev);
519 pci_disable_device(dev);
520 pci_set_drvdata(dev, NULL);
525 igbuio_config_intr_mode(char *intr_str)
528 pr_info("Use MSIX interrupt by default\n");
532 if (!strcmp(intr_str, RTE_INTR_MODE_MSIX_NAME)) {
533 igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
534 pr_info("Use MSIX interrupt\n");
535 } else if (!strcmp(intr_str, RTE_INTR_MODE_LEGACY_NAME)) {
536 igbuio_intr_mode_preferred = RTE_INTR_MODE_LEGACY;
537 pr_info("Use legacy interrupt\n");
539 pr_info("Error: bad parameter - %s\n", intr_str);
546 static struct pci_driver igbuio_pci_driver = {
549 .probe = igbuio_pci_probe,
550 .remove = igbuio_pci_remove,
554 igbuio_pci_init_module(void)
558 ret = igbuio_config_intr_mode(intr_mode);
562 return pci_register_driver(&igbuio_pci_driver);
566 igbuio_pci_exit_module(void)
568 pci_unregister_driver(&igbuio_pci_driver);
571 module_init(igbuio_pci_init_module);
572 module_exit(igbuio_pci_exit_module);
574 module_param(intr_mode, charp, S_IRUGO);
575 MODULE_PARM_DESC(intr_mode,
576 "igb_uio interrupt mode (default=msix):\n"
577 " " RTE_INTR_MODE_MSIX_NAME " Use MSIX interrupt\n"
578 " " RTE_INTR_MODE_LEGACY_NAME " Use Legacy interrupt\n"
581 MODULE_DESCRIPTION("UIO driver for Intel IGB PCI cards");
582 MODULE_LICENSE("GPL");
583 MODULE_AUTHOR("Intel Corporation");