4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * The full GNU General Public License is included in this distribution
19 * in the file called LICENSE.GPL.
21 * Contact Information:
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27 #include <linux/device.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/uio_driver.h>
32 #include <linux/irq.h>
33 #include <linux/msi.h>
34 #include <linux/version.h>
35 #include <linux/slab.h>
37 #include <rte_pci_dev_features.h>
42 * A structure describing the private information for a uio device.
44 struct rte_uio_pci_dev {
47 enum rte_intr_mode mode;
50 static char *intr_mode;
51 static enum rte_intr_mode igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
55 show_max_vfs(struct device *dev, struct device_attribute *attr,
58 return snprintf(buf, 10, "%u\n", dev_num_vf(dev));
62 store_max_vfs(struct device *dev, struct device_attribute *attr,
63 const char *buf, size_t count)
66 unsigned long max_vfs;
67 struct pci_dev *pdev = to_pci_dev(dev);
69 if (0 != kstrtoul(buf, 0, &max_vfs))
73 pci_disable_sriov(pdev);
74 else if (0 == pci_num_vf(pdev))
75 err = pci_enable_sriov(pdev, max_vfs);
76 else /* do nothing if change max_vfs number */
79 return err ? err : count;
82 static DEVICE_ATTR(max_vfs, S_IRUGO | S_IWUSR, show_max_vfs, store_max_vfs);
84 static struct attribute *dev_attrs[] = {
85 &dev_attr_max_vfs.attr,
89 static const struct attribute_group dev_attr_grp = {
93 #ifndef HAVE_PCI_MSI_MASK_IRQ
95 * It masks the msix on/off of generating MSI-X messages.
98 igbuio_msix_mask_irq(struct msi_desc *desc, s32 state)
100 u32 mask_bits = desc->masked;
101 unsigned int offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
102 PCI_MSIX_ENTRY_VECTOR_CTRL;
105 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
107 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
109 if (mask_bits != desc->masked) {
110 writel(mask_bits, desc->mask_base + offset);
111 readl(desc->mask_base);
112 desc->masked = mask_bits;
117 * It masks the msi on/off of generating MSI messages.
120 igbuio_msi_mask_irq(struct pci_dev *pdev, struct msi_desc *desc, int32_t state)
122 u32 mask_bits = desc->masked;
123 u32 offset = desc->irq - pdev->irq;
124 u32 mask = 1 << offset;
125 u32 flag = !!state << offset;
127 if (!desc->msi_attrib.maskbit)
133 if (mask_bits != desc->masked) {
134 pci_write_config_dword(pdev, desc->mask_pos, mask_bits);
135 desc->masked = mask_bits;
140 igbuio_mask_irq(struct pci_dev *pdev, enum rte_intr_mode mode, s32 irq_state)
142 struct msi_desc *desc;
143 struct list_head *msi_list;
145 #ifdef HAVE_MSI_LIST_IN_GENERIC_DEVICE
146 msi_list = &pdev->dev.msi_list;
148 msi_list = &pdev->msi_list;
151 if (mode == RTE_INTR_MODE_MSIX) {
152 list_for_each_entry(desc, msi_list, list)
153 igbuio_msix_mask_irq(desc, irq_state);
154 } else if (mode == RTE_INTR_MODE_MSI) {
155 list_for_each_entry(desc, msi_list, list)
156 igbuio_msi_mask_irq(pdev, desc, irq_state);
162 * This is the irqcontrol callback to be registered to uio_info.
163 * It can be used to disable/enable interrupt from user space processes.
166 * pointer to uio_info.
168 * state value. 1 to enable interrupt, 0 to disable interrupt.
172 * - On failure, a negative value.
175 igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
177 struct rte_uio_pci_dev *udev = info->priv;
178 struct pci_dev *pdev = udev->pdev;
180 #ifdef HAVE_PCI_MSI_MASK_IRQ
181 struct irq_data *irq = irq_get_irq_data(udev->info.irq);
184 pci_cfg_access_lock(pdev);
186 if (udev->mode == RTE_INTR_MODE_MSIX || udev->mode == RTE_INTR_MODE_MSI) {
187 #ifdef HAVE_PCI_MSI_MASK_IRQ
189 pci_msi_unmask_irq(irq);
191 pci_msi_mask_irq(irq);
193 igbuio_mask_irq(pdev, udev->mode, irq_state);
197 if (udev->mode == RTE_INTR_MODE_LEGACY)
198 pci_intx(pdev, !!irq_state);
200 pci_cfg_access_unlock(pdev);
206 * This is interrupt handler which will check if the interrupt is for the right device.
207 * If yes, disable it here and will be enable later.
210 igbuio_pci_irqhandler(int irq, struct uio_info *info)
212 struct rte_uio_pci_dev *udev = info->priv;
214 /* Legacy mode need to mask in hardware */
215 if (udev->mode == RTE_INTR_MODE_LEGACY &&
216 !pci_check_and_mask_intx(udev->pdev))
219 /* Message signal mode, no share IRQ and automasked */
224 * This gets called while opening uio device file.
227 igbuio_pci_open(struct uio_info *info, struct inode *inode)
229 struct rte_uio_pci_dev *udev = info->priv;
230 struct pci_dev *dev = udev->pdev;
232 pci_reset_function(dev);
234 /* set bus master, which was cleared by the reset function */
241 igbuio_pci_release(struct uio_info *info, struct inode *inode)
243 struct rte_uio_pci_dev *udev = info->priv;
244 struct pci_dev *dev = udev->pdev;
246 /* stop the device from further DMA */
247 pci_clear_master(dev);
249 pci_reset_function(dev);
254 /* Remap pci resources described by bar #pci_bar in uio resource n. */
256 igbuio_pci_setup_iomem(struct pci_dev *dev, struct uio_info *info,
257 int n, int pci_bar, const char *name)
259 unsigned long addr, len;
262 if (n >= ARRAY_SIZE(info->mem))
265 addr = pci_resource_start(dev, pci_bar);
266 len = pci_resource_len(dev, pci_bar);
267 if (addr == 0 || len == 0)
269 internal_addr = ioremap(addr, len);
270 if (internal_addr == NULL)
272 info->mem[n].name = name;
273 info->mem[n].addr = addr;
274 info->mem[n].internal_addr = internal_addr;
275 info->mem[n].size = len;
276 info->mem[n].memtype = UIO_MEM_PHYS;
280 /* Get pci port io resources described by bar #pci_bar in uio resource n. */
282 igbuio_pci_setup_ioport(struct pci_dev *dev, struct uio_info *info,
283 int n, int pci_bar, const char *name)
285 unsigned long addr, len;
287 if (n >= ARRAY_SIZE(info->port))
290 addr = pci_resource_start(dev, pci_bar);
291 len = pci_resource_len(dev, pci_bar);
292 if (addr == 0 || len == 0)
295 info->port[n].name = name;
296 info->port[n].start = addr;
297 info->port[n].size = len;
298 info->port[n].porttype = UIO_PORT_X86;
303 /* Unmap previously ioremap'd resources */
305 igbuio_pci_release_iomem(struct uio_info *info)
309 for (i = 0; i < MAX_UIO_MAPS; i++) {
310 if (info->mem[i].internal_addr)
311 iounmap(info->mem[i].internal_addr);
316 igbuio_pci_enable_interrupts(struct rte_uio_pci_dev *udev)
319 #ifndef HAVE_ALLOC_IRQ_VECTORS
320 struct msix_entry msix_entry;
323 switch (igbuio_intr_mode_preferred) {
324 case RTE_INTR_MODE_MSIX:
325 /* Only 1 msi-x vector needed */
326 #ifndef HAVE_ALLOC_IRQ_VECTORS
327 msix_entry.entry = 0;
328 if (pci_enable_msix(udev->pdev, &msix_entry, 1) == 0) {
329 dev_dbg(&udev->pdev->dev, "using MSI-X");
330 udev->info.irq_flags = IRQF_NO_THREAD;
331 udev->info.irq = msix_entry.vector;
332 udev->mode = RTE_INTR_MODE_MSIX;
336 if (pci_alloc_irq_vectors(udev->pdev, 1, 1, PCI_IRQ_MSIX) == 1) {
337 dev_dbg(&udev->pdev->dev, "using MSI-X");
338 udev->info.irq_flags = IRQF_NO_THREAD;
339 udev->info.irq = pci_irq_vector(udev->pdev, 0);
340 udev->mode = RTE_INTR_MODE_MSIX;
344 /* fall back to MSI */
345 case RTE_INTR_MODE_MSI:
346 #ifndef HAVE_ALLOC_IRQ_VECTORS
347 if (pci_enable_msi(udev->pdev) == 0) {
348 dev_dbg(&udev->pdev->dev, "using MSI");
349 udev->info.irq_flags = IRQF_NO_THREAD;
350 udev->info.irq = udev->pdev->irq;
351 udev->mode = RTE_INTR_MODE_MSI;
355 if (pci_alloc_irq_vectors(udev->pdev, 1, 1, PCI_IRQ_MSI) == 1) {
356 dev_dbg(&udev->pdev->dev, "using MSI");
357 udev->info.irq_flags = IRQF_NO_THREAD;
358 udev->info.irq = pci_irq_vector(udev->pdev, 0);
359 udev->mode = RTE_INTR_MODE_MSI;
363 /* fall back to INTX */
364 case RTE_INTR_MODE_LEGACY:
365 if (pci_intx_mask_supported(udev->pdev)) {
366 dev_dbg(&udev->pdev->dev, "using INTX");
367 udev->info.irq_flags = IRQF_SHARED | IRQF_NO_THREAD;
368 udev->info.irq = udev->pdev->irq;
369 udev->mode = RTE_INTR_MODE_LEGACY;
372 dev_notice(&udev->pdev->dev, "PCI INTX mask not supported\n");
373 /* fall back to no IRQ */
374 case RTE_INTR_MODE_NONE:
375 udev->mode = RTE_INTR_MODE_NONE;
376 udev->info.irq = UIO_IRQ_NONE;
380 dev_err(&udev->pdev->dev, "invalid IRQ mode %u",
381 igbuio_intr_mode_preferred);
389 igbuio_pci_disable_interrupts(struct rte_uio_pci_dev *udev)
391 #ifndef HAVE_ALLOC_IRQ_VECTORS
392 if (udev->mode == RTE_INTR_MODE_MSIX)
393 pci_disable_msix(udev->pdev);
394 if (udev->mode == RTE_INTR_MODE_MSI)
395 pci_disable_msi(udev->pdev);
397 if (udev->mode == RTE_INTR_MODE_MSIX ||
398 udev->mode == RTE_INTR_MODE_MSI)
399 pci_free_irq_vectors(udev->pdev);
404 igbuio_setup_bars(struct pci_dev *dev, struct uio_info *info)
406 int i, iom, iop, ret;
408 static const char *bar_names[PCI_STD_RESOURCE_END + 1] = {
420 for (i = 0; i < ARRAY_SIZE(bar_names); i++) {
421 if (pci_resource_len(dev, i) != 0 &&
422 pci_resource_start(dev, i) != 0) {
423 flags = pci_resource_flags(dev, i);
424 if (flags & IORESOURCE_MEM) {
425 ret = igbuio_pci_setup_iomem(dev, info, iom,
430 } else if (flags & IORESOURCE_IO) {
431 ret = igbuio_pci_setup_ioport(dev, info, iop,
440 return (iom != 0 || iop != 0) ? ret : -ENOENT;
443 #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)
448 igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
450 struct rte_uio_pci_dev *udev;
451 dma_addr_t map_dma_addr;
455 udev = kzalloc(sizeof(struct rte_uio_pci_dev), GFP_KERNEL);
460 * enable device: ask low-level code to enable I/O and
463 err = pci_enable_device(dev);
465 dev_err(&dev->dev, "Cannot enable PCI device\n");
469 /* enable bus mastering on the device */
472 /* remap IO memory */
473 err = igbuio_setup_bars(dev, &udev->info);
475 goto fail_release_iomem;
477 /* set 64-bit DMA mask */
478 err = pci_set_dma_mask(dev, DMA_BIT_MASK(64));
480 dev_err(&dev->dev, "Cannot set DMA mask\n");
481 goto fail_release_iomem;
484 err = pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64));
486 dev_err(&dev->dev, "Cannot set consistent DMA mask\n");
487 goto fail_release_iomem;
491 udev->info.name = "igb_uio";
492 udev->info.version = "0.1";
493 udev->info.handler = igbuio_pci_irqhandler;
494 udev->info.irqcontrol = igbuio_pci_irqcontrol;
495 udev->info.open = igbuio_pci_open;
496 udev->info.release = igbuio_pci_release;
497 udev->info.priv = udev;
500 err = igbuio_pci_enable_interrupts(udev);
502 goto fail_release_iomem;
504 err = sysfs_create_group(&dev->dev.kobj, &dev_attr_grp);
506 goto fail_disable_interrupts;
508 /* register uio driver */
509 err = uio_register_device(&dev->dev, &udev->info);
511 goto fail_remove_group;
513 pci_set_drvdata(dev, udev);
515 dev_info(&dev->dev, "uio device registered with irq %lx\n",
519 * Doing a harmless dma mapping for attaching the device to
520 * the iommu identity mapping if kernel boots with iommu=pt.
521 * Note this is not a problem if no IOMMU at all.
523 map_addr = dma_alloc_coherent(&dev->dev, 1024, &map_dma_addr,
526 memset(map_addr, 0, 1024);
529 dev_info(&dev->dev, "dma mapping failed\n");
531 dev_info(&dev->dev, "mapping 1K dma=%#llx host=%p\n",
532 (unsigned long long)map_dma_addr, map_addr);
534 dma_free_coherent(&dev->dev, 1024, map_addr, map_dma_addr);
535 dev_info(&dev->dev, "unmapping 1K dma=%#llx host=%p\n",
536 (unsigned long long)map_dma_addr, map_addr);
542 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
543 fail_disable_interrupts:
544 igbuio_pci_disable_interrupts(udev);
546 igbuio_pci_release_iomem(&udev->info);
547 pci_disable_device(dev);
555 igbuio_pci_remove(struct pci_dev *dev)
557 struct rte_uio_pci_dev *udev = pci_get_drvdata(dev);
559 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
560 uio_unregister_device(&udev->info);
561 igbuio_pci_disable_interrupts(udev);
562 igbuio_pci_release_iomem(&udev->info);
563 pci_disable_device(dev);
564 pci_set_drvdata(dev, NULL);
569 igbuio_config_intr_mode(char *intr_str)
572 pr_info("Use MSIX interrupt by default\n");
576 if (!strcmp(intr_str, RTE_INTR_MODE_MSIX_NAME)) {
577 igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
578 pr_info("Use MSIX interrupt\n");
579 } else if (!strcmp(intr_str, RTE_INTR_MODE_MSI_NAME)) {
580 igbuio_intr_mode_preferred = RTE_INTR_MODE_MSI;
581 pr_info("Use MSI interrupt\n");
582 } else if (!strcmp(intr_str, RTE_INTR_MODE_LEGACY_NAME)) {
583 igbuio_intr_mode_preferred = RTE_INTR_MODE_LEGACY;
584 pr_info("Use legacy interrupt\n");
586 pr_info("Error: bad parameter - %s\n", intr_str);
593 static struct pci_driver igbuio_pci_driver = {
596 .probe = igbuio_pci_probe,
597 .remove = igbuio_pci_remove,
601 igbuio_pci_init_module(void)
605 ret = igbuio_config_intr_mode(intr_mode);
609 return pci_register_driver(&igbuio_pci_driver);
613 igbuio_pci_exit_module(void)
615 pci_unregister_driver(&igbuio_pci_driver);
618 module_init(igbuio_pci_init_module);
619 module_exit(igbuio_pci_exit_module);
621 module_param(intr_mode, charp, S_IRUGO);
622 MODULE_PARM_DESC(intr_mode,
623 "igb_uio interrupt mode (default=msix):\n"
624 " " RTE_INTR_MODE_MSIX_NAME " Use MSIX interrupt\n"
625 " " RTE_INTR_MODE_MSI_NAME " Use MSI interrupt\n"
626 " " RTE_INTR_MODE_LEGACY_NAME " Use Legacy interrupt\n"
629 MODULE_DESCRIPTION("UIO driver for Intel IGB PCI cards");
630 MODULE_LICENSE("GPL");
631 MODULE_AUTHOR("Intel Corporation");