4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * The full GNU General Public License is included in this distribution
19 * in the file called LICENSE.GPL.
21 * Contact Information:
25 #include <linux/device.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/uio_driver.h>
30 #include <linux/msi.h>
31 #include <linux/version.h>
33 #ifdef CONFIG_XEN_DOM0
38 * MSI-X related macros, copy from linux/pci_regs.h in kernel 2.6.39,
39 * but none of them in kernel 2.6.35.
41 #ifndef PCI_MSIX_ENTRY_SIZE
42 #define PCI_MSIX_ENTRY_SIZE 16
43 #define PCI_MSIX_ENTRY_LOWER_ADDR 0
44 #define PCI_MSIX_ENTRY_UPPER_ADDR 4
45 #define PCI_MSIX_ENTRY_DATA 8
46 #define PCI_MSIX_ENTRY_VECTOR_CTRL 12
47 #define PCI_MSIX_ENTRY_CTRL_MASKBIT 1
50 #define IGBUIO_NUM_MSI_VECTORS 1
53 enum igbuio_intr_mode {
54 IGBUIO_LEGACY_INTR_MODE = 0,
56 IGBUIO_MSIX_INTR_MODE,
61 * A structure describing the private information for a uio device.
63 struct rte_uio_pci_dev {
66 spinlock_t lock; /* spinlock for accessing PCI config space or msix data in multi tasks/isr */
67 enum igbuio_intr_mode mode;
69 msix_entries[IGBUIO_NUM_MSI_VECTORS]; /* pointer to the msix vectors to be allocated later */
72 static char *intr_mode = NULL;
73 static enum igbuio_intr_mode igbuio_intr_mode_preferred = IGBUIO_MSIX_INTR_MODE;
75 /* PCI device id table */
76 static struct pci_device_id igbuio_pci_ids[] = {
77 #define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {PCI_DEVICE(vend, dev)},
78 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {PCI_DEVICE(vend, dev)},
79 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {PCI_DEVICE(vend, dev)},
80 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {PCI_DEVICE(vend, dev)},
81 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {PCI_DEVICE(vend, dev)},
82 #define RTE_PCI_DEV_ID_DECL_VIRTIO(vend, dev) {PCI_DEVICE(vend, dev)},
83 #define RTE_PCI_DEV_ID_DECL_VMXNET3(vend, dev) {PCI_DEVICE(vend, dev)},
84 #include <rte_pci_dev_ids.h>
88 MODULE_DEVICE_TABLE(pci, igbuio_pci_ids);
90 static inline struct rte_uio_pci_dev *
91 igbuio_get_uio_pci_dev(struct uio_info *info)
93 return container_of(info, struct rte_uio_pci_dev, info);
97 int local_pci_num_vf(struct pci_dev *dev)
99 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34)
108 } *iov = (struct iov*)dev->sriov;
113 return iov->nr_virtfn;
115 return pci_num_vf(dev);
120 show_max_vfs(struct device *dev, struct device_attribute *attr,
123 return snprintf(buf, 10, "%u\n", local_pci_num_vf(
124 container_of(dev, struct pci_dev, dev)));
128 store_max_vfs(struct device *dev, struct device_attribute *attr,
129 const char *buf, size_t count)
132 unsigned long max_vfs;
133 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
135 if (0 != strict_strtoul(buf, 0, &max_vfs))
139 pci_disable_sriov(pdev);
140 else if (0 == local_pci_num_vf(pdev))
141 err = pci_enable_sriov(pdev, max_vfs);
142 else /* do nothing if change max_vfs number */
145 return err ? err : count;
148 static DEVICE_ATTR(max_vfs, S_IRUGO | S_IWUSR, show_max_vfs, store_max_vfs);
149 static struct attribute *dev_attrs[] = {
150 &dev_attr_max_vfs.attr,
154 static const struct attribute_group dev_attr_grp = {
159 pci_lock(struct pci_dev * pdev)
161 /* Some function names changes between 3.2.0 and 3.3.0... */
162 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0)
163 pci_block_user_cfg_access(pdev);
166 return pci_cfg_access_trylock(pdev);
171 pci_unlock(struct pci_dev * pdev)
173 /* Some function names changes between 3.2.0 and 3.3.0... */
174 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0)
175 pci_unblock_user_cfg_access(pdev);
177 pci_cfg_access_unlock(pdev);
182 * It masks the msix on/off of generating MSI-X messages.
185 igbuio_msix_mask_irq(struct msi_desc *desc, int32_t state)
187 uint32_t mask_bits = desc->masked;
188 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
189 PCI_MSIX_ENTRY_VECTOR_CTRL;
192 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
194 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
196 if (mask_bits != desc->masked) {
197 writel(mask_bits, desc->mask_base + offset);
198 readl(desc->mask_base);
199 desc->masked = mask_bits;
206 * This function sets/clears the masks for generating LSC interrupts.
209 * The pointer to struct uio_info.
211 * The on/off flag of masking LSC.
213 * -On success, zero value.
214 * -On failure, a negative value.
217 igbuio_set_interrupt_mask(struct rte_uio_pci_dev *udev, int32_t state)
219 struct pci_dev *pdev = udev->pdev;
221 if (udev->mode == IGBUIO_MSIX_INTR_MODE) {
222 struct msi_desc *desc;
224 list_for_each_entry(desc, &pdev->msi_list, list) {
225 igbuio_msix_mask_irq(desc, state);
228 else if (udev->mode == IGBUIO_LEGACY_INTR_MODE) {
232 pci_read_config_dword(pdev, PCI_COMMAND, &status);
235 new = old & (~PCI_COMMAND_INTX_DISABLE);
237 new = old | PCI_COMMAND_INTX_DISABLE;
240 pci_write_config_word(pdev, PCI_COMMAND, new);
247 * This is the irqcontrol callback to be registered to uio_info.
248 * It can be used to disable/enable interrupt from user space processes.
251 * pointer to uio_info.
253 * state value. 1 to enable interrupt, 0 to disable interrupt.
257 * - On failure, a negative value.
260 igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
263 struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
264 struct pci_dev *pdev = udev->pdev;
266 spin_lock_irqsave(&udev->lock, flags);
267 if (!pci_lock(pdev)) {
268 spin_unlock_irqrestore(&udev->lock, flags);
272 igbuio_set_interrupt_mask(udev, irq_state);
275 spin_unlock_irqrestore(&udev->lock, flags);
281 * This is interrupt handler which will check if the interrupt is for the right device.
282 * If yes, disable it here and will be enable later.
285 igbuio_pci_irqhandler(int irq, struct uio_info *info)
287 irqreturn_t ret = IRQ_NONE;
289 struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
290 struct pci_dev *pdev = udev->pdev;
291 uint32_t cmd_status_dword;
294 spin_lock_irqsave(&udev->lock, flags);
295 /* block userspace PCI config reads/writes */
299 /* for legacy mode, interrupt maybe shared */
300 if (udev->mode == IGBUIO_LEGACY_INTR_MODE) {
301 pci_read_config_dword(pdev, PCI_COMMAND, &cmd_status_dword);
302 status = cmd_status_dword >> 16;
303 /* interrupt is not ours, goes to out */
304 if (!(status & PCI_STATUS_INTERRUPT))
308 igbuio_set_interrupt_mask(udev, 0);
311 /* unblock userspace PCI config reads/writes */
314 spin_unlock_irqrestore(&udev->lock, flags);
315 printk(KERN_INFO "irq 0x%x %s\n", irq, (ret == IRQ_HANDLED) ? "handled" : "not handled");
320 #ifdef CONFIG_XEN_DOM0
322 igbuio_dom0_mmap_phys(struct uio_info *info, struct vm_area_struct *vma)
325 idx = (int)vma->vm_pgoff;
326 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
327 vma->vm_page_prot.pgprot |= _PAGE_IOMAP;
329 return remap_pfn_range(vma,
331 info->mem[idx].addr >> PAGE_SHIFT,
332 vma->vm_end - vma->vm_start,
337 * This is uio device mmap method which will use igbuio mmap for Xen
341 igbuio_dom0_pci_mmap(struct uio_info *info, struct vm_area_struct *vma)
345 if (vma->vm_pgoff >= MAX_UIO_MAPS)
347 if(info->mem[vma->vm_pgoff].size == 0)
350 idx = (int)vma->vm_pgoff;
351 switch (info->mem[idx].memtype) {
353 return igbuio_dom0_mmap_phys(info, vma);
354 case UIO_MEM_LOGICAL:
355 case UIO_MEM_VIRTUAL:
362 /* Remap pci resources described by bar #pci_bar in uio resource n. */
364 igbuio_pci_setup_iomem(struct pci_dev *dev, struct uio_info *info,
365 int n, int pci_bar, const char *name)
367 unsigned long addr, len;
370 if (sizeof(info->mem) / sizeof (info->mem[0]) <= n)
373 addr = pci_resource_start(dev, pci_bar);
374 len = pci_resource_len(dev, pci_bar);
375 if (addr == 0 || len == 0)
377 internal_addr = ioremap(addr, len);
378 if (internal_addr == NULL)
380 info->mem[n].name = name;
381 info->mem[n].addr = addr;
382 info->mem[n].internal_addr = internal_addr;
383 info->mem[n].size = len;
384 info->mem[n].memtype = UIO_MEM_PHYS;
388 /* Get pci port io resources described by bar #pci_bar in uio resource n. */
390 igbuio_pci_setup_ioport(struct pci_dev *dev, struct uio_info *info,
391 int n, int pci_bar, const char *name)
393 unsigned long addr, len;
395 if (sizeof(info->port) / sizeof (info->port[0]) <= n)
398 addr = pci_resource_start(dev, pci_bar);
399 len = pci_resource_len(dev, pci_bar);
400 if (addr == 0 || len == 0)
403 info->port[n].name = name;
404 info->port[n].start = addr;
405 info->port[n].size = len;
406 info->port[n].porttype = UIO_PORT_X86;
411 /* Unmap previously ioremap'd resources */
413 igbuio_pci_release_iomem(struct uio_info *info)
416 for (i = 0; i < MAX_UIO_MAPS; i++) {
417 if (info->mem[i].internal_addr)
418 iounmap(info->mem[i].internal_addr);
423 igbuio_setup_bars(struct pci_dev *dev, struct uio_info *info)
425 int i, iom, iop, ret;
427 static const char *bar_names[PCI_STD_RESOURCE_END + 1] = {
439 for (i = 0; i != sizeof(bar_names) / sizeof(bar_names[0]); i++) {
440 if (pci_resource_len(dev, i) != 0 &&
441 pci_resource_start(dev, i) != 0) {
442 flags = pci_resource_flags(dev, i);
443 if (flags & IORESOURCE_MEM) {
444 if ((ret = igbuio_pci_setup_iomem(dev, info,
445 iom, i, bar_names[i])) != 0)
448 } else if (flags & IORESOURCE_IO) {
449 if ((ret = igbuio_pci_setup_ioport(dev, info,
450 iop, i, bar_names[i])) != 0)
457 return ((iom != 0) ? ret : ENOENT);
460 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0)
465 igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
467 struct rte_uio_pci_dev *udev;
469 udev = kzalloc(sizeof(struct rte_uio_pci_dev), GFP_KERNEL);
474 * enable device: ask low-level code to enable I/O and
477 if (pci_enable_device(dev)) {
478 printk(KERN_ERR "Cannot enable PCI device\n");
483 * reserve device's PCI memory regions for use by this
486 if (pci_request_regions(dev, "igb_uio")) {
487 printk(KERN_ERR "Cannot request regions\n");
491 /* enable bus mastering on the device */
494 /* remap IO memory */
495 if (igbuio_setup_bars(dev, &udev->info))
496 goto fail_release_iomem;
498 /* set 64-bit DMA mask */
499 if (pci_set_dma_mask(dev, DMA_BIT_MASK(64))) {
500 printk(KERN_ERR "Cannot set DMA mask\n");
501 goto fail_release_iomem;
502 } else if (pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64))) {
503 printk(KERN_ERR "Cannot set consistent DMA mask\n");
504 goto fail_release_iomem;
508 udev->info.name = "Intel IGB UIO";
509 udev->info.version = "0.1";
510 udev->info.handler = igbuio_pci_irqhandler;
511 udev->info.irqcontrol = igbuio_pci_irqcontrol;
512 #ifdef CONFIG_XEN_DOM0
513 /* check if the driver run on Xen Dom0 */
514 if (xen_initial_domain())
515 udev->info.mmap = igbuio_dom0_pci_mmap;
517 udev->info.priv = udev;
519 udev->mode = 0; /* set the default value for interrupt mode */
520 spin_lock_init(&udev->lock);
522 /* check if it need to try msix first */
523 if (igbuio_intr_mode_preferred == IGBUIO_MSIX_INTR_MODE) {
526 for (vector = 0; vector < IGBUIO_NUM_MSI_VECTORS; vector ++)
527 udev->msix_entries[vector].entry = vector;
529 if (pci_enable_msix(udev->pdev, udev->msix_entries, IGBUIO_NUM_MSI_VECTORS) == 0) {
530 udev->mode = IGBUIO_MSIX_INTR_MODE;
533 pci_disable_msix(udev->pdev);
534 printk(KERN_INFO "fail to enable pci msix, or not enough msix entries\n");
537 switch (udev->mode) {
538 case IGBUIO_MSIX_INTR_MODE:
539 udev->info.irq_flags = 0;
540 udev->info.irq = udev->msix_entries[0].vector;
542 case IGBUIO_MSI_INTR_MODE:
544 case IGBUIO_LEGACY_INTR_MODE:
545 udev->info.irq_flags = IRQF_SHARED;
546 udev->info.irq = dev->irq;
552 pci_set_drvdata(dev, udev);
553 igbuio_pci_irqcontrol(&udev->info, 0);
555 if (sysfs_create_group(&dev->dev.kobj, &dev_attr_grp))
556 goto fail_release_iomem;
558 /* register uio driver */
559 if (uio_register_device(&dev->dev, &udev->info))
560 goto fail_release_iomem;
562 printk(KERN_INFO "uio device registered with irq %lx\n", udev->info.irq);
567 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
568 igbuio_pci_release_iomem(&udev->info);
569 if (udev->mode == IGBUIO_MSIX_INTR_MODE)
570 pci_disable_msix(udev->pdev);
571 pci_release_regions(dev);
573 pci_disable_device(dev);
581 igbuio_pci_remove(struct pci_dev *dev)
583 struct uio_info *info = pci_get_drvdata(dev);
585 if (info->priv == NULL) {
586 printk(KERN_DEBUG "Not igbuio device\n");
590 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
591 uio_unregister_device(info);
592 igbuio_pci_release_iomem(info);
593 if (((struct rte_uio_pci_dev *)info->priv)->mode ==
594 IGBUIO_MSIX_INTR_MODE)
595 pci_disable_msix(dev);
596 pci_release_regions(dev);
597 pci_disable_device(dev);
598 pci_set_drvdata(dev, NULL);
603 igbuio_config_intr_mode(char *intr_str)
606 printk(KERN_INFO "Use MSIX interrupt by default\n");
610 if (!strcmp(intr_str, "msix")) {
611 igbuio_intr_mode_preferred = IGBUIO_MSIX_INTR_MODE;
612 printk(KERN_INFO "Use MSIX interrupt\n");
613 } else if (!strcmp(intr_str, "legacy")) {
614 igbuio_intr_mode_preferred = IGBUIO_LEGACY_INTR_MODE;
615 printk(KERN_INFO "Use legacy interrupt\n");
617 printk(KERN_INFO "Error: bad parameter - %s\n", intr_str);
624 static struct pci_driver igbuio_pci_driver = {
626 .id_table = igbuio_pci_ids,
627 .probe = igbuio_pci_probe,
628 .remove = igbuio_pci_remove,
632 igbuio_pci_init_module(void)
636 ret = igbuio_config_intr_mode(intr_mode);
640 return pci_register_driver(&igbuio_pci_driver);
644 igbuio_pci_exit_module(void)
646 pci_unregister_driver(&igbuio_pci_driver);
649 module_init(igbuio_pci_init_module);
650 module_exit(igbuio_pci_exit_module);
652 module_param(intr_mode, charp, S_IRUGO | S_IWUSR);
653 MODULE_PARM_DESC(intr_mode,
654 "igb_uio interrupt mode (default=msix):\n"
655 " msix Use MSIX interrupt\n"
656 " legacy Use Legacy interrupt\n"
659 MODULE_DESCRIPTION("UIO driver for Intel IGB PCI cards");
660 MODULE_LICENSE("GPL");
661 MODULE_AUTHOR("Intel Corporation");