4 * Copyright(c) 2010-2013 Intel Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * The full GNU General Public License is included in this distribution
19 * in the file called LICENSE.GPL.
21 * Contact Information:
25 #include <linux/device.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/uio_driver.h>
30 #include <linux/msi.h>
31 #include <linux/version.h>
34 * MSI-X related macros, copy from linux/pci_regs.h in kernel 2.6.39,
35 * but none of them in kernel 2.6.35.
37 #ifndef PCI_MSIX_ENTRY_SIZE
38 #define PCI_MSIX_ENTRY_SIZE 16
39 #define PCI_MSIX_ENTRY_LOWER_ADDR 0
40 #define PCI_MSIX_ENTRY_UPPER_ADDR 4
41 #define PCI_MSIX_ENTRY_DATA 8
42 #define PCI_MSIX_ENTRY_VECTOR_CTRL 12
43 #define PCI_MSIX_ENTRY_CTRL_MASKBIT 1
46 #define IGBUIO_NUM_MSI_VECTORS 1
49 enum igbuio_intr_mode {
50 IGBUIO_LEGACY_INTR_MODE = 0,
52 IGBUIO_MSIX_INTR_MODE,
57 * A structure describing the private information for a uio device.
59 struct rte_uio_pci_dev {
62 spinlock_t lock; /* spinlock for accessing PCI config space or msix data in multi tasks/isr */
63 enum igbuio_intr_mode mode;
65 msix_entries[IGBUIO_NUM_MSI_VECTORS]; /* pointer to the msix vectors to be allocated later */
68 static char *intr_mode = NULL;
69 static enum igbuio_intr_mode igbuio_intr_mode_preferred = IGBUIO_MSIX_INTR_MODE;
71 /* PCI device id table */
72 static struct pci_device_id igbuio_pci_ids[] = {
73 #define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {PCI_DEVICE(vend, dev)},
74 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {PCI_DEVICE(vend, dev)},
75 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {PCI_DEVICE(vend, dev)},
76 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {PCI_DEVICE(vend, dev)},
77 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {PCI_DEVICE(vend, dev)},
78 #define RTE_PCI_DEV_ID_DECL_VIRTIO(vend, dev) {PCI_DEVICE(vend, dev)},
79 #include <rte_pci_dev_ids.h>
83 MODULE_DEVICE_TABLE(pci, igbuio_pci_ids);
85 static inline struct rte_uio_pci_dev *
86 igbuio_get_uio_pci_dev(struct uio_info *info)
88 return container_of(info, struct rte_uio_pci_dev, info);
92 int local_pci_num_vf(struct pci_dev *dev)
94 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34)
103 } *iov = (struct iov*)dev->sriov;
108 return iov->nr_virtfn;
110 return pci_num_vf(dev);
115 show_max_vfs(struct device *dev, struct device_attribute *attr,
118 return snprintf(buf, 10, "%u\n", local_pci_num_vf(
119 container_of(dev, struct pci_dev, dev)));
123 store_max_vfs(struct device *dev, struct device_attribute *attr,
124 const char *buf, size_t count)
127 unsigned long max_vfs;
128 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
130 if (0 != strict_strtoul(buf, 0, &max_vfs))
134 pci_disable_sriov(pdev);
135 else if (0 == local_pci_num_vf(pdev))
136 err = pci_enable_sriov(pdev, max_vfs);
137 else /* do nothing if change max_vfs number */
140 return err ? err : count;
143 static DEVICE_ATTR(max_vfs, S_IRUGO | S_IWUSR, show_max_vfs, store_max_vfs);
144 static struct attribute *dev_attrs[] = {
145 &dev_attr_max_vfs.attr,
149 static const struct attribute_group dev_attr_grp = {
154 pci_lock(struct pci_dev * pdev)
156 /* Some function names changes between 3.2.0 and 3.3.0... */
157 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0)
158 pci_block_user_cfg_access(pdev);
161 return pci_cfg_access_trylock(pdev);
166 pci_unlock(struct pci_dev * pdev)
168 /* Some function names changes between 3.2.0 and 3.3.0... */
169 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0)
170 pci_unblock_user_cfg_access(pdev);
172 pci_cfg_access_unlock(pdev);
177 * It masks the msix on/off of generating MSI-X messages.
180 igbuio_msix_mask_irq(struct msi_desc *desc, int32_t state)
182 uint32_t mask_bits = desc->masked;
183 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
184 PCI_MSIX_ENTRY_VECTOR_CTRL;
187 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
189 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
191 if (mask_bits != desc->masked) {
192 writel(mask_bits, desc->mask_base + offset);
193 readl(desc->mask_base);
194 desc->masked = mask_bits;
201 * This function sets/clears the masks for generating LSC interrupts.
204 * The pointer to struct uio_info.
206 * The on/off flag of masking LSC.
208 * -On success, zero value.
209 * -On failure, a negative value.
212 igbuio_set_interrupt_mask(struct rte_uio_pci_dev *udev, int32_t state)
214 struct pci_dev *pdev = udev->pdev;
216 if (udev->mode == IGBUIO_MSIX_INTR_MODE) {
217 struct msi_desc *desc;
219 list_for_each_entry(desc, &pdev->msi_list, list) {
220 igbuio_msix_mask_irq(desc, state);
223 else if (udev->mode == IGBUIO_LEGACY_INTR_MODE) {
227 pci_read_config_dword(pdev, PCI_COMMAND, &status);
230 new = old & (~PCI_COMMAND_INTX_DISABLE);
232 new = old | PCI_COMMAND_INTX_DISABLE;
235 pci_write_config_word(pdev, PCI_COMMAND, new);
242 * This is the irqcontrol callback to be registered to uio_info.
243 * It can be used to disable/enable interrupt from user space processes.
246 * pointer to uio_info.
248 * state value. 1 to enable interrupt, 0 to disable interrupt.
252 * - On failure, a negative value.
255 igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
258 struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
259 struct pci_dev *pdev = udev->pdev;
261 spin_lock_irqsave(&udev->lock, flags);
262 if (!pci_lock(pdev)) {
263 spin_unlock_irqrestore(&udev->lock, flags);
267 igbuio_set_interrupt_mask(udev, irq_state);
270 spin_unlock_irqrestore(&udev->lock, flags);
276 * This is interrupt handler which will check if the interrupt is for the right device.
277 * If yes, disable it here and will be enable later.
280 igbuio_pci_irqhandler(int irq, struct uio_info *info)
282 irqreturn_t ret = IRQ_NONE;
284 struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
285 struct pci_dev *pdev = udev->pdev;
286 uint32_t cmd_status_dword;
289 spin_lock_irqsave(&udev->lock, flags);
290 /* block userspace PCI config reads/writes */
294 /* for legacy mode, interrupt maybe shared */
295 if (udev->mode == IGBUIO_LEGACY_INTR_MODE) {
296 pci_read_config_dword(pdev, PCI_COMMAND, &cmd_status_dword);
297 status = cmd_status_dword >> 16;
298 /* interrupt is not ours, goes to out */
299 if (!(status & PCI_STATUS_INTERRUPT))
303 igbuio_set_interrupt_mask(udev, 0);
306 /* unblock userspace PCI config reads/writes */
309 spin_unlock_irqrestore(&udev->lock, flags);
310 printk(KERN_INFO "irq 0x%x %s\n", irq, (ret == IRQ_HANDLED) ? "handled" : "not handled");
315 /* Remap pci resources described by bar #pci_bar in uio resource n. */
317 igbuio_pci_setup_iomem(struct pci_dev *dev, struct uio_info *info,
318 int n, int pci_bar, const char *name)
320 unsigned long addr, len;
323 if (sizeof(info->mem) / sizeof (info->mem[0]) <= n)
326 addr = pci_resource_start(dev, pci_bar);
327 len = pci_resource_len(dev, pci_bar);
328 if (addr == 0 || len == 0)
330 internal_addr = ioremap(addr, len);
331 if (internal_addr == NULL)
333 info->mem[n].name = name;
334 info->mem[n].addr = addr;
335 info->mem[n].internal_addr = internal_addr;
336 info->mem[n].size = len;
337 info->mem[n].memtype = UIO_MEM_PHYS;
341 /* Get pci port io resources described by bar #pci_bar in uio resource n. */
343 igbuio_pci_setup_ioport(struct pci_dev *dev, struct uio_info *info,
344 int n, int pci_bar, const char *name)
346 unsigned long addr, len;
348 if (sizeof(info->port) / sizeof (info->port[0]) <= n)
351 addr = pci_resource_start(dev, pci_bar);
352 len = pci_resource_len(dev, pci_bar);
353 if (addr == 0 || len == 0)
356 info->port[n].name = name;
357 info->port[n].start = addr;
358 info->port[n].size = len;
359 info->port[n].porttype = UIO_PORT_X86;
364 /* Unmap previously ioremap'd resources */
366 igbuio_pci_release_iomem(struct uio_info *info)
369 for (i = 0; i < MAX_UIO_MAPS; i++) {
370 if (info->mem[i].internal_addr)
371 iounmap(info->mem[i].internal_addr);
376 igbuio_setup_bars(struct pci_dev *dev, struct uio_info *info)
378 int i, iom, iop, ret;
380 static const char *bar_names[PCI_STD_RESOURCE_END + 1] = {
392 for (i = 0; i != sizeof(bar_names) / sizeof(bar_names[0]); i++) {
393 if (pci_resource_len(dev, i) != 0 &&
394 pci_resource_start(dev, i) != 0) {
395 flags = pci_resource_flags(dev, i);
396 if (flags & IORESOURCE_MEM) {
397 if ((ret = igbuio_pci_setup_iomem(dev, info,
398 iom, i, bar_names[i])) != 0)
401 } else if (flags & IORESOURCE_IO) {
402 if ((ret = igbuio_pci_setup_ioport(dev, info,
403 iop, i, bar_names[i])) != 0)
410 return ((iom != 0) ? ret : ENOENT);
413 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0)
418 igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
420 struct rte_uio_pci_dev *udev;
422 udev = kzalloc(sizeof(struct rte_uio_pci_dev), GFP_KERNEL);
427 * enable device: ask low-level code to enable I/O and
430 if (pci_enable_device(dev)) {
431 printk(KERN_ERR "Cannot enable PCI device\n");
436 * reserve device's PCI memory regions for use by this
439 if (pci_request_regions(dev, "igb_uio")) {
440 printk(KERN_ERR "Cannot request regions\n");
444 /* enable bus mastering on the device */
447 /* remap IO memory */
448 if (igbuio_setup_bars(dev, &udev->info))
449 goto fail_release_iomem;
451 /* set 64-bit DMA mask */
452 if (pci_set_dma_mask(dev, DMA_BIT_MASK(64))) {
453 printk(KERN_ERR "Cannot set DMA mask\n");
454 goto fail_release_iomem;
455 } else if (pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64))) {
456 printk(KERN_ERR "Cannot set consistent DMA mask\n");
457 goto fail_release_iomem;
461 udev->info.name = "Intel IGB UIO";
462 udev->info.version = "0.1";
463 udev->info.handler = igbuio_pci_irqhandler;
464 udev->info.irqcontrol = igbuio_pci_irqcontrol;
465 udev->info.priv = udev;
467 udev->mode = 0; /* set the default value for interrupt mode */
468 spin_lock_init(&udev->lock);
470 /* check if it need to try msix first */
471 if (igbuio_intr_mode_preferred == IGBUIO_MSIX_INTR_MODE) {
474 for (vector = 0; vector < IGBUIO_NUM_MSI_VECTORS; vector ++)
475 udev->msix_entries[vector].entry = vector;
477 if (pci_enable_msix(udev->pdev, udev->msix_entries, IGBUIO_NUM_MSI_VECTORS) == 0) {
478 udev->mode = IGBUIO_MSIX_INTR_MODE;
481 pci_disable_msix(udev->pdev);
482 printk(KERN_INFO "fail to enable pci msix, or not enough msix entries\n");
485 switch (udev->mode) {
486 case IGBUIO_MSIX_INTR_MODE:
487 udev->info.irq_flags = 0;
488 udev->info.irq = udev->msix_entries[0].vector;
490 case IGBUIO_MSI_INTR_MODE:
492 case IGBUIO_LEGACY_INTR_MODE:
493 udev->info.irq_flags = IRQF_SHARED;
494 udev->info.irq = dev->irq;
500 pci_set_drvdata(dev, udev);
501 igbuio_pci_irqcontrol(&udev->info, 0);
503 if (sysfs_create_group(&dev->dev.kobj, &dev_attr_grp))
504 goto fail_release_iomem;
506 /* register uio driver */
507 if (uio_register_device(&dev->dev, &udev->info))
508 goto fail_release_iomem;
510 printk(KERN_INFO "uio device registered with irq %lx\n", udev->info.irq);
515 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
516 igbuio_pci_release_iomem(&udev->info);
517 if (udev->mode == IGBUIO_MSIX_INTR_MODE)
518 pci_disable_msix(udev->pdev);
519 pci_release_regions(dev);
521 pci_disable_device(dev);
529 igbuio_pci_remove(struct pci_dev *dev)
531 struct uio_info *info = pci_get_drvdata(dev);
533 if (info->priv == NULL) {
534 printk(KERN_DEBUG "Not igbuio device\n");
538 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
539 uio_unregister_device(info);
540 igbuio_pci_release_iomem(info);
541 if (((struct rte_uio_pci_dev *)info->priv)->mode ==
542 IGBUIO_MSIX_INTR_MODE)
543 pci_disable_msix(dev);
544 pci_release_regions(dev);
545 pci_disable_device(dev);
546 pci_set_drvdata(dev, NULL);
551 igbuio_config_intr_mode(char *intr_str)
554 printk(KERN_INFO "Use MSIX interrupt by default\n");
558 if (!strcmp(intr_str, "msix")) {
559 igbuio_intr_mode_preferred = IGBUIO_MSIX_INTR_MODE;
560 printk(KERN_INFO "Use MSIX interrupt\n");
561 } else if (!strcmp(intr_str, "legacy")) {
562 igbuio_intr_mode_preferred = IGBUIO_LEGACY_INTR_MODE;
563 printk(KERN_INFO "Use legacy interrupt\n");
565 printk(KERN_INFO "Error: bad parameter - %s\n", intr_str);
572 static struct pci_driver igbuio_pci_driver = {
574 .id_table = igbuio_pci_ids,
575 .probe = igbuio_pci_probe,
576 .remove = igbuio_pci_remove,
580 igbuio_pci_init_module(void)
584 ret = igbuio_config_intr_mode(intr_mode);
588 return pci_register_driver(&igbuio_pci_driver);
592 igbuio_pci_exit_module(void)
594 pci_unregister_driver(&igbuio_pci_driver);
597 module_init(igbuio_pci_init_module);
598 module_exit(igbuio_pci_exit_module);
600 module_param(intr_mode, charp, S_IRUGO | S_IWUSR);
601 MODULE_PARM_DESC(intr_mode,
602 "igb_uio interrupt mode (default=msix):\n"
603 " msix Use MSIX interrupt\n"
604 " legacy Use Legacy interrupt\n"
607 MODULE_DESCRIPTION("UIO driver for Intel IGB PCI cards");
608 MODULE_LICENSE("GPL");
609 MODULE_AUTHOR("Intel Corporation");