4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * The full GNU General Public License is included in this distribution
19 * in the file called LICENSE.GPL.
21 * Contact Information:
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27 #include <linux/device.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/uio_driver.h>
32 #include <linux/msi.h>
33 #include <linux/version.h>
34 #include <linux/slab.h>
36 #ifdef CONFIG_XEN_DOM0
39 #include <rte_pci_dev_features.h>
44 #define PCI_SYS_FILE_BUF_SIZE 10
45 #define PCI_DEV_CAP_REG 0xA4
46 #define PCI_DEV_CTRL_REG 0xA8
47 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
48 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
49 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
53 * A structure describing the private information for a uio device.
55 struct rte_uio_pci_dev {
58 enum rte_intr_mode mode;
61 static char *intr_mode;
62 static enum rte_intr_mode igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
66 show_max_vfs(struct device *dev, struct device_attribute *attr,
69 return snprintf(buf, 10, "%u\n", dev_num_vf(dev));
73 store_max_vfs(struct device *dev, struct device_attribute *attr,
74 const char *buf, size_t count)
77 unsigned long max_vfs;
78 struct pci_dev *pdev = to_pci_dev(dev);
80 if (0 != kstrtoul(buf, 0, &max_vfs))
84 pci_disable_sriov(pdev);
85 else if (0 == pci_num_vf(pdev))
86 err = pci_enable_sriov(pdev, max_vfs);
87 else /* do nothing if change max_vfs number */
90 return err ? err : count;
95 show_extended_tag(struct device *dev, struct device_attribute *attr, char *buf)
97 struct pci_dev *pci_dev = to_pci_dev(dev);
100 pci_read_config_dword(pci_dev, PCI_DEV_CAP_REG, &val);
101 if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) /* Not supported */
102 return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n", "invalid");
105 pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
106 PCI_DEV_CTRL_REG, &val);
108 return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n",
109 (val & PCI_DEV_CTRL_EXT_TAG_MASK) ? "on" : "off");
113 store_extended_tag(struct device *dev,
114 struct device_attribute *attr,
118 struct pci_dev *pci_dev = to_pci_dev(dev);
119 uint32_t val = 0, enable;
121 if (strncmp(buf, "on", 2) == 0)
123 else if (strncmp(buf, "off", 3) == 0)
128 pci_cfg_access_lock(pci_dev);
129 pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
130 PCI_DEV_CAP_REG, &val);
131 if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) { /* Not supported */
132 pci_cfg_access_unlock(pci_dev);
137 pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
138 PCI_DEV_CTRL_REG, &val);
140 val |= PCI_DEV_CTRL_EXT_TAG_MASK;
142 val &= ~PCI_DEV_CTRL_EXT_TAG_MASK;
143 pci_bus_write_config_dword(pci_dev->bus, pci_dev->devfn,
144 PCI_DEV_CTRL_REG, val);
145 pci_cfg_access_unlock(pci_dev);
151 show_max_read_request_size(struct device *dev,
152 struct device_attribute *attr,
155 struct pci_dev *pci_dev = to_pci_dev(dev);
156 int val = pcie_get_readrq(pci_dev);
158 return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%d\n", val);
162 store_max_read_request_size(struct device *dev,
163 struct device_attribute *attr,
167 struct pci_dev *pci_dev = to_pci_dev(dev);
168 unsigned long size = 0;
171 if (0 != kstrtoul(buf, 0, &size))
174 ret = pcie_set_readrq(pci_dev, (int)size);
182 static DEVICE_ATTR(max_vfs, S_IRUGO | S_IWUSR, show_max_vfs, store_max_vfs);
183 #ifdef RTE_PCI_CONFIG
184 static DEVICE_ATTR(extended_tag, S_IRUGO | S_IWUSR, show_extended_tag,
186 static DEVICE_ATTR(max_read_request_size, S_IRUGO | S_IWUSR,
187 show_max_read_request_size, store_max_read_request_size);
190 static struct attribute *dev_attrs[] = {
191 &dev_attr_max_vfs.attr,
192 #ifdef RTE_PCI_CONFIG
193 &dev_attr_extended_tag.attr,
194 &dev_attr_max_read_request_size.attr,
199 static const struct attribute_group dev_attr_grp = {
203 * It masks the msix on/off of generating MSI-X messages.
206 igbuio_msix_mask_irq(struct msi_desc *desc, int32_t state)
208 u32 mask_bits = desc->masked;
209 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
210 PCI_MSIX_ENTRY_VECTOR_CTRL;
213 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
215 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
217 if (mask_bits != desc->masked) {
218 writel(mask_bits, desc->mask_base + offset);
219 readl(desc->mask_base);
220 desc->masked = mask_bits;
225 * This is the irqcontrol callback to be registered to uio_info.
226 * It can be used to disable/enable interrupt from user space processes.
229 * pointer to uio_info.
231 * state value. 1 to enable interrupt, 0 to disable interrupt.
235 * - On failure, a negative value.
238 igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
240 struct rte_uio_pci_dev *udev = info->priv;
241 struct pci_dev *pdev = udev->pdev;
243 pci_cfg_access_lock(pdev);
244 if (udev->mode == RTE_INTR_MODE_LEGACY)
245 pci_intx(pdev, !!irq_state);
247 else if (udev->mode == RTE_INTR_MODE_MSIX) {
248 struct msi_desc *desc;
250 #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 3, 0))
251 list_for_each_entry(desc, &pdev->msi_list, list)
252 igbuio_msix_mask_irq(desc, irq_state);
254 list_for_each_entry(desc, &pdev->dev.msi_list, list)
255 igbuio_msix_mask_irq(desc, irq_state);
258 pci_cfg_access_unlock(pdev);
264 * This is interrupt handler which will check if the interrupt is for the right device.
265 * If yes, disable it here and will be enable later.
268 igbuio_pci_irqhandler(int irq, struct uio_info *info)
270 struct rte_uio_pci_dev *udev = info->priv;
272 /* Legacy mode need to mask in hardware */
273 if (udev->mode == RTE_INTR_MODE_LEGACY &&
274 !pci_check_and_mask_intx(udev->pdev))
277 /* Message signal mode, no share IRQ and automasked */
281 #ifdef CONFIG_XEN_DOM0
283 igbuio_dom0_mmap_phys(struct uio_info *info, struct vm_area_struct *vma)
287 idx = (int)vma->vm_pgoff;
288 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
289 #ifdef HAVE_PTE_MASK_PAGE_IOMAP
290 vma->vm_page_prot.pgprot |= _PAGE_IOMAP;
293 return remap_pfn_range(vma,
295 info->mem[idx].addr >> PAGE_SHIFT,
296 vma->vm_end - vma->vm_start,
301 * This is uio device mmap method which will use igbuio mmap for Xen
305 igbuio_dom0_pci_mmap(struct uio_info *info, struct vm_area_struct *vma)
309 if (vma->vm_pgoff >= MAX_UIO_MAPS)
312 if (info->mem[vma->vm_pgoff].size == 0)
315 idx = (int)vma->vm_pgoff;
316 switch (info->mem[idx].memtype) {
318 return igbuio_dom0_mmap_phys(info, vma);
319 case UIO_MEM_LOGICAL:
320 case UIO_MEM_VIRTUAL:
327 /* Remap pci resources described by bar #pci_bar in uio resource n. */
329 igbuio_pci_setup_iomem(struct pci_dev *dev, struct uio_info *info,
330 int n, int pci_bar, const char *name)
332 unsigned long addr, len;
335 if (n >= ARRAY_SIZE(info->mem))
338 addr = pci_resource_start(dev, pci_bar);
339 len = pci_resource_len(dev, pci_bar);
340 if (addr == 0 || len == 0)
342 internal_addr = ioremap(addr, len);
343 if (internal_addr == NULL)
345 info->mem[n].name = name;
346 info->mem[n].addr = addr;
347 info->mem[n].internal_addr = internal_addr;
348 info->mem[n].size = len;
349 info->mem[n].memtype = UIO_MEM_PHYS;
353 /* Get pci port io resources described by bar #pci_bar in uio resource n. */
355 igbuio_pci_setup_ioport(struct pci_dev *dev, struct uio_info *info,
356 int n, int pci_bar, const char *name)
358 unsigned long addr, len;
360 if (n >= ARRAY_SIZE(info->port))
363 addr = pci_resource_start(dev, pci_bar);
364 len = pci_resource_len(dev, pci_bar);
365 if (addr == 0 || len == 0)
368 info->port[n].name = name;
369 info->port[n].start = addr;
370 info->port[n].size = len;
371 info->port[n].porttype = UIO_PORT_X86;
376 /* Unmap previously ioremap'd resources */
378 igbuio_pci_release_iomem(struct uio_info *info)
382 for (i = 0; i < MAX_UIO_MAPS; i++) {
383 if (info->mem[i].internal_addr)
384 iounmap(info->mem[i].internal_addr);
389 igbuio_setup_bars(struct pci_dev *dev, struct uio_info *info)
391 int i, iom, iop, ret;
393 static const char *bar_names[PCI_STD_RESOURCE_END + 1] = {
405 for (i = 0; i < ARRAY_SIZE(bar_names); i++) {
406 if (pci_resource_len(dev, i) != 0 &&
407 pci_resource_start(dev, i) != 0) {
408 flags = pci_resource_flags(dev, i);
409 if (flags & IORESOURCE_MEM) {
410 ret = igbuio_pci_setup_iomem(dev, info, iom,
415 } else if (flags & IORESOURCE_IO) {
416 ret = igbuio_pci_setup_ioport(dev, info, iop,
425 return (iom != 0) ? ret : -ENOENT;
428 #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)
433 igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
435 struct rte_uio_pci_dev *udev;
436 struct msix_entry msix_entry;
439 udev = kzalloc(sizeof(struct rte_uio_pci_dev), GFP_KERNEL);
444 * enable device: ask low-level code to enable I/O and
447 err = pci_enable_device(dev);
449 dev_err(&dev->dev, "Cannot enable PCI device\n");
454 * reserve device's PCI memory regions for use by this
457 err = pci_request_regions(dev, "igb_uio");
459 dev_err(&dev->dev, "Cannot request regions\n");
463 /* enable bus mastering on the device */
466 /* remap IO memory */
467 err = igbuio_setup_bars(dev, &udev->info);
469 goto fail_release_iomem;
471 /* set 64-bit DMA mask */
472 err = pci_set_dma_mask(dev, DMA_BIT_MASK(64));
474 dev_err(&dev->dev, "Cannot set DMA mask\n");
475 goto fail_release_iomem;
478 err = pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64));
480 dev_err(&dev->dev, "Cannot set consistent DMA mask\n");
481 goto fail_release_iomem;
485 udev->info.name = "igb_uio";
486 udev->info.version = "0.1";
487 udev->info.handler = igbuio_pci_irqhandler;
488 udev->info.irqcontrol = igbuio_pci_irqcontrol;
489 #ifdef CONFIG_XEN_DOM0
490 /* check if the driver run on Xen Dom0 */
491 if (xen_initial_domain())
492 udev->info.mmap = igbuio_dom0_pci_mmap;
494 udev->info.priv = udev;
497 switch (igbuio_intr_mode_preferred) {
498 case RTE_INTR_MODE_MSIX:
499 /* Only 1 msi-x vector needed */
500 msix_entry.entry = 0;
501 if (pci_enable_msix(dev, &msix_entry, 1) == 0) {
502 dev_dbg(&dev->dev, "using MSI-X");
503 udev->info.irq = msix_entry.vector;
504 udev->mode = RTE_INTR_MODE_MSIX;
507 /* fall back to INTX */
508 case RTE_INTR_MODE_LEGACY:
509 if (pci_intx_mask_supported(dev)) {
510 dev_dbg(&dev->dev, "using INTX");
511 udev->info.irq_flags = IRQF_SHARED;
512 udev->info.irq = dev->irq;
513 udev->mode = RTE_INTR_MODE_LEGACY;
516 dev_notice(&dev->dev, "PCI INTX mask not supported\n");
517 /* fall back to no IRQ */
518 case RTE_INTR_MODE_NONE:
519 udev->mode = RTE_INTR_MODE_NONE;
524 dev_err(&dev->dev, "invalid IRQ mode %u",
525 igbuio_intr_mode_preferred);
527 goto fail_release_iomem;
530 err = sysfs_create_group(&dev->dev.kobj, &dev_attr_grp);
532 goto fail_release_iomem;
534 /* register uio driver */
535 err = uio_register_device(&dev->dev, &udev->info);
537 goto fail_remove_group;
539 pci_set_drvdata(dev, udev);
541 dev_info(&dev->dev, "uio device registered with irq %lx\n",
547 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
549 igbuio_pci_release_iomem(&udev->info);
550 if (udev->mode == RTE_INTR_MODE_MSIX)
551 pci_disable_msix(udev->pdev);
552 pci_release_regions(dev);
554 pci_disable_device(dev);
562 igbuio_pci_remove(struct pci_dev *dev)
564 struct uio_info *info = pci_get_drvdata(dev);
565 struct rte_uio_pci_dev *udev;
567 if (info->priv == NULL) {
568 pr_notice("Not igbuio device\n");
573 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
574 uio_unregister_device(info);
575 igbuio_pci_release_iomem(info);
576 if (udev->mode == RTE_INTR_MODE_MSIX)
577 pci_disable_msix(dev);
578 pci_release_regions(dev);
579 pci_disable_device(dev);
580 pci_set_drvdata(dev, NULL);
585 igbuio_config_intr_mode(char *intr_str)
588 pr_info("Use MSIX interrupt by default\n");
592 if (!strcmp(intr_str, RTE_INTR_MODE_MSIX_NAME)) {
593 igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
594 pr_info("Use MSIX interrupt\n");
595 } else if (!strcmp(intr_str, RTE_INTR_MODE_LEGACY_NAME)) {
596 igbuio_intr_mode_preferred = RTE_INTR_MODE_LEGACY;
597 pr_info("Use legacy interrupt\n");
599 pr_info("Error: bad parameter - %s\n", intr_str);
606 static struct pci_driver igbuio_pci_driver = {
609 .probe = igbuio_pci_probe,
610 .remove = igbuio_pci_remove,
614 igbuio_pci_init_module(void)
618 ret = igbuio_config_intr_mode(intr_mode);
622 return pci_register_driver(&igbuio_pci_driver);
626 igbuio_pci_exit_module(void)
628 pci_unregister_driver(&igbuio_pci_driver);
631 module_init(igbuio_pci_init_module);
632 module_exit(igbuio_pci_exit_module);
634 module_param(intr_mode, charp, S_IRUGO);
635 MODULE_PARM_DESC(intr_mode,
636 "igb_uio interrupt mode (default=msix):\n"
637 " " RTE_INTR_MODE_MSIX_NAME " Use MSIX interrupt\n"
638 " " RTE_INTR_MODE_LEGACY_NAME " Use Legacy interrupt\n"
641 MODULE_DESCRIPTION("UIO driver for Intel IGB PCI cards");
642 MODULE_LICENSE("GPL");
643 MODULE_AUTHOR("Intel Corporation");