4 * Copyright(c) 2010-2012 Intel Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * The full GNU General Public License is included in this distribution
19 * in the file called LICENSE.GPL.
21 * Contact Information:
26 #include <linux/device.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include <linux/uio_driver.h>
31 #include <linux/msi.h>
32 #include <linux/version.h>
34 /* Some function names changes between 3.2.0 and 3.3.0... */
35 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0)
36 #define PCI_LOCK pci_block_user_cfg_access
37 #define PCI_UNLOCK pci_unblock_user_cfg_access
39 #define PCI_LOCK pci_cfg_access_lock
40 #define PCI_UNLOCK pci_cfg_access_unlock
44 * MSI-X related macros, copy from linux/pci_regs.h in kernel 2.6.39,
45 * but none of them in kernel 2.6.35.
47 #ifndef PCI_MSIX_ENTRY_SIZE
48 #define PCI_MSIX_ENTRY_SIZE 16
49 #define PCI_MSIX_ENTRY_LOWER_ADDR 0
50 #define PCI_MSIX_ENTRY_UPPER_ADDR 4
51 #define PCI_MSIX_ENTRY_DATA 8
52 #define PCI_MSIX_ENTRY_VECTOR_CTRL 12
53 #define PCI_MSIX_ENTRY_CTRL_MASKBIT 1
56 #define IGBUIO_NUM_MSI_VECTORS 1
59 enum igbuio_intr_mode {
60 IGBUIO_LEGACY_INTR_MODE = 0,
62 IGBUIO_MSIX_INTR_MODE,
67 * A structure describing the private information for a uio device.
69 struct rte_uio_pci_dev {
72 spinlock_t lock; /* spinlock for accessing PCI config space or msix data in multi tasks/isr */
73 enum igbuio_intr_mode mode;
75 msix_entries[IGBUIO_NUM_MSI_VECTORS]; /* pointer to the msix vectors to be allocated later */
78 static const enum igbuio_intr_mode igbuio_intr_mode_preferred = IGBUIO_MSIX_INTR_MODE;
80 /* PCI device id table */
81 static struct pci_device_id igbuio_pci_ids[] = {
82 #define RTE_PCI_DEV_ID_DECL(vend, dev) {PCI_DEVICE(vend, dev)},
83 #include <rte_pci_dev_ids.h>
87 static inline struct rte_uio_pci_dev *
88 igbuio_get_uio_pci_dev(struct uio_info *info)
90 return container_of(info, struct rte_uio_pci_dev, info);
94 * It masks the msix on/off of generating MSI-X messages.
97 igbuio_msix_mask_irq(struct msi_desc *desc, int32_t state)
99 uint32_t mask_bits = desc->masked;
100 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
101 PCI_MSIX_ENTRY_VECTOR_CTRL;
104 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
106 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
108 if (mask_bits != desc->masked) {
109 writel(mask_bits, desc->mask_base + offset);
110 readl(desc->mask_base);
111 desc->masked = mask_bits;
118 * This function sets/clears the masks for generating LSC interrupts.
121 * The pointer to struct uio_info.
123 * The on/off flag of masking LSC.
125 * -On success, zero value.
126 * -On failure, a negative value.
129 igbuio_set_interrupt_mask(struct rte_uio_pci_dev *udev, int32_t state)
131 struct pci_dev *pdev = udev->pdev;
133 if (udev->mode == IGBUIO_MSIX_INTR_MODE) {
134 struct msi_desc *desc;
136 list_for_each_entry(desc, &pdev->msi_list, list) {
137 igbuio_msix_mask_irq(desc, state);
140 else if (udev->mode == IGBUIO_LEGACY_INTR_MODE) {
144 pci_read_config_dword(pdev, PCI_COMMAND, &status);
147 new = old & (~PCI_COMMAND_INTX_DISABLE);
149 new = old | PCI_COMMAND_INTX_DISABLE;
152 pci_write_config_word(pdev, PCI_COMMAND, new);
159 * This is the irqcontrol callback to be registered to uio_info.
160 * It can be used to disable/enable interrupt from user space processes.
163 * pointer to uio_info.
165 * state value. 1 to enable interrupt, 0 to disable interrupt.
169 * - On failure, a negative value.
172 igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
175 struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
176 struct pci_dev *pdev = udev->pdev;
178 spin_lock_irqsave(&udev->lock, flags);
181 igbuio_set_interrupt_mask(udev, irq_state);
184 spin_unlock_irqrestore(&udev->lock, flags);
190 * This is interrupt handler which will check if the interrupt is for the right device.
191 * If yes, disable it here and will be enable later.
194 igbuio_pci_irqhandler(int irq, struct uio_info *info)
196 irqreturn_t ret = IRQ_NONE;
198 struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
199 struct pci_dev *pdev = udev->pdev;
200 uint32_t cmd_status_dword;
203 spin_lock_irqsave(&udev->lock, flags);
204 /* block userspace PCI config reads/writes */
207 /* for legacy mode, interrupt maybe shared */
208 if (udev->mode == IGBUIO_LEGACY_INTR_MODE) {
209 pci_read_config_dword(pdev, PCI_COMMAND, &cmd_status_dword);
210 status = cmd_status_dword >> 16;
211 /* interrupt is not ours, goes to out */
212 if (!(status & PCI_STATUS_INTERRUPT))
216 igbuio_set_interrupt_mask(udev, 0);
219 /* unblock userspace PCI config reads/writes */
221 spin_unlock_irqrestore(&udev->lock, flags);
222 printk(KERN_INFO "irq 0x%x %s\n", irq, (ret == IRQ_HANDLED) ? "handled" : "not handled");
227 /* Remap pci resources described by bar #pci_bar in uio resource n. */
229 igbuio_pci_setup_iomem(struct pci_dev *dev, struct uio_info *info,
230 int n, int pci_bar, const char *name)
232 unsigned long addr, len;
235 addr = pci_resource_start(dev, pci_bar);
236 len = pci_resource_len(dev, pci_bar);
237 if (addr == 0 || len == 0)
239 internal_addr = ioremap(addr, len);
240 if (internal_addr == NULL)
242 info->mem[n].name = name;
243 info->mem[n].addr = addr;
244 info->mem[n].internal_addr = internal_addr;
245 info->mem[n].size = len;
246 info->mem[n].memtype = UIO_MEM_PHYS;
250 /* Unmap previously ioremap'd resources */
252 igbuio_pci_release_iomem(struct uio_info *info)
255 for (i = 0; i < MAX_UIO_MAPS; i++) {
256 if (info->mem[i].internal_addr)
257 iounmap(info->mem[i].internal_addr);
262 igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
264 struct rte_uio_pci_dev *udev;
266 udev = kzalloc(sizeof(struct rte_uio_pci_dev), GFP_KERNEL);
271 * enable device: ask low-level code to enable I/O and
274 if (pci_enable_device(dev)) {
275 printk(KERN_ERR "Cannot enable PCI device\n");
279 /* XXX should we use 64 bits ? */
280 /* set 32-bit DMA mask */
281 if (pci_set_dma_mask(dev,(uint64_t)0xffffffff)) {
282 printk(KERN_ERR "Cannot set DMA mask\n");
287 * reserve device's PCI memory regions for use by this
290 if (pci_request_regions(dev, "igb_uio")) {
291 printk(KERN_ERR "Cannot request regions\n");
295 /* enable bus mastering on the device */
298 /* remap IO memory */
299 if (igbuio_pci_setup_iomem(dev, &udev->info, 0, 0, "config"))
300 goto fail_release_regions;
303 udev->info.name = "Intel IGB UIO";
304 udev->info.version = "0.1";
305 udev->info.handler = igbuio_pci_irqhandler;
306 udev->info.irqcontrol = igbuio_pci_irqcontrol;
307 udev->info.priv = udev;
309 udev->mode = 0; /* set the default value for interrupt mode */
310 spin_lock_init(&udev->lock);
312 /* check if it need to try msix first */
313 if (igbuio_intr_mode_preferred == IGBUIO_MSIX_INTR_MODE) {
316 for (vector = 0; vector < IGBUIO_NUM_MSI_VECTORS; vector ++)
317 udev->msix_entries[vector].entry = vector;
319 if (pci_enable_msix(udev->pdev, udev->msix_entries, IGBUIO_NUM_MSI_VECTORS) == 0) {
320 udev->mode = IGBUIO_MSIX_INTR_MODE;
323 pci_disable_msix(udev->pdev);
324 printk(KERN_INFO "fail to enable pci msix, or not enough msix entries\n");
327 switch (udev->mode) {
328 case IGBUIO_MSIX_INTR_MODE:
329 udev->info.irq_flags = 0;
330 udev->info.irq = udev->msix_entries[0].vector;
332 case IGBUIO_MSI_INTR_MODE:
334 case IGBUIO_LEGACY_INTR_MODE:
335 udev->info.irq_flags = IRQF_SHARED;
336 udev->info.irq = dev->irq;
342 pci_set_drvdata(dev, udev);
343 igbuio_pci_irqcontrol(&udev->info, 0);
345 /* register uio driver */
346 if (uio_register_device(&dev->dev, &udev->info))
347 goto fail_release_iomem;
349 printk(KERN_INFO "uio device registered with irq %lx\n", udev->info.irq);
354 igbuio_pci_release_iomem(&udev->info);
355 if (udev->mode == IGBUIO_MSIX_INTR_MODE)
356 pci_disable_msix(udev->pdev);
357 fail_release_regions:
358 pci_release_regions(dev);
360 pci_disable_device(dev);
368 igbuio_pci_remove(struct pci_dev *dev)
370 struct uio_info *info = pci_get_drvdata(dev);
372 uio_unregister_device(info);
373 if (((struct rte_uio_pci_dev *)info->priv)->mode == IGBUIO_MSIX_INTR_MODE)
374 pci_disable_msix(dev);
375 pci_release_regions(dev);
376 pci_disable_device(dev);
377 pci_set_drvdata(dev, NULL);
381 static struct pci_driver igbuio_pci_driver = {
383 .id_table = igbuio_pci_ids,
384 .probe = igbuio_pci_probe,
385 .remove = igbuio_pci_remove,
389 igbuio_pci_init_module(void)
391 return pci_register_driver(&igbuio_pci_driver);
395 igbuio_pci_exit_module(void)
397 pci_unregister_driver(&igbuio_pci_driver);
400 module_init(igbuio_pci_init_module);
401 module_exit(igbuio_pci_exit_module);
403 MODULE_DESCRIPTION("UIO driver for Intel IGB PCI cards");
404 MODULE_LICENSE("GPL");
405 MODULE_AUTHOR("Intel Corporation");