1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8 #include <linux/device.h>
9 #include <linux/module.h>
10 #include <linux/pci.h>
11 #include <linux/uio_driver.h>
13 #include <linux/irq.h>
14 #include <linux/msi.h>
15 #include <linux/version.h>
16 #include <linux/slab.h>
18 #include <rte_pci_dev_features.h>
23 * A structure describing the private information for a uio device.
25 struct rte_uio_pci_dev {
28 enum rte_intr_mode mode;
31 static char *intr_mode;
32 static enum rte_intr_mode igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
35 show_max_vfs(struct device *dev, struct device_attribute *attr,
38 return snprintf(buf, 10, "%u\n", dev_num_vf(dev));
42 store_max_vfs(struct device *dev, struct device_attribute *attr,
43 const char *buf, size_t count)
46 unsigned long max_vfs;
47 struct pci_dev *pdev = to_pci_dev(dev);
49 if (0 != kstrtoul(buf, 0, &max_vfs))
53 pci_disable_sriov(pdev);
54 else if (0 == pci_num_vf(pdev))
55 err = pci_enable_sriov(pdev, max_vfs);
56 else /* do nothing if change max_vfs number */
59 return err ? err : count;
62 static DEVICE_ATTR(max_vfs, S_IRUGO | S_IWUSR, show_max_vfs, store_max_vfs);
64 static struct attribute *dev_attrs[] = {
65 &dev_attr_max_vfs.attr,
69 static const struct attribute_group dev_attr_grp = {
73 #ifndef HAVE_PCI_MSI_MASK_IRQ
75 * It masks the msix on/off of generating MSI-X messages.
78 igbuio_msix_mask_irq(struct msi_desc *desc, s32 state)
80 u32 mask_bits = desc->masked;
81 unsigned int offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
82 PCI_MSIX_ENTRY_VECTOR_CTRL;
85 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
87 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
89 if (mask_bits != desc->masked) {
90 writel(mask_bits, desc->mask_base + offset);
91 readl(desc->mask_base);
92 desc->masked = mask_bits;
97 * It masks the msi on/off of generating MSI messages.
100 igbuio_msi_mask_irq(struct pci_dev *pdev, struct msi_desc *desc, int32_t state)
102 u32 mask_bits = desc->masked;
103 u32 offset = desc->irq - pdev->irq;
104 u32 mask = 1 << offset;
106 if (!desc->msi_attrib.maskbit)
114 if (mask_bits != desc->masked) {
115 pci_write_config_dword(pdev, desc->mask_pos, mask_bits);
116 desc->masked = mask_bits;
121 igbuio_mask_irq(struct pci_dev *pdev, enum rte_intr_mode mode, s32 irq_state)
123 struct msi_desc *desc;
124 struct list_head *msi_list;
126 #ifdef HAVE_MSI_LIST_IN_GENERIC_DEVICE
127 msi_list = &pdev->dev.msi_list;
129 msi_list = &pdev->msi_list;
132 if (mode == RTE_INTR_MODE_MSIX) {
133 list_for_each_entry(desc, msi_list, list)
134 igbuio_msix_mask_irq(desc, irq_state);
135 } else if (mode == RTE_INTR_MODE_MSI) {
136 list_for_each_entry(desc, msi_list, list)
137 igbuio_msi_mask_irq(pdev, desc, irq_state);
143 * This is the irqcontrol callback to be registered to uio_info.
144 * It can be used to disable/enable interrupt from user space processes.
147 * pointer to uio_info.
149 * state value. 1 to enable interrupt, 0 to disable interrupt.
153 * - On failure, a negative value.
156 igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
158 struct rte_uio_pci_dev *udev = info->priv;
159 struct pci_dev *pdev = udev->pdev;
161 #ifdef HAVE_PCI_MSI_MASK_IRQ
162 struct irq_data *irq = irq_get_irq_data(udev->info.irq);
165 pci_cfg_access_lock(pdev);
167 if (udev->mode == RTE_INTR_MODE_MSIX || udev->mode == RTE_INTR_MODE_MSI) {
168 #ifdef HAVE_PCI_MSI_MASK_IRQ
170 pci_msi_unmask_irq(irq);
172 pci_msi_mask_irq(irq);
174 igbuio_mask_irq(pdev, udev->mode, irq_state);
178 if (udev->mode == RTE_INTR_MODE_LEGACY)
179 pci_intx(pdev, !!irq_state);
181 pci_cfg_access_unlock(pdev);
187 * This is interrupt handler which will check if the interrupt is for the right device.
188 * If yes, disable it here and will be enable later.
191 igbuio_pci_irqhandler(int irq, void *dev_id)
193 struct rte_uio_pci_dev *udev = (struct rte_uio_pci_dev *)dev_id;
194 struct uio_info *info = &udev->info;
196 /* Legacy mode need to mask in hardware */
197 if (udev->mode == RTE_INTR_MODE_LEGACY &&
198 !pci_check_and_mask_intx(udev->pdev))
201 uio_event_notify(info);
203 /* Message signal mode, no share IRQ and automasked */
208 igbuio_pci_enable_interrupts(struct rte_uio_pci_dev *udev)
211 #ifndef HAVE_ALLOC_IRQ_VECTORS
212 struct msix_entry msix_entry;
215 switch (igbuio_intr_mode_preferred) {
216 case RTE_INTR_MODE_MSIX:
217 /* Only 1 msi-x vector needed */
218 #ifndef HAVE_ALLOC_IRQ_VECTORS
219 msix_entry.entry = 0;
220 if (pci_enable_msix(udev->pdev, &msix_entry, 1) == 0) {
221 dev_dbg(&udev->pdev->dev, "using MSI-X");
222 udev->info.irq_flags = IRQF_NO_THREAD;
223 udev->info.irq = msix_entry.vector;
224 udev->mode = RTE_INTR_MODE_MSIX;
228 if (pci_alloc_irq_vectors(udev->pdev, 1, 1, PCI_IRQ_MSIX) == 1) {
229 dev_dbg(&udev->pdev->dev, "using MSI-X");
230 udev->info.irq_flags = IRQF_NO_THREAD;
231 udev->info.irq = pci_irq_vector(udev->pdev, 0);
232 udev->mode = RTE_INTR_MODE_MSIX;
237 /* fall back to MSI */
238 case RTE_INTR_MODE_MSI:
239 #ifndef HAVE_ALLOC_IRQ_VECTORS
240 if (pci_enable_msi(udev->pdev) == 0) {
241 dev_dbg(&udev->pdev->dev, "using MSI");
242 udev->info.irq_flags = IRQF_NO_THREAD;
243 udev->info.irq = udev->pdev->irq;
244 udev->mode = RTE_INTR_MODE_MSI;
248 if (pci_alloc_irq_vectors(udev->pdev, 1, 1, PCI_IRQ_MSI) == 1) {
249 dev_dbg(&udev->pdev->dev, "using MSI");
250 udev->info.irq_flags = IRQF_NO_THREAD;
251 udev->info.irq = pci_irq_vector(udev->pdev, 0);
252 udev->mode = RTE_INTR_MODE_MSI;
256 /* fall back to INTX */
257 case RTE_INTR_MODE_LEGACY:
258 if (pci_intx_mask_supported(udev->pdev)) {
259 dev_dbg(&udev->pdev->dev, "using INTX");
260 udev->info.irq_flags = IRQF_SHARED | IRQF_NO_THREAD;
261 udev->info.irq = udev->pdev->irq;
262 udev->mode = RTE_INTR_MODE_LEGACY;
265 dev_notice(&udev->pdev->dev, "PCI INTX mask not supported\n");
266 /* fall back to no IRQ */
267 case RTE_INTR_MODE_NONE:
268 udev->mode = RTE_INTR_MODE_NONE;
269 udev->info.irq = UIO_IRQ_NONE;
273 dev_err(&udev->pdev->dev, "invalid IRQ mode %u",
274 igbuio_intr_mode_preferred);
275 udev->info.irq = UIO_IRQ_NONE;
279 if (udev->info.irq != UIO_IRQ_NONE)
280 err = request_irq(udev->info.irq, igbuio_pci_irqhandler,
281 udev->info.irq_flags, udev->info.name,
283 dev_info(&udev->pdev->dev, "uio device registered with irq %lx\n",
290 igbuio_pci_disable_interrupts(struct rte_uio_pci_dev *udev)
292 if (udev->info.irq) {
293 free_irq(udev->info.irq, udev);
297 #ifndef HAVE_ALLOC_IRQ_VECTORS
298 if (udev->mode == RTE_INTR_MODE_MSIX)
299 pci_disable_msix(udev->pdev);
300 if (udev->mode == RTE_INTR_MODE_MSI)
301 pci_disable_msi(udev->pdev);
303 if (udev->mode == RTE_INTR_MODE_MSIX ||
304 udev->mode == RTE_INTR_MODE_MSI)
305 pci_free_irq_vectors(udev->pdev);
311 * This gets called while opening uio device file.
314 igbuio_pci_open(struct uio_info *info, struct inode *inode)
316 struct rte_uio_pci_dev *udev = info->priv;
317 struct pci_dev *dev = udev->pdev;
320 /* set bus master, which was cleared by the reset function */
323 /* enable interrupts */
324 err = igbuio_pci_enable_interrupts(udev);
326 dev_err(&dev->dev, "Enable interrupt fails\n");
333 igbuio_pci_release(struct uio_info *info, struct inode *inode)
335 struct rte_uio_pci_dev *udev = info->priv;
336 struct pci_dev *dev = udev->pdev;
338 /* disable interrupts */
339 igbuio_pci_disable_interrupts(udev);
341 /* stop the device from further DMA */
342 pci_clear_master(dev);
347 /* Remap pci resources described by bar #pci_bar in uio resource n. */
349 igbuio_pci_setup_iomem(struct pci_dev *dev, struct uio_info *info,
350 int n, int pci_bar, const char *name)
352 unsigned long addr, len;
355 if (n >= ARRAY_SIZE(info->mem))
358 addr = pci_resource_start(dev, pci_bar);
359 len = pci_resource_len(dev, pci_bar);
360 if (addr == 0 || len == 0)
362 internal_addr = ioremap(addr, len);
363 if (internal_addr == NULL)
365 info->mem[n].name = name;
366 info->mem[n].addr = addr;
367 info->mem[n].internal_addr = internal_addr;
368 info->mem[n].size = len;
369 info->mem[n].memtype = UIO_MEM_PHYS;
373 /* Get pci port io resources described by bar #pci_bar in uio resource n. */
375 igbuio_pci_setup_ioport(struct pci_dev *dev, struct uio_info *info,
376 int n, int pci_bar, const char *name)
378 unsigned long addr, len;
380 if (n >= ARRAY_SIZE(info->port))
383 addr = pci_resource_start(dev, pci_bar);
384 len = pci_resource_len(dev, pci_bar);
385 if (addr == 0 || len == 0)
388 info->port[n].name = name;
389 info->port[n].start = addr;
390 info->port[n].size = len;
391 info->port[n].porttype = UIO_PORT_X86;
396 /* Unmap previously ioremap'd resources */
398 igbuio_pci_release_iomem(struct uio_info *info)
402 for (i = 0; i < MAX_UIO_MAPS; i++) {
403 if (info->mem[i].internal_addr)
404 iounmap(info->mem[i].internal_addr);
409 igbuio_setup_bars(struct pci_dev *dev, struct uio_info *info)
411 int i, iom, iop, ret;
413 static const char *bar_names[PCI_STD_RESOURCE_END + 1] = {
425 for (i = 0; i < ARRAY_SIZE(bar_names); i++) {
426 if (pci_resource_len(dev, i) != 0 &&
427 pci_resource_start(dev, i) != 0) {
428 flags = pci_resource_flags(dev, i);
429 if (flags & IORESOURCE_MEM) {
430 ret = igbuio_pci_setup_iomem(dev, info, iom,
435 } else if (flags & IORESOURCE_IO) {
436 ret = igbuio_pci_setup_ioport(dev, info, iop,
445 return (iom != 0 || iop != 0) ? ret : -ENOENT;
448 #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)
453 igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
455 struct rte_uio_pci_dev *udev;
456 dma_addr_t map_dma_addr;
460 udev = kzalloc(sizeof(struct rte_uio_pci_dev), GFP_KERNEL);
465 * enable device: ask low-level code to enable I/O and
468 err = pci_enable_device(dev);
470 dev_err(&dev->dev, "Cannot enable PCI device\n");
474 /* enable bus mastering on the device */
477 /* remap IO memory */
478 err = igbuio_setup_bars(dev, &udev->info);
480 goto fail_release_iomem;
482 /* set 64-bit DMA mask */
483 err = pci_set_dma_mask(dev, DMA_BIT_MASK(64));
485 dev_err(&dev->dev, "Cannot set DMA mask\n");
486 goto fail_release_iomem;
489 err = pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64));
491 dev_err(&dev->dev, "Cannot set consistent DMA mask\n");
492 goto fail_release_iomem;
496 udev->info.name = "igb_uio";
497 udev->info.version = "0.1";
498 udev->info.irqcontrol = igbuio_pci_irqcontrol;
499 udev->info.open = igbuio_pci_open;
500 udev->info.release = igbuio_pci_release;
501 udev->info.priv = udev;
504 err = sysfs_create_group(&dev->dev.kobj, &dev_attr_grp);
506 goto fail_release_iomem;
508 /* register uio driver */
509 err = uio_register_device(&dev->dev, &udev->info);
511 goto fail_remove_group;
513 pci_set_drvdata(dev, udev);
516 * Doing a harmless dma mapping for attaching the device to
517 * the iommu identity mapping if kernel boots with iommu=pt.
518 * Note this is not a problem if no IOMMU at all.
520 map_addr = dma_alloc_coherent(&dev->dev, 1024, &map_dma_addr,
523 memset(map_addr, 0, 1024);
526 dev_info(&dev->dev, "dma mapping failed\n");
528 dev_info(&dev->dev, "mapping 1K dma=%#llx host=%p\n",
529 (unsigned long long)map_dma_addr, map_addr);
531 dma_free_coherent(&dev->dev, 1024, map_addr, map_dma_addr);
532 dev_info(&dev->dev, "unmapping 1K dma=%#llx host=%p\n",
533 (unsigned long long)map_dma_addr, map_addr);
539 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
541 igbuio_pci_release_iomem(&udev->info);
542 pci_disable_device(dev);
550 igbuio_pci_remove(struct pci_dev *dev)
552 struct rte_uio_pci_dev *udev = pci_get_drvdata(dev);
554 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
555 uio_unregister_device(&udev->info);
556 igbuio_pci_release_iomem(&udev->info);
557 pci_disable_device(dev);
558 pci_set_drvdata(dev, NULL);
563 igbuio_config_intr_mode(char *intr_str)
566 pr_info("Use MSIX interrupt by default\n");
570 if (!strcmp(intr_str, RTE_INTR_MODE_MSIX_NAME)) {
571 igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
572 pr_info("Use MSIX interrupt\n");
573 } else if (!strcmp(intr_str, RTE_INTR_MODE_MSI_NAME)) {
574 igbuio_intr_mode_preferred = RTE_INTR_MODE_MSI;
575 pr_info("Use MSI interrupt\n");
576 } else if (!strcmp(intr_str, RTE_INTR_MODE_LEGACY_NAME)) {
577 igbuio_intr_mode_preferred = RTE_INTR_MODE_LEGACY;
578 pr_info("Use legacy interrupt\n");
580 pr_info("Error: bad parameter - %s\n", intr_str);
587 static struct pci_driver igbuio_pci_driver = {
590 .probe = igbuio_pci_probe,
591 .remove = igbuio_pci_remove,
595 igbuio_pci_init_module(void)
599 ret = igbuio_config_intr_mode(intr_mode);
603 return pci_register_driver(&igbuio_pci_driver);
607 igbuio_pci_exit_module(void)
609 pci_unregister_driver(&igbuio_pci_driver);
612 module_init(igbuio_pci_init_module);
613 module_exit(igbuio_pci_exit_module);
615 module_param(intr_mode, charp, S_IRUGO);
616 MODULE_PARM_DESC(intr_mode,
617 "igb_uio interrupt mode (default=msix):\n"
618 " " RTE_INTR_MODE_MSIX_NAME " Use MSIX interrupt\n"
619 " " RTE_INTR_MODE_MSI_NAME " Use MSI interrupt\n"
620 " " RTE_INTR_MODE_LEGACY_NAME " Use Legacy interrupt\n"
623 MODULE_DESCRIPTION("UIO driver for Intel IGB PCI cards");
624 MODULE_LICENSE("GPL");
625 MODULE_AUTHOR("Intel Corporation");