4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * The full GNU General Public License is included in this distribution
19 * in the file called LICENSE.GPL.
21 * Contact Information:
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27 #include <linux/device.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/uio_driver.h>
32 #include <linux/msi.h>
33 #include <linux/version.h>
34 #include <linux/slab.h>
36 #ifdef CONFIG_XEN_DOM0
39 #include <rte_pci_dev_features.h>
44 #define PCI_SYS_FILE_BUF_SIZE 10
45 #define PCI_DEV_CAP_REG 0xA4
46 #define PCI_DEV_CTRL_REG 0xA8
47 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
48 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
49 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
53 * A structure describing the private information for a uio device.
55 struct rte_uio_pci_dev {
58 enum rte_intr_mode mode;
61 static char *intr_mode = NULL;
62 static enum rte_intr_mode igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
64 static inline struct rte_uio_pci_dev *
65 igbuio_get_uio_pci_dev(struct uio_info *info)
67 return container_of(info, struct rte_uio_pci_dev, info);
72 show_max_vfs(struct device *dev, struct device_attribute *attr,
75 return snprintf(buf, 10, "%u\n",
76 pci_num_vf(container_of(dev, struct pci_dev, dev)));
80 store_max_vfs(struct device *dev, struct device_attribute *attr,
81 const char *buf, size_t count)
84 unsigned long max_vfs;
85 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
87 if (0 != kstrtoul(buf, 0, &max_vfs))
91 pci_disable_sriov(pdev);
92 else if (0 == pci_num_vf(pdev))
93 err = pci_enable_sriov(pdev, max_vfs);
94 else /* do nothing if change max_vfs number */
97 return err ? err : count;
100 #ifdef RTE_PCI_CONFIG
102 show_extended_tag(struct device *dev, struct device_attribute *attr, char *buf)
104 struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
107 pci_read_config_dword(pci_dev, PCI_DEV_CAP_REG, &val);
108 if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) /* Not supported */
109 return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n", "invalid");
112 pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
113 PCI_DEV_CTRL_REG, &val);
115 return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n",
116 (val & PCI_DEV_CTRL_EXT_TAG_MASK) ? "on" : "off");
120 store_extended_tag(struct device *dev,
121 struct device_attribute *attr,
125 struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
126 uint32_t val = 0, enable;
128 if (strncmp(buf, "on", 2) == 0)
130 else if (strncmp(buf, "off", 3) == 0)
135 pci_cfg_access_lock(pci_dev);
136 pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
137 PCI_DEV_CAP_REG, &val);
138 if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) { /* Not supported */
139 pci_cfg_access_unlock(pci_dev);
144 pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
145 PCI_DEV_CTRL_REG, &val);
147 val |= PCI_DEV_CTRL_EXT_TAG_MASK;
149 val &= ~PCI_DEV_CTRL_EXT_TAG_MASK;
150 pci_bus_write_config_dword(pci_dev->bus, pci_dev->devfn,
151 PCI_DEV_CTRL_REG, val);
152 pci_cfg_access_unlock(pci_dev);
158 show_max_read_request_size(struct device *dev,
159 struct device_attribute *attr,
162 struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
163 int val = pcie_get_readrq(pci_dev);
165 return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%d\n", val);
169 store_max_read_request_size(struct device *dev,
170 struct device_attribute *attr,
174 struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
175 unsigned long size = 0;
178 if (0 != kstrtoul(buf, 0, &size))
181 ret = pcie_set_readrq(pci_dev, (int)size);
189 static DEVICE_ATTR(max_vfs, S_IRUGO | S_IWUSR, show_max_vfs, store_max_vfs);
190 #ifdef RTE_PCI_CONFIG
191 static DEVICE_ATTR(extended_tag, S_IRUGO | S_IWUSR, show_extended_tag,
193 static DEVICE_ATTR(max_read_request_size, S_IRUGO | S_IWUSR,
194 show_max_read_request_size, store_max_read_request_size);
197 static struct attribute *dev_attrs[] = {
198 &dev_attr_max_vfs.attr,
199 #ifdef RTE_PCI_CONFIG
200 &dev_attr_extended_tag.attr,
201 &dev_attr_max_read_request_size.attr,
206 static const struct attribute_group dev_attr_grp = {
210 * It masks the msix on/off of generating MSI-X messages.
213 igbuio_msix_mask_irq(struct msi_desc *desc, int32_t state)
215 u32 mask_bits = desc->masked;
216 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
217 PCI_MSIX_ENTRY_VECTOR_CTRL;
220 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
222 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
224 if (mask_bits != desc->masked) {
225 writel(mask_bits, desc->mask_base + offset);
226 readl(desc->mask_base);
227 desc->masked = mask_bits;
232 * This is the irqcontrol callback to be registered to uio_info.
233 * It can be used to disable/enable interrupt from user space processes.
236 * pointer to uio_info.
238 * state value. 1 to enable interrupt, 0 to disable interrupt.
242 * - On failure, a negative value.
245 igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
247 struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
248 struct pci_dev *pdev = udev->pdev;
250 pci_cfg_access_lock(pdev);
251 if (udev->mode == RTE_INTR_MODE_LEGACY)
252 pci_intx(pdev, !!irq_state);
254 else if (udev->mode == RTE_INTR_MODE_MSIX) {
255 struct msi_desc *desc;
257 list_for_each_entry(desc, &pdev->msi_list, list)
258 igbuio_msix_mask_irq(desc, irq_state);
260 pci_cfg_access_unlock(pdev);
266 * This is interrupt handler which will check if the interrupt is for the right device.
267 * If yes, disable it here and will be enable later.
270 igbuio_pci_irqhandler(int irq, struct uio_info *info)
272 struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
274 /* Legacy mode need to mask in hardware */
275 if (udev->mode == RTE_INTR_MODE_LEGACY &&
276 !pci_check_and_mask_intx(udev->pdev))
279 /* Message signal mode, no share IRQ and automasked */
283 #ifdef CONFIG_XEN_DOM0
285 igbuio_dom0_mmap_phys(struct uio_info *info, struct vm_area_struct *vma)
289 idx = (int)vma->vm_pgoff;
290 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
291 #ifdef HAVE_PTE_MASK_PAGE_IOMAP
292 vma->vm_page_prot.pgprot |= _PAGE_IOMAP;
295 return remap_pfn_range(vma,
297 info->mem[idx].addr >> PAGE_SHIFT,
298 vma->vm_end - vma->vm_start,
303 * This is uio device mmap method which will use igbuio mmap for Xen
307 igbuio_dom0_pci_mmap(struct uio_info *info, struct vm_area_struct *vma)
311 if (vma->vm_pgoff >= MAX_UIO_MAPS)
314 if (info->mem[vma->vm_pgoff].size == 0)
317 idx = (int)vma->vm_pgoff;
318 switch (info->mem[idx].memtype) {
320 return igbuio_dom0_mmap_phys(info, vma);
321 case UIO_MEM_LOGICAL:
322 case UIO_MEM_VIRTUAL:
329 /* Remap pci resources described by bar #pci_bar in uio resource n. */
331 igbuio_pci_setup_iomem(struct pci_dev *dev, struct uio_info *info,
332 int n, int pci_bar, const char *name)
334 unsigned long addr, len;
337 if (sizeof(info->mem) / sizeof(info->mem[0]) <= n)
340 addr = pci_resource_start(dev, pci_bar);
341 len = pci_resource_len(dev, pci_bar);
342 if (addr == 0 || len == 0)
344 internal_addr = ioremap(addr, len);
345 if (internal_addr == NULL)
347 info->mem[n].name = name;
348 info->mem[n].addr = addr;
349 info->mem[n].internal_addr = internal_addr;
350 info->mem[n].size = len;
351 info->mem[n].memtype = UIO_MEM_PHYS;
355 /* Get pci port io resources described by bar #pci_bar in uio resource n. */
357 igbuio_pci_setup_ioport(struct pci_dev *dev, struct uio_info *info,
358 int n, int pci_bar, const char *name)
360 unsigned long addr, len;
362 if (sizeof(info->port) / sizeof(info->port[0]) <= n)
365 addr = pci_resource_start(dev, pci_bar);
366 len = pci_resource_len(dev, pci_bar);
367 if (addr == 0 || len == 0)
370 info->port[n].name = name;
371 info->port[n].start = addr;
372 info->port[n].size = len;
373 info->port[n].porttype = UIO_PORT_X86;
378 /* Unmap previously ioremap'd resources */
380 igbuio_pci_release_iomem(struct uio_info *info)
384 for (i = 0; i < MAX_UIO_MAPS; i++) {
385 if (info->mem[i].internal_addr)
386 iounmap(info->mem[i].internal_addr);
391 igbuio_setup_bars(struct pci_dev *dev, struct uio_info *info)
393 int i, iom, iop, ret;
395 static const char *bar_names[PCI_STD_RESOURCE_END + 1] = {
407 for (i = 0; i != sizeof(bar_names) / sizeof(bar_names[0]); i++) {
408 if (pci_resource_len(dev, i) != 0 &&
409 pci_resource_start(dev, i) != 0) {
410 flags = pci_resource_flags(dev, i);
411 if (flags & IORESOURCE_MEM) {
412 ret = igbuio_pci_setup_iomem(dev, info, iom,
417 } else if (flags & IORESOURCE_IO) {
418 ret = igbuio_pci_setup_ioport(dev, info, iop,
427 return (iom != 0) ? ret : -ENOENT;
430 #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)
435 igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
437 struct rte_uio_pci_dev *udev;
438 struct msix_entry msix_entry;
441 udev = kzalloc(sizeof(struct rte_uio_pci_dev), GFP_KERNEL);
446 * enable device: ask low-level code to enable I/O and
449 err = pci_enable_device(dev);
451 dev_err(&dev->dev, "Cannot enable PCI device\n");
456 * reserve device's PCI memory regions for use by this
459 err = pci_request_regions(dev, "igb_uio");
461 dev_err(&dev->dev, "Cannot request regions\n");
465 /* enable bus mastering on the device */
468 /* remap IO memory */
469 err = igbuio_setup_bars(dev, &udev->info);
471 goto fail_release_iomem;
473 /* set 64-bit DMA mask */
474 err = pci_set_dma_mask(dev, DMA_BIT_MASK(64));
476 dev_err(&dev->dev, "Cannot set DMA mask\n");
477 goto fail_release_iomem;
480 err = pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64));
482 dev_err(&dev->dev, "Cannot set consistent DMA mask\n");
483 goto fail_release_iomem;
487 udev->info.name = "igb_uio";
488 udev->info.version = "0.1";
489 udev->info.handler = igbuio_pci_irqhandler;
490 udev->info.irqcontrol = igbuio_pci_irqcontrol;
491 #ifdef CONFIG_XEN_DOM0
492 /* check if the driver run on Xen Dom0 */
493 if (xen_initial_domain())
494 udev->info.mmap = igbuio_dom0_pci_mmap;
496 udev->info.priv = udev;
499 switch (igbuio_intr_mode_preferred) {
500 case RTE_INTR_MODE_MSIX:
501 /* Only 1 msi-x vector needed */
502 msix_entry.entry = 0;
503 if (pci_enable_msix(dev, &msix_entry, 1) == 0) {
504 dev_dbg(&dev->dev, "using MSI-X");
505 udev->info.irq = msix_entry.vector;
506 udev->mode = RTE_INTR_MODE_MSIX;
509 /* fall back to INTX */
510 case RTE_INTR_MODE_LEGACY:
511 if (pci_intx_mask_supported(dev)) {
512 dev_dbg(&dev->dev, "using INTX");
513 udev->info.irq_flags = IRQF_SHARED;
514 udev->info.irq = dev->irq;
515 udev->mode = RTE_INTR_MODE_LEGACY;
518 dev_notice(&dev->dev, "PCI INTX mask not supported\n");
519 /* fall back to no IRQ */
520 case RTE_INTR_MODE_NONE:
521 udev->mode = RTE_INTR_MODE_NONE;
526 dev_err(&dev->dev, "invalid IRQ mode %u",
527 igbuio_intr_mode_preferred);
529 goto fail_release_iomem;
532 err = sysfs_create_group(&dev->dev.kobj, &dev_attr_grp);
534 goto fail_release_iomem;
536 /* register uio driver */
537 err = uio_register_device(&dev->dev, &udev->info);
539 goto fail_remove_group;
541 pci_set_drvdata(dev, udev);
543 dev_info(&dev->dev, "uio device registered with irq %lx\n",
549 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
551 igbuio_pci_release_iomem(&udev->info);
552 if (udev->mode == RTE_INTR_MODE_MSIX)
553 pci_disable_msix(udev->pdev);
554 pci_release_regions(dev);
556 pci_disable_device(dev);
564 igbuio_pci_remove(struct pci_dev *dev)
566 struct uio_info *info = pci_get_drvdata(dev);
567 struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
569 if (info->priv == NULL) {
570 pr_notice("Not igbuio device\n");
574 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
575 uio_unregister_device(info);
576 igbuio_pci_release_iomem(info);
577 if (udev->mode == RTE_INTR_MODE_MSIX)
578 pci_disable_msix(dev);
579 pci_release_regions(dev);
580 pci_disable_device(dev);
581 pci_set_drvdata(dev, NULL);
586 igbuio_config_intr_mode(char *intr_str)
589 pr_info("Use MSIX interrupt by default\n");
593 if (!strcmp(intr_str, RTE_INTR_MODE_MSIX_NAME)) {
594 igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
595 pr_info("Use MSIX interrupt\n");
596 } else if (!strcmp(intr_str, RTE_INTR_MODE_LEGACY_NAME)) {
597 igbuio_intr_mode_preferred = RTE_INTR_MODE_LEGACY;
598 pr_info("Use legacy interrupt\n");
600 pr_info("Error: bad parameter - %s\n", intr_str);
607 static struct pci_driver igbuio_pci_driver = {
610 .probe = igbuio_pci_probe,
611 .remove = igbuio_pci_remove,
615 igbuio_pci_init_module(void)
619 ret = igbuio_config_intr_mode(intr_mode);
623 return pci_register_driver(&igbuio_pci_driver);
627 igbuio_pci_exit_module(void)
629 pci_unregister_driver(&igbuio_pci_driver);
632 module_init(igbuio_pci_init_module);
633 module_exit(igbuio_pci_exit_module);
635 module_param(intr_mode, charp, S_IRUGO);
636 MODULE_PARM_DESC(intr_mode,
637 "igb_uio interrupt mode (default=msix):\n"
638 " " RTE_INTR_MODE_MSIX_NAME " Use MSIX interrupt\n"
639 " " RTE_INTR_MODE_LEGACY_NAME " Use Legacy interrupt\n"
642 MODULE_DESCRIPTION("UIO driver for Intel IGB PCI cards");
643 MODULE_LICENSE("GPL");
644 MODULE_AUTHOR("Intel Corporation");