4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * The full GNU General Public License is included in this distribution
19 * in the file called LICENSE.GPL.
21 * Contact Information:
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27 #include <linux/device.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/uio_driver.h>
32 #include <linux/msi.h>
33 #include <linux/version.h>
35 #ifdef CONFIG_XEN_DOM0
38 #include <rte_pci_dev_features.h>
41 #define PCI_SYS_FILE_BUF_SIZE 10
42 #define PCI_DEV_CAP_REG 0xA4
43 #define PCI_DEV_CTRL_REG 0xA8
44 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
45 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
46 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
50 * A structure describing the private information for a uio device.
52 struct rte_uio_pci_dev {
55 spinlock_t lock; /* spinlock for accessing PCI config space or msix data in multi tasks/isr */
56 enum rte_intr_mode mode;
59 static char *intr_mode = NULL;
60 static enum rte_intr_mode igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
62 static inline struct rte_uio_pci_dev *
63 igbuio_get_uio_pci_dev(struct uio_info *info)
65 return container_of(info, struct rte_uio_pci_dev, info);
69 #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 34)
70 static int pci_num_vf(struct pci_dev *dev)
79 } *iov = (struct iov *)dev->sriov;
84 return iov->nr_virtfn;
89 show_max_vfs(struct device *dev, struct device_attribute *attr,
92 return snprintf(buf, 10, "%u\n",
93 pci_num_vf(container_of(dev, struct pci_dev, dev)));
97 store_max_vfs(struct device *dev, struct device_attribute *attr,
98 const char *buf, size_t count)
101 unsigned long max_vfs;
102 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
104 if (0 != strict_strtoul(buf, 0, &max_vfs))
108 pci_disable_sriov(pdev);
109 else if (0 == pci_num_vf(pdev))
110 err = pci_enable_sriov(pdev, max_vfs);
111 else /* do nothing if change max_vfs number */
114 return err ? err : count;
117 #ifdef RTE_PCI_CONFIG
119 show_extended_tag(struct device *dev, struct device_attribute *attr, char *buf)
121 struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
124 pci_read_config_dword(pci_dev, PCI_DEV_CAP_REG, &val);
125 if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) /* Not supported */
126 return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n", "invalid");
129 pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
130 PCI_DEV_CTRL_REG, &val);
132 return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n",
133 (val & PCI_DEV_CTRL_EXT_TAG_MASK) ? "on" : "off");
137 store_extended_tag(struct device *dev,
138 struct device_attribute *attr,
142 struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
143 uint32_t val = 0, enable;
145 if (strncmp(buf, "on", 2) == 0)
147 else if (strncmp(buf, "off", 3) == 0)
152 pci_cfg_access_lock(pci_dev);
153 pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
154 PCI_DEV_CAP_REG, &val);
155 if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) { /* Not supported */
156 pci_cfg_access_unlock(pci_dev);
161 pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
162 PCI_DEV_CTRL_REG, &val);
164 val |= PCI_DEV_CTRL_EXT_TAG_MASK;
166 val &= ~PCI_DEV_CTRL_EXT_TAG_MASK;
167 pci_bus_write_config_dword(pci_dev->bus, pci_dev->devfn,
168 PCI_DEV_CTRL_REG, val);
169 pci_cfg_access_unlock(pci_dev);
175 show_max_read_request_size(struct device *dev,
176 struct device_attribute *attr,
179 struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
180 int val = pcie_get_readrq(pci_dev);
182 return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%d\n", val);
186 store_max_read_request_size(struct device *dev,
187 struct device_attribute *attr,
191 struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
192 unsigned long size = 0;
195 if (strict_strtoul(buf, 0, &size) != 0)
198 ret = pcie_set_readrq(pci_dev, (int)size);
206 static DEVICE_ATTR(max_vfs, S_IRUGO | S_IWUSR, show_max_vfs, store_max_vfs);
207 #ifdef RTE_PCI_CONFIG
208 static DEVICE_ATTR(extended_tag, S_IRUGO | S_IWUSR, show_extended_tag,
210 static DEVICE_ATTR(max_read_request_size, S_IRUGO | S_IWUSR,
211 show_max_read_request_size, store_max_read_request_size);
214 static struct attribute *dev_attrs[] = {
215 &dev_attr_max_vfs.attr,
216 #ifdef RTE_PCI_CONFIG
217 &dev_attr_extended_tag.attr,
218 &dev_attr_max_read_request_size.attr,
223 static const struct attribute_group dev_attr_grp = {
228 pci_lock(struct pci_dev * pdev)
230 /* Some function names changes between 3.2.0 and 3.3.0... */
231 #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 3, 0)
232 pci_block_user_cfg_access(pdev);
235 return pci_cfg_access_trylock(pdev);
240 pci_unlock(struct pci_dev * pdev)
242 /* Some function names changes between 3.2.0 and 3.3.0... */
243 #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 3, 0)
244 pci_unblock_user_cfg_access(pdev);
246 pci_cfg_access_unlock(pdev);
251 * It masks the msix on/off of generating MSI-X messages.
254 igbuio_msix_mask_irq(struct msi_desc *desc, int32_t state)
256 uint32_t mask_bits = desc->masked;
257 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
258 PCI_MSIX_ENTRY_VECTOR_CTRL;
261 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
263 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
265 if (mask_bits != desc->masked) {
266 writel(mask_bits, desc->mask_base + offset);
267 readl(desc->mask_base);
268 desc->masked = mask_bits;
275 * This function sets/clears the masks for generating LSC interrupts.
278 * The pointer to struct uio_info.
280 * The on/off flag of masking LSC.
282 * -On success, zero value.
283 * -On failure, a negative value.
286 igbuio_set_interrupt_mask(struct rte_uio_pci_dev *udev, int32_t state)
288 struct pci_dev *pdev = udev->pdev;
290 if (udev->mode == RTE_INTR_MODE_MSIX) {
291 struct msi_desc *desc;
293 list_for_each_entry(desc, &pdev->msi_list, list) {
294 igbuio_msix_mask_irq(desc, state);
296 } else if (udev->mode == RTE_INTR_MODE_LEGACY) {
300 pci_read_config_dword(pdev, PCI_COMMAND, &status);
303 new = old & (~PCI_COMMAND_INTX_DISABLE);
305 new = old | PCI_COMMAND_INTX_DISABLE;
308 pci_write_config_word(pdev, PCI_COMMAND, new);
315 * This is the irqcontrol callback to be registered to uio_info.
316 * It can be used to disable/enable interrupt from user space processes.
319 * pointer to uio_info.
321 * state value. 1 to enable interrupt, 0 to disable interrupt.
325 * - On failure, a negative value.
328 igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
331 struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
332 struct pci_dev *pdev = udev->pdev;
334 spin_lock_irqsave(&udev->lock, flags);
335 if (!pci_lock(pdev)) {
336 spin_unlock_irqrestore(&udev->lock, flags);
340 igbuio_set_interrupt_mask(udev, irq_state);
343 spin_unlock_irqrestore(&udev->lock, flags);
349 * This is interrupt handler which will check if the interrupt is for the right device.
350 * If yes, disable it here and will be enable later.
353 igbuio_pci_irqhandler(int irq, struct uio_info *info)
355 irqreturn_t ret = IRQ_NONE;
357 struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
358 struct pci_dev *pdev = udev->pdev;
359 uint32_t cmd_status_dword;
362 spin_lock_irqsave(&udev->lock, flags);
363 /* block userspace PCI config reads/writes */
367 /* for legacy mode, interrupt maybe shared */
368 if (udev->mode == RTE_INTR_MODE_LEGACY) {
369 pci_read_config_dword(pdev, PCI_COMMAND, &cmd_status_dword);
370 status = cmd_status_dword >> 16;
371 /* interrupt is not ours, goes to out */
372 if (!(status & PCI_STATUS_INTERRUPT))
376 igbuio_set_interrupt_mask(udev, 0);
379 /* unblock userspace PCI config reads/writes */
382 spin_unlock_irqrestore(&udev->lock, flags);
383 pr_info("irq 0x%x %s\n", irq, (ret == IRQ_HANDLED) ? "handled" : "not handled");
388 #ifdef CONFIG_XEN_DOM0
390 igbuio_dom0_mmap_phys(struct uio_info *info, struct vm_area_struct *vma)
394 idx = (int)vma->vm_pgoff;
395 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
396 vma->vm_page_prot.pgprot |= _PAGE_IOMAP;
398 return remap_pfn_range(vma,
400 info->mem[idx].addr >> PAGE_SHIFT,
401 vma->vm_end - vma->vm_start,
406 * This is uio device mmap method which will use igbuio mmap for Xen
410 igbuio_dom0_pci_mmap(struct uio_info *info, struct vm_area_struct *vma)
414 if (vma->vm_pgoff >= MAX_UIO_MAPS)
417 if (info->mem[vma->vm_pgoff].size == 0)
420 idx = (int)vma->vm_pgoff;
421 switch (info->mem[idx].memtype) {
423 return igbuio_dom0_mmap_phys(info, vma);
424 case UIO_MEM_LOGICAL:
425 case UIO_MEM_VIRTUAL:
432 /* Remap pci resources described by bar #pci_bar in uio resource n. */
434 igbuio_pci_setup_iomem(struct pci_dev *dev, struct uio_info *info,
435 int n, int pci_bar, const char *name)
437 unsigned long addr, len;
440 if (sizeof(info->mem) / sizeof(info->mem[0]) <= n)
443 addr = pci_resource_start(dev, pci_bar);
444 len = pci_resource_len(dev, pci_bar);
445 if (addr == 0 || len == 0)
447 internal_addr = ioremap(addr, len);
448 if (internal_addr == NULL)
450 info->mem[n].name = name;
451 info->mem[n].addr = addr;
452 info->mem[n].internal_addr = internal_addr;
453 info->mem[n].size = len;
454 info->mem[n].memtype = UIO_MEM_PHYS;
458 /* Get pci port io resources described by bar #pci_bar in uio resource n. */
460 igbuio_pci_setup_ioport(struct pci_dev *dev, struct uio_info *info,
461 int n, int pci_bar, const char *name)
463 unsigned long addr, len;
465 if (sizeof(info->port) / sizeof(info->port[0]) <= n)
468 addr = pci_resource_start(dev, pci_bar);
469 len = pci_resource_len(dev, pci_bar);
470 if (addr == 0 || len == 0)
473 info->port[n].name = name;
474 info->port[n].start = addr;
475 info->port[n].size = len;
476 info->port[n].porttype = UIO_PORT_X86;
481 /* Unmap previously ioremap'd resources */
483 igbuio_pci_release_iomem(struct uio_info *info)
487 for (i = 0; i < MAX_UIO_MAPS; i++) {
488 if (info->mem[i].internal_addr)
489 iounmap(info->mem[i].internal_addr);
494 igbuio_setup_bars(struct pci_dev *dev, struct uio_info *info)
496 int i, iom, iop, ret;
498 static const char *bar_names[PCI_STD_RESOURCE_END + 1] = {
510 for (i = 0; i != sizeof(bar_names) / sizeof(bar_names[0]); i++) {
511 if (pci_resource_len(dev, i) != 0 &&
512 pci_resource_start(dev, i) != 0) {
513 flags = pci_resource_flags(dev, i);
514 if (flags & IORESOURCE_MEM) {
515 ret = igbuio_pci_setup_iomem(dev, info, iom,
520 } else if (flags & IORESOURCE_IO) {
521 ret = igbuio_pci_setup_ioport(dev, info, iop,
530 return (iom != 0) ? ret : -ENOENT;
533 #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)
538 igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
540 struct rte_uio_pci_dev *udev;
541 struct msix_entry msix_entry;
544 udev = kzalloc(sizeof(struct rte_uio_pci_dev), GFP_KERNEL);
549 * enable device: ask low-level code to enable I/O and
552 err = pci_enable_device(dev);
554 dev_err(&dev->dev, "Cannot enable PCI device\n");
559 * reserve device's PCI memory regions for use by this
562 err = pci_request_regions(dev, "igb_uio");
564 dev_err(&dev->dev, "Cannot request regions\n");
568 /* enable bus mastering on the device */
571 /* remap IO memory */
572 err = igbuio_setup_bars(dev, &udev->info);
574 goto fail_release_iomem;
576 /* set 64-bit DMA mask */
577 err = pci_set_dma_mask(dev, DMA_BIT_MASK(64));
579 dev_err(&dev->dev, "Cannot set DMA mask\n");
580 goto fail_release_iomem;
583 err = pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64));
585 dev_err(&dev->dev, "Cannot set consistent DMA mask\n");
586 goto fail_release_iomem;
590 udev->info.name = "igb_uio";
591 udev->info.version = "0.1";
592 udev->info.handler = igbuio_pci_irqhandler;
593 udev->info.irqcontrol = igbuio_pci_irqcontrol;
594 #ifdef CONFIG_XEN_DOM0
595 /* check if the driver run on Xen Dom0 */
596 if (xen_initial_domain())
597 udev->info.mmap = igbuio_dom0_pci_mmap;
599 udev->info.priv = udev;
601 udev->mode = RTE_INTR_MODE_LEGACY;
602 spin_lock_init(&udev->lock);
604 /* check if it need to try msix first */
605 if (igbuio_intr_mode_preferred == RTE_INTR_MODE_MSIX) {
606 /* Only 1 msi-x vector needed */
607 msix_entry.entry = 0;
608 if (pci_enable_msix(dev, &msix_entry, 1) == 0) {
609 dev_dbg(&dev->dev, "using MSI-X");
610 udev->mode = RTE_INTR_MODE_MSIX;
613 pci_disable_msix(udev->pdev);
614 pr_info("fail to enable pci msix, or not enough msix entries\n");
617 switch (udev->mode) {
618 case RTE_INTR_MODE_MSIX:
619 udev->info.irq_flags = 0;
620 udev->info.irq = msix_entry.vector;
622 case RTE_INTR_MODE_MSI:
624 case RTE_INTR_MODE_LEGACY:
625 udev->info.irq_flags = IRQF_SHARED;
626 udev->info.irq = dev->irq;
632 pci_set_drvdata(dev, udev);
633 igbuio_pci_irqcontrol(&udev->info, 0);
635 err = sysfs_create_group(&dev->dev.kobj, &dev_attr_grp);
637 goto fail_release_iomem;
639 /* register uio driver */
640 err = uio_register_device(&dev->dev, &udev->info);
642 goto fail_remove_group;
644 pr_info("uio device registered with irq %lx\n", udev->info.irq);
649 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
651 igbuio_pci_release_iomem(&udev->info);
652 if (udev->mode == RTE_INTR_MODE_MSIX)
653 pci_disable_msix(udev->pdev);
654 pci_release_regions(dev);
656 pci_disable_device(dev);
664 igbuio_pci_remove(struct pci_dev *dev)
666 struct uio_info *info = pci_get_drvdata(dev);
667 struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
669 if (info->priv == NULL) {
670 pr_notice("Not igbuio device\n");
674 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
675 uio_unregister_device(info);
676 igbuio_pci_release_iomem(info);
677 if (udev->mode == RTE_INTR_MODE_MSIX)
678 pci_disable_msix(dev);
679 pci_release_regions(dev);
680 pci_disable_device(dev);
681 pci_set_drvdata(dev, NULL);
686 igbuio_config_intr_mode(char *intr_str)
689 pr_info("Use MSIX interrupt by default\n");
693 if (!strcmp(intr_str, RTE_INTR_MODE_MSIX_NAME)) {
694 igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
695 pr_info("Use MSIX interrupt\n");
696 } else if (!strcmp(intr_str, RTE_INTR_MODE_LEGACY_NAME)) {
697 igbuio_intr_mode_preferred = RTE_INTR_MODE_LEGACY;
698 pr_info("Use legacy interrupt\n");
700 pr_info("Error: bad parameter - %s\n", intr_str);
707 static struct pci_driver igbuio_pci_driver = {
710 .probe = igbuio_pci_probe,
711 .remove = igbuio_pci_remove,
715 igbuio_pci_init_module(void)
719 ret = igbuio_config_intr_mode(intr_mode);
723 return pci_register_driver(&igbuio_pci_driver);
727 igbuio_pci_exit_module(void)
729 pci_unregister_driver(&igbuio_pci_driver);
732 module_init(igbuio_pci_init_module);
733 module_exit(igbuio_pci_exit_module);
735 module_param(intr_mode, charp, S_IRUGO);
736 MODULE_PARM_DESC(intr_mode,
737 "igb_uio interrupt mode (default=msix):\n"
738 " " RTE_INTR_MODE_MSIX_NAME " Use MSIX interrupt\n"
739 " " RTE_INTR_MODE_LEGACY_NAME " Use Legacy interrupt\n"
742 MODULE_DESCRIPTION("UIO driver for Intel IGB PCI cards");
743 MODULE_LICENSE("GPL");
744 MODULE_AUTHOR("Intel Corporation");