4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * The full GNU General Public License is included in this distribution
19 * in the file called LICENSE.GPL.
21 * Contact Information:
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27 #include <linux/device.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/uio_driver.h>
32 #include <linux/msi.h>
33 #include <linux/version.h>
35 #ifdef CONFIG_XEN_DOM0
38 #include <rte_pci_dev_features.h>
43 #define PCI_SYS_FILE_BUF_SIZE 10
44 #define PCI_DEV_CAP_REG 0xA4
45 #define PCI_DEV_CTRL_REG 0xA8
46 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
47 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
48 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
52 * A structure describing the private information for a uio device.
54 struct rte_uio_pci_dev {
57 enum rte_intr_mode mode;
60 static char *intr_mode = NULL;
61 static enum rte_intr_mode igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
63 static inline struct rte_uio_pci_dev *
64 igbuio_get_uio_pci_dev(struct uio_info *info)
66 return container_of(info, struct rte_uio_pci_dev, info);
71 show_max_vfs(struct device *dev, struct device_attribute *attr,
74 return snprintf(buf, 10, "%u\n",
75 pci_num_vf(container_of(dev, struct pci_dev, dev)));
79 store_max_vfs(struct device *dev, struct device_attribute *attr,
80 const char *buf, size_t count)
83 unsigned long max_vfs;
84 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
86 if (0 != strict_strtoul(buf, 0, &max_vfs))
90 pci_disable_sriov(pdev);
91 else if (0 == pci_num_vf(pdev))
92 err = pci_enable_sriov(pdev, max_vfs);
93 else /* do nothing if change max_vfs number */
96 return err ? err : count;
101 show_extended_tag(struct device *dev, struct device_attribute *attr, char *buf)
103 struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
106 pci_read_config_dword(pci_dev, PCI_DEV_CAP_REG, &val);
107 if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) /* Not supported */
108 return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n", "invalid");
111 pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
112 PCI_DEV_CTRL_REG, &val);
114 return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n",
115 (val & PCI_DEV_CTRL_EXT_TAG_MASK) ? "on" : "off");
119 store_extended_tag(struct device *dev,
120 struct device_attribute *attr,
124 struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
125 uint32_t val = 0, enable;
127 if (strncmp(buf, "on", 2) == 0)
129 else if (strncmp(buf, "off", 3) == 0)
134 pci_cfg_access_lock(pci_dev);
135 pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
136 PCI_DEV_CAP_REG, &val);
137 if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) { /* Not supported */
138 pci_cfg_access_unlock(pci_dev);
143 pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
144 PCI_DEV_CTRL_REG, &val);
146 val |= PCI_DEV_CTRL_EXT_TAG_MASK;
148 val &= ~PCI_DEV_CTRL_EXT_TAG_MASK;
149 pci_bus_write_config_dword(pci_dev->bus, pci_dev->devfn,
150 PCI_DEV_CTRL_REG, val);
151 pci_cfg_access_unlock(pci_dev);
157 show_max_read_request_size(struct device *dev,
158 struct device_attribute *attr,
161 struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
162 int val = pcie_get_readrq(pci_dev);
164 return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%d\n", val);
168 store_max_read_request_size(struct device *dev,
169 struct device_attribute *attr,
173 struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
174 unsigned long size = 0;
177 if (strict_strtoul(buf, 0, &size) != 0)
180 ret = pcie_set_readrq(pci_dev, (int)size);
188 static DEVICE_ATTR(max_vfs, S_IRUGO | S_IWUSR, show_max_vfs, store_max_vfs);
189 #ifdef RTE_PCI_CONFIG
190 static DEVICE_ATTR(extended_tag, S_IRUGO | S_IWUSR, show_extended_tag,
192 static DEVICE_ATTR(max_read_request_size, S_IRUGO | S_IWUSR,
193 show_max_read_request_size, store_max_read_request_size);
196 static struct attribute *dev_attrs[] = {
197 &dev_attr_max_vfs.attr,
198 #ifdef RTE_PCI_CONFIG
199 &dev_attr_extended_tag.attr,
200 &dev_attr_max_read_request_size.attr,
205 static const struct attribute_group dev_attr_grp = {
209 * It masks the msix on/off of generating MSI-X messages.
212 igbuio_msix_mask_irq(struct msi_desc *desc, int32_t state)
214 u32 mask_bits = desc->masked;
215 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
216 PCI_MSIX_ENTRY_VECTOR_CTRL;
219 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
221 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
223 if (mask_bits != desc->masked) {
224 writel(mask_bits, desc->mask_base + offset);
225 readl(desc->mask_base);
226 desc->masked = mask_bits;
231 igbuio_msi_mask_irq(struct irq_data *data, u32 enable)
233 struct msi_desc *desc = irq_data_get_msi(data);
234 u32 mask_bits = desc->masked;
235 unsigned offset = data->irq - desc->dev->irq;
236 u32 mask = 1 << offset;
237 u32 flag = enable << offset;
242 if (desc->msi_attrib.maskbit && mask_bits != desc->masked) {
243 pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits);
244 desc->masked = mask_bits;
249 * This is the irqcontrol callback to be registered to uio_info.
250 * It can be used to disable/enable interrupt from user space processes.
253 * pointer to uio_info.
255 * state value. 1 to enable interrupt, 0 to disable interrupt.
259 * - On failure, a negative value.
262 igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
264 struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
265 struct pci_dev *pdev = udev->pdev;
267 pci_cfg_access_lock(pdev);
268 if (udev->mode == RTE_INTR_MODE_LEGACY)
269 pci_intx(pdev, !!irq_state);
270 else if (udev->mode == RTE_INTR_MODE_MSI) {
271 struct irq_data *data = irq_get_irq_data(pdev->irq);
273 igbuio_msi_mask_irq(data, !!irq_state);
274 } else if (udev->mode == RTE_INTR_MODE_MSIX) {
275 struct msi_desc *desc;
277 list_for_each_entry(desc, &pdev->msi_list, list)
278 igbuio_msix_mask_irq(desc, irq_state);
280 pci_cfg_access_unlock(pdev);
286 * This is interrupt handler which will check if the interrupt is for the right device.
287 * If yes, disable it here and will be enable later.
290 igbuio_pci_irqhandler(int irq, struct uio_info *info)
292 struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
294 /* Legacy mode need to mask in hardware */
295 if (udev->mode == RTE_INTR_MODE_LEGACY &&
296 !pci_check_and_mask_intx(udev->pdev))
299 /* Message signal mode, no share IRQ and automasked */
303 #ifdef CONFIG_XEN_DOM0
305 igbuio_dom0_mmap_phys(struct uio_info *info, struct vm_area_struct *vma)
309 idx = (int)vma->vm_pgoff;
310 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
311 vma->vm_page_prot.pgprot |= _PAGE_IOMAP;
313 return remap_pfn_range(vma,
315 info->mem[idx].addr >> PAGE_SHIFT,
316 vma->vm_end - vma->vm_start,
321 * This is uio device mmap method which will use igbuio mmap for Xen
325 igbuio_dom0_pci_mmap(struct uio_info *info, struct vm_area_struct *vma)
329 if (vma->vm_pgoff >= MAX_UIO_MAPS)
332 if (info->mem[vma->vm_pgoff].size == 0)
335 idx = (int)vma->vm_pgoff;
336 switch (info->mem[idx].memtype) {
338 return igbuio_dom0_mmap_phys(info, vma);
339 case UIO_MEM_LOGICAL:
340 case UIO_MEM_VIRTUAL:
347 /* Remap pci resources described by bar #pci_bar in uio resource n. */
349 igbuio_pci_setup_iomem(struct pci_dev *dev, struct uio_info *info,
350 int n, int pci_bar, const char *name)
352 unsigned long addr, len;
355 if (sizeof(info->mem) / sizeof(info->mem[0]) <= n)
358 addr = pci_resource_start(dev, pci_bar);
359 len = pci_resource_len(dev, pci_bar);
360 if (addr == 0 || len == 0)
362 internal_addr = ioremap(addr, len);
363 if (internal_addr == NULL)
365 info->mem[n].name = name;
366 info->mem[n].addr = addr;
367 info->mem[n].internal_addr = internal_addr;
368 info->mem[n].size = len;
369 info->mem[n].memtype = UIO_MEM_PHYS;
373 /* Get pci port io resources described by bar #pci_bar in uio resource n. */
375 igbuio_pci_setup_ioport(struct pci_dev *dev, struct uio_info *info,
376 int n, int pci_bar, const char *name)
378 unsigned long addr, len;
380 if (sizeof(info->port) / sizeof(info->port[0]) <= n)
383 addr = pci_resource_start(dev, pci_bar);
384 len = pci_resource_len(dev, pci_bar);
385 if (addr == 0 || len == 0)
388 info->port[n].name = name;
389 info->port[n].start = addr;
390 info->port[n].size = len;
391 info->port[n].porttype = UIO_PORT_X86;
396 /* Unmap previously ioremap'd resources */
398 igbuio_pci_release_iomem(struct uio_info *info)
402 for (i = 0; i < MAX_UIO_MAPS; i++) {
403 if (info->mem[i].internal_addr)
404 iounmap(info->mem[i].internal_addr);
409 igbuio_setup_bars(struct pci_dev *dev, struct uio_info *info)
411 int i, iom, iop, ret;
413 static const char *bar_names[PCI_STD_RESOURCE_END + 1] = {
425 for (i = 0; i != sizeof(bar_names) / sizeof(bar_names[0]); i++) {
426 if (pci_resource_len(dev, i) != 0 &&
427 pci_resource_start(dev, i) != 0) {
428 flags = pci_resource_flags(dev, i);
429 if (flags & IORESOURCE_MEM) {
430 ret = igbuio_pci_setup_iomem(dev, info, iom,
435 } else if (flags & IORESOURCE_IO) {
436 ret = igbuio_pci_setup_ioport(dev, info, iop,
445 return (iom != 0) ? ret : -ENOENT;
448 #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)
453 igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
455 struct rte_uio_pci_dev *udev;
456 struct msix_entry msix_entry;
459 udev = kzalloc(sizeof(struct rte_uio_pci_dev), GFP_KERNEL);
464 * enable device: ask low-level code to enable I/O and
467 err = pci_enable_device(dev);
469 dev_err(&dev->dev, "Cannot enable PCI device\n");
474 * reserve device's PCI memory regions for use by this
477 err = pci_request_regions(dev, "igb_uio");
479 dev_err(&dev->dev, "Cannot request regions\n");
483 /* enable bus mastering on the device */
486 /* remap IO memory */
487 err = igbuio_setup_bars(dev, &udev->info);
489 goto fail_release_iomem;
491 /* set 64-bit DMA mask */
492 err = pci_set_dma_mask(dev, DMA_BIT_MASK(64));
494 dev_err(&dev->dev, "Cannot set DMA mask\n");
495 goto fail_release_iomem;
498 err = pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64));
500 dev_err(&dev->dev, "Cannot set consistent DMA mask\n");
501 goto fail_release_iomem;
505 udev->info.name = "igb_uio";
506 udev->info.version = "0.1";
507 udev->info.handler = igbuio_pci_irqhandler;
508 udev->info.irqcontrol = igbuio_pci_irqcontrol;
509 udev->info.irq = dev->irq;
510 #ifdef CONFIG_XEN_DOM0
511 /* check if the driver run on Xen Dom0 */
512 if (xen_initial_domain())
513 udev->info.mmap = igbuio_dom0_pci_mmap;
515 udev->info.priv = udev;
518 switch (igbuio_intr_mode_preferred) {
519 case RTE_INTR_MODE_NONE:
522 case RTE_INTR_MODE_MSIX:
523 /* Only 1 msi-x vector needed */
524 msix_entry.entry = 0;
525 if (pci_enable_msix(dev, &msix_entry, 1) == 0) {
526 dev_dbg(&dev->dev, "using MSI-X");
527 udev->info.irq = msix_entry.vector;
528 udev->mode = RTE_INTR_MODE_MSIX;
531 /* fall back to MSI */
532 case RTE_INTR_MODE_MSI:
533 if (pci_enable_msi(dev) == 0) {
534 dev_dbg(&dev->dev, "using MSI");
535 udev->mode = RTE_INTR_MODE_MSI;
538 /* fall back to INTX */
539 case RTE_INTR_MODE_LEGACY:
540 if (pci_intx_mask_supported(dev)) {
541 dev_dbg(&dev->dev, "using INTX");
542 udev->info.irq_flags = IRQF_SHARED;
543 udev->mode = RTE_INTR_MODE_LEGACY;
545 dev_err(&dev->dev, "PCI INTX mask not supported\n");
547 goto fail_release_iomem;
551 dev_err(&dev->dev, "invalid IRQ mode %u",
552 igbuio_intr_mode_preferred);
554 goto fail_release_iomem;
557 err = sysfs_create_group(&dev->dev.kobj, &dev_attr_grp);
559 goto fail_release_iomem;
561 /* register uio driver */
562 err = uio_register_device(&dev->dev, &udev->info);
564 goto fail_remove_group;
566 pci_set_drvdata(dev, udev);
568 dev_info(&dev->dev, "uio device registered with irq %lx\n",
574 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
576 igbuio_pci_release_iomem(&udev->info);
577 if (udev->mode == RTE_INTR_MODE_MSIX)
578 pci_disable_msix(udev->pdev);
579 else if (udev->mode == RTE_INTR_MODE_MSI)
580 pci_disable_msi(udev->pdev);
581 pci_release_regions(dev);
583 pci_disable_device(dev);
591 igbuio_pci_remove(struct pci_dev *dev)
593 struct uio_info *info = pci_get_drvdata(dev);
594 struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
596 if (info->priv == NULL) {
597 pr_notice("Not igbuio device\n");
601 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
602 uio_unregister_device(info);
603 igbuio_pci_release_iomem(info);
604 if (udev->mode == RTE_INTR_MODE_MSIX)
605 pci_disable_msix(dev);
606 else if (udev->mode == RTE_INTR_MODE_MSI)
607 pci_disable_msi(dev);
608 pci_release_regions(dev);
609 pci_disable_device(dev);
610 pci_set_drvdata(dev, NULL);
615 igbuio_config_intr_mode(char *intr_str)
618 pr_info("Use MSIX interrupt by default\n");
622 if (!strcmp(intr_str, RTE_INTR_MODE_MSIX_NAME)) {
623 igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
624 pr_info("Use MSIX interrupt\n");
625 } else if (!strcmp(intr_str, RTE_INTR_MODE_MSI_NAME)) {
626 igbuio_intr_mode_preferred = RTE_INTR_MODE_MSI;
627 pr_info("Use MSI interrupt\n");
628 } else if (!strcmp(intr_str, RTE_INTR_MODE_LEGACY_NAME)) {
629 igbuio_intr_mode_preferred = RTE_INTR_MODE_LEGACY;
630 pr_info("Use legacy interrupt\n");
632 pr_info("Error: bad parameter - %s\n", intr_str);
639 static struct pci_driver igbuio_pci_driver = {
642 .probe = igbuio_pci_probe,
643 .remove = igbuio_pci_remove,
647 igbuio_pci_init_module(void)
651 ret = igbuio_config_intr_mode(intr_mode);
655 return pci_register_driver(&igbuio_pci_driver);
659 igbuio_pci_exit_module(void)
661 pci_unregister_driver(&igbuio_pci_driver);
664 module_init(igbuio_pci_init_module);
665 module_exit(igbuio_pci_exit_module);
667 module_param(intr_mode, charp, S_IRUGO);
668 MODULE_PARM_DESC(intr_mode,
669 "igb_uio interrupt mode (default=msix):\n"
670 " " RTE_INTR_MODE_MSIX_NAME " Use MSIX interrupt\n"
671 " " RTE_INTR_MODE_MSI_NAME " Use MSI interrupt\n"
672 " " RTE_INTR_MODE_LEGACY_NAME " Use Legacy interrupt\n"
675 MODULE_DESCRIPTION("UIO driver for Intel IGB PCI cards");
676 MODULE_LICENSE("GPL");
677 MODULE_AUTHOR("Intel Corporation");