4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * The full GNU General Public License is included in this distribution
19 * in the file called LICENSE.GPL.
21 * Contact Information:
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27 #include <linux/device.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/uio_driver.h>
32 #include <linux/msi.h>
33 #include <linux/version.h>
35 #ifdef CONFIG_XEN_DOM0
38 #include <rte_pci_dev_features.h>
41 * MSI-X related macros, copy from linux/pci_regs.h in kernel 2.6.39,
42 * but none of them in kernel 2.6.35.
44 #ifndef PCI_MSIX_ENTRY_SIZE
45 #define PCI_MSIX_ENTRY_SIZE 16
46 #define PCI_MSIX_ENTRY_LOWER_ADDR 0
47 #define PCI_MSIX_ENTRY_UPPER_ADDR 4
48 #define PCI_MSIX_ENTRY_DATA 8
49 #define PCI_MSIX_ENTRY_VECTOR_CTRL 12
50 #define PCI_MSIX_ENTRY_CTRL_MASKBIT 1
54 #define PCI_SYS_FILE_BUF_SIZE 10
55 #define PCI_DEV_CAP_REG 0xA4
56 #define PCI_DEV_CTRL_REG 0xA8
57 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
58 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
59 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
62 #define IGBUIO_NUM_MSI_VECTORS 1
65 * A structure describing the private information for a uio device.
67 struct rte_uio_pci_dev {
70 spinlock_t lock; /* spinlock for accessing PCI config space or msix data in multi tasks/isr */
71 enum rte_intr_mode mode;
73 msix_entries[IGBUIO_NUM_MSI_VECTORS]; /* pointer to the msix vectors to be allocated later */
76 static char *intr_mode = NULL;
77 static enum rte_intr_mode igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
79 static inline struct rte_uio_pci_dev *
80 igbuio_get_uio_pci_dev(struct uio_info *info)
82 return container_of(info, struct rte_uio_pci_dev, info);
86 #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 34)
87 static int pci_num_vf(struct pci_dev *dev)
96 } *iov = (struct iov *)dev->sriov;
101 return iov->nr_virtfn;
106 show_max_vfs(struct device *dev, struct device_attribute *attr,
109 return snprintf(buf, 10, "%u\n",
110 pci_num_vf(container_of(dev, struct pci_dev, dev)));
114 store_max_vfs(struct device *dev, struct device_attribute *attr,
115 const char *buf, size_t count)
118 unsigned long max_vfs;
119 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
121 if (0 != strict_strtoul(buf, 0, &max_vfs))
125 pci_disable_sriov(pdev);
126 else if (0 == pci_num_vf(pdev))
127 err = pci_enable_sriov(pdev, max_vfs);
128 else /* do nothing if change max_vfs number */
131 return err ? err : count;
134 #ifdef RTE_PCI_CONFIG
136 show_extended_tag(struct device *dev, struct device_attribute *attr, char *buf)
138 struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
141 pci_read_config_dword(pci_dev, PCI_DEV_CAP_REG, &val);
142 if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) /* Not supported */
143 return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n", "invalid");
146 pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
147 PCI_DEV_CTRL_REG, &val);
149 return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n",
150 (val & PCI_DEV_CTRL_EXT_TAG_MASK) ? "on" : "off");
154 store_extended_tag(struct device *dev,
155 struct device_attribute *attr,
159 struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
160 uint32_t val = 0, enable;
162 if (strncmp(buf, "on", 2) == 0)
164 else if (strncmp(buf, "off", 3) == 0)
169 pci_cfg_access_lock(pci_dev);
170 pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
171 PCI_DEV_CAP_REG, &val);
172 if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) { /* Not supported */
173 pci_cfg_access_unlock(pci_dev);
178 pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
179 PCI_DEV_CTRL_REG, &val);
181 val |= PCI_DEV_CTRL_EXT_TAG_MASK;
183 val &= ~PCI_DEV_CTRL_EXT_TAG_MASK;
184 pci_bus_write_config_dword(pci_dev->bus, pci_dev->devfn,
185 PCI_DEV_CTRL_REG, val);
186 pci_cfg_access_unlock(pci_dev);
192 show_max_read_request_size(struct device *dev,
193 struct device_attribute *attr,
196 struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
197 int val = pcie_get_readrq(pci_dev);
199 return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%d\n", val);
203 store_max_read_request_size(struct device *dev,
204 struct device_attribute *attr,
208 struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
209 unsigned long size = 0;
212 if (strict_strtoul(buf, 0, &size) != 0)
215 ret = pcie_set_readrq(pci_dev, (int)size);
223 static DEVICE_ATTR(max_vfs, S_IRUGO | S_IWUSR, show_max_vfs, store_max_vfs);
224 #ifdef RTE_PCI_CONFIG
225 static DEVICE_ATTR(extended_tag, S_IRUGO | S_IWUSR, show_extended_tag,
227 static DEVICE_ATTR(max_read_request_size, S_IRUGO | S_IWUSR,
228 show_max_read_request_size, store_max_read_request_size);
231 static struct attribute *dev_attrs[] = {
232 &dev_attr_max_vfs.attr,
233 #ifdef RTE_PCI_CONFIG
234 &dev_attr_extended_tag.attr,
235 &dev_attr_max_read_request_size.attr,
240 static const struct attribute_group dev_attr_grp = {
245 pci_lock(struct pci_dev * pdev)
247 /* Some function names changes between 3.2.0 and 3.3.0... */
248 #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 3, 0)
249 pci_block_user_cfg_access(pdev);
252 return pci_cfg_access_trylock(pdev);
257 pci_unlock(struct pci_dev * pdev)
259 /* Some function names changes between 3.2.0 and 3.3.0... */
260 #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 3, 0)
261 pci_unblock_user_cfg_access(pdev);
263 pci_cfg_access_unlock(pdev);
268 * It masks the msix on/off of generating MSI-X messages.
271 igbuio_msix_mask_irq(struct msi_desc *desc, int32_t state)
273 uint32_t mask_bits = desc->masked;
274 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
275 PCI_MSIX_ENTRY_VECTOR_CTRL;
278 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
280 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
282 if (mask_bits != desc->masked) {
283 writel(mask_bits, desc->mask_base + offset);
284 readl(desc->mask_base);
285 desc->masked = mask_bits;
292 * This function sets/clears the masks for generating LSC interrupts.
295 * The pointer to struct uio_info.
297 * The on/off flag of masking LSC.
299 * -On success, zero value.
300 * -On failure, a negative value.
303 igbuio_set_interrupt_mask(struct rte_uio_pci_dev *udev, int32_t state)
305 struct pci_dev *pdev = udev->pdev;
307 if (udev->mode == RTE_INTR_MODE_MSIX) {
308 struct msi_desc *desc;
310 list_for_each_entry(desc, &pdev->msi_list, list) {
311 igbuio_msix_mask_irq(desc, state);
313 } else if (udev->mode == RTE_INTR_MODE_LEGACY) {
317 pci_read_config_dword(pdev, PCI_COMMAND, &status);
320 new = old & (~PCI_COMMAND_INTX_DISABLE);
322 new = old | PCI_COMMAND_INTX_DISABLE;
325 pci_write_config_word(pdev, PCI_COMMAND, new);
332 * This is the irqcontrol callback to be registered to uio_info.
333 * It can be used to disable/enable interrupt from user space processes.
336 * pointer to uio_info.
338 * state value. 1 to enable interrupt, 0 to disable interrupt.
342 * - On failure, a negative value.
345 igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
348 struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
349 struct pci_dev *pdev = udev->pdev;
351 spin_lock_irqsave(&udev->lock, flags);
352 if (!pci_lock(pdev)) {
353 spin_unlock_irqrestore(&udev->lock, flags);
357 igbuio_set_interrupt_mask(udev, irq_state);
360 spin_unlock_irqrestore(&udev->lock, flags);
366 * This is interrupt handler which will check if the interrupt is for the right device.
367 * If yes, disable it here and will be enable later.
370 igbuio_pci_irqhandler(int irq, struct uio_info *info)
372 irqreturn_t ret = IRQ_NONE;
374 struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
375 struct pci_dev *pdev = udev->pdev;
376 uint32_t cmd_status_dword;
379 spin_lock_irqsave(&udev->lock, flags);
380 /* block userspace PCI config reads/writes */
384 /* for legacy mode, interrupt maybe shared */
385 if (udev->mode == RTE_INTR_MODE_LEGACY) {
386 pci_read_config_dword(pdev, PCI_COMMAND, &cmd_status_dword);
387 status = cmd_status_dword >> 16;
388 /* interrupt is not ours, goes to out */
389 if (!(status & PCI_STATUS_INTERRUPT))
393 igbuio_set_interrupt_mask(udev, 0);
396 /* unblock userspace PCI config reads/writes */
399 spin_unlock_irqrestore(&udev->lock, flags);
400 pr_info("irq 0x%x %s\n", irq, (ret == IRQ_HANDLED) ? "handled" : "not handled");
405 #ifdef CONFIG_XEN_DOM0
407 igbuio_dom0_mmap_phys(struct uio_info *info, struct vm_area_struct *vma)
411 idx = (int)vma->vm_pgoff;
412 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
413 vma->vm_page_prot.pgprot |= _PAGE_IOMAP;
415 return remap_pfn_range(vma,
417 info->mem[idx].addr >> PAGE_SHIFT,
418 vma->vm_end - vma->vm_start,
423 * This is uio device mmap method which will use igbuio mmap for Xen
427 igbuio_dom0_pci_mmap(struct uio_info *info, struct vm_area_struct *vma)
431 if (vma->vm_pgoff >= MAX_UIO_MAPS)
434 if (info->mem[vma->vm_pgoff].size == 0)
437 idx = (int)vma->vm_pgoff;
438 switch (info->mem[idx].memtype) {
440 return igbuio_dom0_mmap_phys(info, vma);
441 case UIO_MEM_LOGICAL:
442 case UIO_MEM_VIRTUAL:
449 /* Remap pci resources described by bar #pci_bar in uio resource n. */
451 igbuio_pci_setup_iomem(struct pci_dev *dev, struct uio_info *info,
452 int n, int pci_bar, const char *name)
454 unsigned long addr, len;
457 if (sizeof(info->mem) / sizeof(info->mem[0]) <= n)
460 addr = pci_resource_start(dev, pci_bar);
461 len = pci_resource_len(dev, pci_bar);
462 if (addr == 0 || len == 0)
464 internal_addr = ioremap(addr, len);
465 if (internal_addr == NULL)
467 info->mem[n].name = name;
468 info->mem[n].addr = addr;
469 info->mem[n].internal_addr = internal_addr;
470 info->mem[n].size = len;
471 info->mem[n].memtype = UIO_MEM_PHYS;
475 /* Get pci port io resources described by bar #pci_bar in uio resource n. */
477 igbuio_pci_setup_ioport(struct pci_dev *dev, struct uio_info *info,
478 int n, int pci_bar, const char *name)
480 unsigned long addr, len;
482 if (sizeof(info->port) / sizeof(info->port[0]) <= n)
485 addr = pci_resource_start(dev, pci_bar);
486 len = pci_resource_len(dev, pci_bar);
487 if (addr == 0 || len == 0)
490 info->port[n].name = name;
491 info->port[n].start = addr;
492 info->port[n].size = len;
493 info->port[n].porttype = UIO_PORT_X86;
498 /* Unmap previously ioremap'd resources */
500 igbuio_pci_release_iomem(struct uio_info *info)
504 for (i = 0; i < MAX_UIO_MAPS; i++) {
505 if (info->mem[i].internal_addr)
506 iounmap(info->mem[i].internal_addr);
511 igbuio_setup_bars(struct pci_dev *dev, struct uio_info *info)
513 int i, iom, iop, ret;
515 static const char *bar_names[PCI_STD_RESOURCE_END + 1] = {
527 for (i = 0; i != sizeof(bar_names) / sizeof(bar_names[0]); i++) {
528 if (pci_resource_len(dev, i) != 0 &&
529 pci_resource_start(dev, i) != 0) {
530 flags = pci_resource_flags(dev, i);
531 if (flags & IORESOURCE_MEM) {
532 ret = igbuio_pci_setup_iomem(dev, info, iom,
537 } else if (flags & IORESOURCE_IO) {
538 ret = igbuio_pci_setup_ioport(dev, info, iop,
547 return (iom != 0) ? ret : -ENOENT;
550 #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)
555 igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
557 struct rte_uio_pci_dev *udev;
560 udev = kzalloc(sizeof(struct rte_uio_pci_dev), GFP_KERNEL);
565 * enable device: ask low-level code to enable I/O and
568 err = pci_enable_device(dev);
570 dev_err(&dev->dev, "Cannot enable PCI device\n");
575 * reserve device's PCI memory regions for use by this
578 err = pci_request_regions(dev, "igb_uio");
580 dev_err(&dev->dev, "Cannot request regions\n");
584 /* enable bus mastering on the device */
587 /* remap IO memory */
588 err = igbuio_setup_bars(dev, &udev->info);
590 goto fail_release_iomem;
592 /* set 64-bit DMA mask */
593 err = pci_set_dma_mask(dev, DMA_BIT_MASK(64));
595 dev_err(&dev->dev, "Cannot set DMA mask\n");
596 goto fail_release_iomem;
599 err = pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64));
601 dev_err(&dev->dev, "Cannot set consistent DMA mask\n");
602 goto fail_release_iomem;
606 udev->info.name = "igb_uio";
607 udev->info.version = "0.1";
608 udev->info.handler = igbuio_pci_irqhandler;
609 udev->info.irqcontrol = igbuio_pci_irqcontrol;
610 #ifdef CONFIG_XEN_DOM0
611 /* check if the driver run on Xen Dom0 */
612 if (xen_initial_domain())
613 udev->info.mmap = igbuio_dom0_pci_mmap;
615 udev->info.priv = udev;
617 udev->mode = RTE_INTR_MODE_LEGACY;
618 spin_lock_init(&udev->lock);
620 /* check if it need to try msix first */
621 if (igbuio_intr_mode_preferred == RTE_INTR_MODE_MSIX) {
624 for (vector = 0; vector < IGBUIO_NUM_MSI_VECTORS; vector ++)
625 udev->msix_entries[vector].entry = vector;
627 if (pci_enable_msix(udev->pdev, udev->msix_entries, IGBUIO_NUM_MSI_VECTORS) == 0) {
628 udev->mode = RTE_INTR_MODE_MSIX;
631 pci_disable_msix(udev->pdev);
632 pr_info("fail to enable pci msix, or not enough msix entries\n");
635 switch (udev->mode) {
636 case RTE_INTR_MODE_MSIX:
637 udev->info.irq_flags = 0;
638 udev->info.irq = udev->msix_entries[0].vector;
640 case RTE_INTR_MODE_MSI:
642 case RTE_INTR_MODE_LEGACY:
643 udev->info.irq_flags = IRQF_SHARED;
644 udev->info.irq = dev->irq;
650 pci_set_drvdata(dev, udev);
651 igbuio_pci_irqcontrol(&udev->info, 0);
653 err = sysfs_create_group(&dev->dev.kobj, &dev_attr_grp);
655 goto fail_release_iomem;
657 /* register uio driver */
658 err = uio_register_device(&dev->dev, &udev->info);
660 goto fail_remove_group;
662 pr_info("uio device registered with irq %lx\n", udev->info.irq);
667 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
669 igbuio_pci_release_iomem(&udev->info);
670 if (udev->mode == RTE_INTR_MODE_MSIX)
671 pci_disable_msix(udev->pdev);
672 pci_release_regions(dev);
674 pci_disable_device(dev);
682 igbuio_pci_remove(struct pci_dev *dev)
684 struct uio_info *info = pci_get_drvdata(dev);
686 if (info->priv == NULL) {
687 pr_notice("Not igbuio device\n");
691 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
692 uio_unregister_device(info);
693 igbuio_pci_release_iomem(info);
694 if (((struct rte_uio_pci_dev *)info->priv)->mode ==
696 pci_disable_msix(dev);
697 pci_release_regions(dev);
698 pci_disable_device(dev);
699 pci_set_drvdata(dev, NULL);
704 igbuio_config_intr_mode(char *intr_str)
707 pr_info("Use MSIX interrupt by default\n");
711 if (!strcmp(intr_str, RTE_INTR_MODE_MSIX_NAME)) {
712 igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
713 pr_info("Use MSIX interrupt\n");
714 } else if (!strcmp(intr_str, RTE_INTR_MODE_LEGACY_NAME)) {
715 igbuio_intr_mode_preferred = RTE_INTR_MODE_LEGACY;
716 pr_info("Use legacy interrupt\n");
718 pr_info("Error: bad parameter - %s\n", intr_str);
725 static struct pci_driver igbuio_pci_driver = {
728 .probe = igbuio_pci_probe,
729 .remove = igbuio_pci_remove,
733 igbuio_pci_init_module(void)
737 ret = igbuio_config_intr_mode(intr_mode);
741 return pci_register_driver(&igbuio_pci_driver);
745 igbuio_pci_exit_module(void)
747 pci_unregister_driver(&igbuio_pci_driver);
750 module_init(igbuio_pci_init_module);
751 module_exit(igbuio_pci_exit_module);
753 module_param(intr_mode, charp, S_IRUGO);
754 MODULE_PARM_DESC(intr_mode,
755 "igb_uio interrupt mode (default=msix):\n"
756 " " RTE_INTR_MODE_MSIX_NAME " Use MSIX interrupt\n"
757 " " RTE_INTR_MODE_LEGACY_NAME " Use Legacy interrupt\n"
760 MODULE_DESCRIPTION("UIO driver for Intel IGB PCI cards");
761 MODULE_LICENSE("GPL");
762 MODULE_AUTHOR("Intel Corporation");