4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * The full GNU General Public License is included in this distribution
19 * in the file called LICENSE.GPL.
21 * Contact Information:
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27 #include <linux/device.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/uio_driver.h>
32 #include <linux/msi.h>
33 #include <linux/version.h>
34 #include <linux/slab.h>
36 #ifdef CONFIG_XEN_DOM0
39 #include <rte_pci_dev_features.h>
44 #define PCI_SYS_FILE_BUF_SIZE 10
45 #define PCI_DEV_CAP_REG 0xA4
46 #define PCI_DEV_CTRL_REG 0xA8
47 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
48 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
49 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
53 * A structure describing the private information for a uio device.
55 struct rte_uio_pci_dev {
58 enum rte_intr_mode mode;
61 static char *intr_mode = NULL;
62 static enum rte_intr_mode igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
66 show_max_vfs(struct device *dev, struct device_attribute *attr,
69 return snprintf(buf, 10, "%u\n",
70 pci_num_vf(container_of(dev, struct pci_dev, dev)));
74 store_max_vfs(struct device *dev, struct device_attribute *attr,
75 const char *buf, size_t count)
78 unsigned long max_vfs;
79 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
81 if (0 != kstrtoul(buf, 0, &max_vfs))
85 pci_disable_sriov(pdev);
86 else if (0 == pci_num_vf(pdev))
87 err = pci_enable_sriov(pdev, max_vfs);
88 else /* do nothing if change max_vfs number */
91 return err ? err : count;
96 show_extended_tag(struct device *dev, struct device_attribute *attr, char *buf)
98 struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
101 pci_read_config_dword(pci_dev, PCI_DEV_CAP_REG, &val);
102 if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) /* Not supported */
103 return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n", "invalid");
106 pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
107 PCI_DEV_CTRL_REG, &val);
109 return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n",
110 (val & PCI_DEV_CTRL_EXT_TAG_MASK) ? "on" : "off");
114 store_extended_tag(struct device *dev,
115 struct device_attribute *attr,
119 struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
120 uint32_t val = 0, enable;
122 if (strncmp(buf, "on", 2) == 0)
124 else if (strncmp(buf, "off", 3) == 0)
129 pci_cfg_access_lock(pci_dev);
130 pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
131 PCI_DEV_CAP_REG, &val);
132 if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) { /* Not supported */
133 pci_cfg_access_unlock(pci_dev);
138 pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
139 PCI_DEV_CTRL_REG, &val);
141 val |= PCI_DEV_CTRL_EXT_TAG_MASK;
143 val &= ~PCI_DEV_CTRL_EXT_TAG_MASK;
144 pci_bus_write_config_dword(pci_dev->bus, pci_dev->devfn,
145 PCI_DEV_CTRL_REG, val);
146 pci_cfg_access_unlock(pci_dev);
152 show_max_read_request_size(struct device *dev,
153 struct device_attribute *attr,
156 struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
157 int val = pcie_get_readrq(pci_dev);
159 return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%d\n", val);
163 store_max_read_request_size(struct device *dev,
164 struct device_attribute *attr,
168 struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
169 unsigned long size = 0;
172 if (0 != kstrtoul(buf, 0, &size))
175 ret = pcie_set_readrq(pci_dev, (int)size);
183 static DEVICE_ATTR(max_vfs, S_IRUGO | S_IWUSR, show_max_vfs, store_max_vfs);
184 #ifdef RTE_PCI_CONFIG
185 static DEVICE_ATTR(extended_tag, S_IRUGO | S_IWUSR, show_extended_tag,
187 static DEVICE_ATTR(max_read_request_size, S_IRUGO | S_IWUSR,
188 show_max_read_request_size, store_max_read_request_size);
191 static struct attribute *dev_attrs[] = {
192 &dev_attr_max_vfs.attr,
193 #ifdef RTE_PCI_CONFIG
194 &dev_attr_extended_tag.attr,
195 &dev_attr_max_read_request_size.attr,
200 static const struct attribute_group dev_attr_grp = {
204 * It masks the msix on/off of generating MSI-X messages.
207 igbuio_msix_mask_irq(struct msi_desc *desc, int32_t state)
209 u32 mask_bits = desc->masked;
210 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
211 PCI_MSIX_ENTRY_VECTOR_CTRL;
214 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
216 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
218 if (mask_bits != desc->masked) {
219 writel(mask_bits, desc->mask_base + offset);
220 readl(desc->mask_base);
221 desc->masked = mask_bits;
226 * This is the irqcontrol callback to be registered to uio_info.
227 * It can be used to disable/enable interrupt from user space processes.
230 * pointer to uio_info.
232 * state value. 1 to enable interrupt, 0 to disable interrupt.
236 * - On failure, a negative value.
239 igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
241 struct rte_uio_pci_dev *udev = info->priv;
242 struct pci_dev *pdev = udev->pdev;
244 pci_cfg_access_lock(pdev);
245 if (udev->mode == RTE_INTR_MODE_LEGACY)
246 pci_intx(pdev, !!irq_state);
248 else if (udev->mode == RTE_INTR_MODE_MSIX) {
249 struct msi_desc *desc;
251 list_for_each_entry(desc, &pdev->msi_list, list)
252 igbuio_msix_mask_irq(desc, irq_state);
254 pci_cfg_access_unlock(pdev);
260 * This is interrupt handler which will check if the interrupt is for the right device.
261 * If yes, disable it here and will be enable later.
264 igbuio_pci_irqhandler(int irq, struct uio_info *info)
266 struct rte_uio_pci_dev *udev = info->priv;
268 /* Legacy mode need to mask in hardware */
269 if (udev->mode == RTE_INTR_MODE_LEGACY &&
270 !pci_check_and_mask_intx(udev->pdev))
273 /* Message signal mode, no share IRQ and automasked */
277 #ifdef CONFIG_XEN_DOM0
279 igbuio_dom0_mmap_phys(struct uio_info *info, struct vm_area_struct *vma)
283 idx = (int)vma->vm_pgoff;
284 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
285 #ifdef HAVE_PTE_MASK_PAGE_IOMAP
286 vma->vm_page_prot.pgprot |= _PAGE_IOMAP;
289 return remap_pfn_range(vma,
291 info->mem[idx].addr >> PAGE_SHIFT,
292 vma->vm_end - vma->vm_start,
297 * This is uio device mmap method which will use igbuio mmap for Xen
301 igbuio_dom0_pci_mmap(struct uio_info *info, struct vm_area_struct *vma)
305 if (vma->vm_pgoff >= MAX_UIO_MAPS)
308 if (info->mem[vma->vm_pgoff].size == 0)
311 idx = (int)vma->vm_pgoff;
312 switch (info->mem[idx].memtype) {
314 return igbuio_dom0_mmap_phys(info, vma);
315 case UIO_MEM_LOGICAL:
316 case UIO_MEM_VIRTUAL:
323 /* Remap pci resources described by bar #pci_bar in uio resource n. */
325 igbuio_pci_setup_iomem(struct pci_dev *dev, struct uio_info *info,
326 int n, int pci_bar, const char *name)
328 unsigned long addr, len;
331 if (sizeof(info->mem) / sizeof(info->mem[0]) <= n)
334 addr = pci_resource_start(dev, pci_bar);
335 len = pci_resource_len(dev, pci_bar);
336 if (addr == 0 || len == 0)
338 internal_addr = ioremap(addr, len);
339 if (internal_addr == NULL)
341 info->mem[n].name = name;
342 info->mem[n].addr = addr;
343 info->mem[n].internal_addr = internal_addr;
344 info->mem[n].size = len;
345 info->mem[n].memtype = UIO_MEM_PHYS;
349 /* Get pci port io resources described by bar #pci_bar in uio resource n. */
351 igbuio_pci_setup_ioport(struct pci_dev *dev, struct uio_info *info,
352 int n, int pci_bar, const char *name)
354 unsigned long addr, len;
356 if (sizeof(info->port) / sizeof(info->port[0]) <= n)
359 addr = pci_resource_start(dev, pci_bar);
360 len = pci_resource_len(dev, pci_bar);
361 if (addr == 0 || len == 0)
364 info->port[n].name = name;
365 info->port[n].start = addr;
366 info->port[n].size = len;
367 info->port[n].porttype = UIO_PORT_X86;
372 /* Unmap previously ioremap'd resources */
374 igbuio_pci_release_iomem(struct uio_info *info)
378 for (i = 0; i < MAX_UIO_MAPS; i++) {
379 if (info->mem[i].internal_addr)
380 iounmap(info->mem[i].internal_addr);
385 igbuio_setup_bars(struct pci_dev *dev, struct uio_info *info)
387 int i, iom, iop, ret;
389 static const char *bar_names[PCI_STD_RESOURCE_END + 1] = {
401 for (i = 0; i != sizeof(bar_names) / sizeof(bar_names[0]); i++) {
402 if (pci_resource_len(dev, i) != 0 &&
403 pci_resource_start(dev, i) != 0) {
404 flags = pci_resource_flags(dev, i);
405 if (flags & IORESOURCE_MEM) {
406 ret = igbuio_pci_setup_iomem(dev, info, iom,
411 } else if (flags & IORESOURCE_IO) {
412 ret = igbuio_pci_setup_ioport(dev, info, iop,
421 return (iom != 0) ? ret : -ENOENT;
424 #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)
429 igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
431 struct rte_uio_pci_dev *udev;
432 struct msix_entry msix_entry;
435 udev = kzalloc(sizeof(struct rte_uio_pci_dev), GFP_KERNEL);
440 * enable device: ask low-level code to enable I/O and
443 err = pci_enable_device(dev);
445 dev_err(&dev->dev, "Cannot enable PCI device\n");
450 * reserve device's PCI memory regions for use by this
453 err = pci_request_regions(dev, "igb_uio");
455 dev_err(&dev->dev, "Cannot request regions\n");
459 /* enable bus mastering on the device */
462 /* remap IO memory */
463 err = igbuio_setup_bars(dev, &udev->info);
465 goto fail_release_iomem;
467 /* set 64-bit DMA mask */
468 err = pci_set_dma_mask(dev, DMA_BIT_MASK(64));
470 dev_err(&dev->dev, "Cannot set DMA mask\n");
471 goto fail_release_iomem;
474 err = pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64));
476 dev_err(&dev->dev, "Cannot set consistent DMA mask\n");
477 goto fail_release_iomem;
481 udev->info.name = "igb_uio";
482 udev->info.version = "0.1";
483 udev->info.handler = igbuio_pci_irqhandler;
484 udev->info.irqcontrol = igbuio_pci_irqcontrol;
485 #ifdef CONFIG_XEN_DOM0
486 /* check if the driver run on Xen Dom0 */
487 if (xen_initial_domain())
488 udev->info.mmap = igbuio_dom0_pci_mmap;
490 udev->info.priv = udev;
493 switch (igbuio_intr_mode_preferred) {
494 case RTE_INTR_MODE_MSIX:
495 /* Only 1 msi-x vector needed */
496 msix_entry.entry = 0;
497 if (pci_enable_msix(dev, &msix_entry, 1) == 0) {
498 dev_dbg(&dev->dev, "using MSI-X");
499 udev->info.irq = msix_entry.vector;
500 udev->mode = RTE_INTR_MODE_MSIX;
503 /* fall back to INTX */
504 case RTE_INTR_MODE_LEGACY:
505 if (pci_intx_mask_supported(dev)) {
506 dev_dbg(&dev->dev, "using INTX");
507 udev->info.irq_flags = IRQF_SHARED;
508 udev->info.irq = dev->irq;
509 udev->mode = RTE_INTR_MODE_LEGACY;
512 dev_notice(&dev->dev, "PCI INTX mask not supported\n");
513 /* fall back to no IRQ */
514 case RTE_INTR_MODE_NONE:
515 udev->mode = RTE_INTR_MODE_NONE;
520 dev_err(&dev->dev, "invalid IRQ mode %u",
521 igbuio_intr_mode_preferred);
523 goto fail_release_iomem;
526 err = sysfs_create_group(&dev->dev.kobj, &dev_attr_grp);
528 goto fail_release_iomem;
530 /* register uio driver */
531 err = uio_register_device(&dev->dev, &udev->info);
533 goto fail_remove_group;
535 pci_set_drvdata(dev, udev);
537 dev_info(&dev->dev, "uio device registered with irq %lx\n",
543 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
545 igbuio_pci_release_iomem(&udev->info);
546 if (udev->mode == RTE_INTR_MODE_MSIX)
547 pci_disable_msix(udev->pdev);
548 pci_release_regions(dev);
550 pci_disable_device(dev);
558 igbuio_pci_remove(struct pci_dev *dev)
560 struct uio_info *info = pci_get_drvdata(dev);
561 struct rte_uio_pci_dev *udev;
563 if (info->priv == NULL) {
564 pr_notice("Not igbuio device\n");
569 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
570 uio_unregister_device(info);
571 igbuio_pci_release_iomem(info);
572 if (udev->mode == RTE_INTR_MODE_MSIX)
573 pci_disable_msix(dev);
574 pci_release_regions(dev);
575 pci_disable_device(dev);
576 pci_set_drvdata(dev, NULL);
581 igbuio_config_intr_mode(char *intr_str)
584 pr_info("Use MSIX interrupt by default\n");
588 if (!strcmp(intr_str, RTE_INTR_MODE_MSIX_NAME)) {
589 igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
590 pr_info("Use MSIX interrupt\n");
591 } else if (!strcmp(intr_str, RTE_INTR_MODE_LEGACY_NAME)) {
592 igbuio_intr_mode_preferred = RTE_INTR_MODE_LEGACY;
593 pr_info("Use legacy interrupt\n");
595 pr_info("Error: bad parameter - %s\n", intr_str);
602 static struct pci_driver igbuio_pci_driver = {
605 .probe = igbuio_pci_probe,
606 .remove = igbuio_pci_remove,
610 igbuio_pci_init_module(void)
614 ret = igbuio_config_intr_mode(intr_mode);
618 return pci_register_driver(&igbuio_pci_driver);
622 igbuio_pci_exit_module(void)
624 pci_unregister_driver(&igbuio_pci_driver);
627 module_init(igbuio_pci_init_module);
628 module_exit(igbuio_pci_exit_module);
630 module_param(intr_mode, charp, S_IRUGO);
631 MODULE_PARM_DESC(intr_mode,
632 "igb_uio interrupt mode (default=msix):\n"
633 " " RTE_INTR_MODE_MSIX_NAME " Use MSIX interrupt\n"
634 " " RTE_INTR_MODE_LEGACY_NAME " Use Legacy interrupt\n"
637 MODULE_DESCRIPTION("UIO driver for Intel IGB PCI cards");
638 MODULE_LICENSE("GPL");
639 MODULE_AUTHOR("Intel Corporation");