4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * The full GNU General Public License is included in this distribution
19 * in the file called LICENSE.GPL.
21 * Contact Information:
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27 #include <linux/device.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/uio_driver.h>
32 #include <linux/irq.h>
33 #include <linux/msi.h>
34 #include <linux/version.h>
35 #include <linux/slab.h>
37 #include <rte_pci_dev_features.h>
42 * A structure describing the private information for a uio device.
44 struct rte_uio_pci_dev {
47 enum rte_intr_mode mode;
50 static char *intr_mode;
51 static enum rte_intr_mode igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
54 show_max_vfs(struct device *dev, struct device_attribute *attr,
57 return snprintf(buf, 10, "%u\n", dev_num_vf(dev));
61 store_max_vfs(struct device *dev, struct device_attribute *attr,
62 const char *buf, size_t count)
65 unsigned long max_vfs;
66 struct pci_dev *pdev = to_pci_dev(dev);
68 if (0 != kstrtoul(buf, 0, &max_vfs))
72 pci_disable_sriov(pdev);
73 else if (0 == pci_num_vf(pdev))
74 err = pci_enable_sriov(pdev, max_vfs);
75 else /* do nothing if change max_vfs number */
78 return err ? err : count;
81 static DEVICE_ATTR(max_vfs, S_IRUGO | S_IWUSR, show_max_vfs, store_max_vfs);
83 static struct attribute *dev_attrs[] = {
84 &dev_attr_max_vfs.attr,
88 static const struct attribute_group dev_attr_grp = {
92 #ifndef HAVE_PCI_MSI_MASK_IRQ
94 * It masks the msix on/off of generating MSI-X messages.
97 igbuio_msix_mask_irq(struct msi_desc *desc, s32 state)
99 u32 mask_bits = desc->masked;
100 unsigned int offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
101 PCI_MSIX_ENTRY_VECTOR_CTRL;
104 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
106 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
108 if (mask_bits != desc->masked) {
109 writel(mask_bits, desc->mask_base + offset);
110 readl(desc->mask_base);
111 desc->masked = mask_bits;
116 * It masks the msi on/off of generating MSI messages.
119 igbuio_msi_mask_irq(struct pci_dev *pdev, struct msi_desc *desc, int32_t state)
121 u32 mask_bits = desc->masked;
122 u32 offset = desc->irq - pdev->irq;
123 u32 mask = 1 << offset;
125 if (!desc->msi_attrib.maskbit)
133 if (mask_bits != desc->masked) {
134 pci_write_config_dword(pdev, desc->mask_pos, mask_bits);
135 desc->masked = mask_bits;
140 igbuio_mask_irq(struct pci_dev *pdev, enum rte_intr_mode mode, s32 irq_state)
142 struct msi_desc *desc;
143 struct list_head *msi_list;
145 #ifdef HAVE_MSI_LIST_IN_GENERIC_DEVICE
146 msi_list = &pdev->dev.msi_list;
148 msi_list = &pdev->msi_list;
151 if (mode == RTE_INTR_MODE_MSIX) {
152 list_for_each_entry(desc, msi_list, list)
153 igbuio_msix_mask_irq(desc, irq_state);
154 } else if (mode == RTE_INTR_MODE_MSI) {
155 list_for_each_entry(desc, msi_list, list)
156 igbuio_msi_mask_irq(pdev, desc, irq_state);
162 * This is the irqcontrol callback to be registered to uio_info.
163 * It can be used to disable/enable interrupt from user space processes.
166 * pointer to uio_info.
168 * state value. 1 to enable interrupt, 0 to disable interrupt.
172 * - On failure, a negative value.
175 igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
177 struct rte_uio_pci_dev *udev = info->priv;
178 struct pci_dev *pdev = udev->pdev;
180 #ifdef HAVE_PCI_MSI_MASK_IRQ
181 struct irq_data *irq = irq_get_irq_data(udev->info.irq);
184 pci_cfg_access_lock(pdev);
186 if (udev->mode == RTE_INTR_MODE_MSIX || udev->mode == RTE_INTR_MODE_MSI) {
187 #ifdef HAVE_PCI_MSI_MASK_IRQ
189 pci_msi_unmask_irq(irq);
191 pci_msi_mask_irq(irq);
193 igbuio_mask_irq(pdev, udev->mode, irq_state);
197 if (udev->mode == RTE_INTR_MODE_LEGACY)
198 pci_intx(pdev, !!irq_state);
200 pci_cfg_access_unlock(pdev);
206 * This is interrupt handler which will check if the interrupt is for the right device.
207 * If yes, disable it here and will be enable later.
210 igbuio_pci_irqhandler(int irq, void *dev_id)
212 struct rte_uio_pci_dev *udev = (struct rte_uio_pci_dev *)dev_id;
213 struct uio_info *info = &udev->info;
215 /* Legacy mode need to mask in hardware */
216 if (udev->mode == RTE_INTR_MODE_LEGACY &&
217 !pci_check_and_mask_intx(udev->pdev))
220 uio_event_notify(info);
222 /* Message signal mode, no share IRQ and automasked */
227 igbuio_pci_enable_interrupts(struct rte_uio_pci_dev *udev)
230 #ifndef HAVE_ALLOC_IRQ_VECTORS
231 struct msix_entry msix_entry;
234 switch (igbuio_intr_mode_preferred) {
235 case RTE_INTR_MODE_MSIX:
236 /* Only 1 msi-x vector needed */
237 #ifndef HAVE_ALLOC_IRQ_VECTORS
238 msix_entry.entry = 0;
239 if (pci_enable_msix(udev->pdev, &msix_entry, 1) == 0) {
240 dev_dbg(&udev->pdev->dev, "using MSI-X");
241 udev->info.irq_flags = IRQF_NO_THREAD;
242 udev->info.irq = msix_entry.vector;
243 udev->mode = RTE_INTR_MODE_MSIX;
247 if (pci_alloc_irq_vectors(udev->pdev, 1, 1, PCI_IRQ_MSIX) == 1) {
248 dev_dbg(&udev->pdev->dev, "using MSI-X");
249 udev->info.irq_flags = IRQF_NO_THREAD;
250 udev->info.irq = pci_irq_vector(udev->pdev, 0);
251 udev->mode = RTE_INTR_MODE_MSIX;
256 /* fall back to MSI */
257 case RTE_INTR_MODE_MSI:
258 #ifndef HAVE_ALLOC_IRQ_VECTORS
259 if (pci_enable_msi(udev->pdev) == 0) {
260 dev_dbg(&udev->pdev->dev, "using MSI");
261 udev->info.irq_flags = IRQF_NO_THREAD;
262 udev->info.irq = udev->pdev->irq;
263 udev->mode = RTE_INTR_MODE_MSI;
267 if (pci_alloc_irq_vectors(udev->pdev, 1, 1, PCI_IRQ_MSI) == 1) {
268 dev_dbg(&udev->pdev->dev, "using MSI");
269 udev->info.irq_flags = IRQF_NO_THREAD;
270 udev->info.irq = pci_irq_vector(udev->pdev, 0);
271 udev->mode = RTE_INTR_MODE_MSI;
275 /* fall back to INTX */
276 case RTE_INTR_MODE_LEGACY:
277 if (pci_intx_mask_supported(udev->pdev)) {
278 dev_dbg(&udev->pdev->dev, "using INTX");
279 udev->info.irq_flags = IRQF_SHARED | IRQF_NO_THREAD;
280 udev->info.irq = udev->pdev->irq;
281 udev->mode = RTE_INTR_MODE_LEGACY;
284 dev_notice(&udev->pdev->dev, "PCI INTX mask not supported\n");
285 /* fall back to no IRQ */
286 case RTE_INTR_MODE_NONE:
287 udev->mode = RTE_INTR_MODE_NONE;
288 udev->info.irq = UIO_IRQ_NONE;
292 dev_err(&udev->pdev->dev, "invalid IRQ mode %u",
293 igbuio_intr_mode_preferred);
294 udev->info.irq = UIO_IRQ_NONE;
298 if (udev->info.irq != UIO_IRQ_NONE)
299 err = request_irq(udev->info.irq, igbuio_pci_irqhandler,
300 udev->info.irq_flags, udev->info.name,
302 dev_info(&udev->pdev->dev, "uio device registered with irq %lx\n",
309 igbuio_pci_disable_interrupts(struct rte_uio_pci_dev *udev)
311 if (udev->info.irq) {
312 free_irq(udev->info.irq, udev);
316 #ifndef HAVE_ALLOC_IRQ_VECTORS
317 if (udev->mode == RTE_INTR_MODE_MSIX)
318 pci_disable_msix(udev->pdev);
319 if (udev->mode == RTE_INTR_MODE_MSI)
320 pci_disable_msi(udev->pdev);
322 if (udev->mode == RTE_INTR_MODE_MSIX ||
323 udev->mode == RTE_INTR_MODE_MSI)
324 pci_free_irq_vectors(udev->pdev);
330 * This gets called while opening uio device file.
333 igbuio_pci_open(struct uio_info *info, struct inode *inode)
335 struct rte_uio_pci_dev *udev = info->priv;
336 struct pci_dev *dev = udev->pdev;
339 /* set bus master, which was cleared by the reset function */
342 /* enable interrupts */
343 err = igbuio_pci_enable_interrupts(udev);
345 dev_err(&dev->dev, "Enable interrupt fails\n");
351 static bool is_device_excluded_from_reset(struct pci_dev *pdev)
353 return !!pci_match_id(no_reset_pci_tbl, pdev);
357 igbuio_pci_release(struct uio_info *info, struct inode *inode)
359 struct rte_uio_pci_dev *udev = info->priv;
360 struct pci_dev *dev = udev->pdev;
362 /* disable interrupts */
363 igbuio_pci_disable_interrupts(udev);
365 /* stop the device from further DMA */
366 pci_clear_master(dev);
368 if (!is_device_excluded_from_reset(dev))
369 pci_reset_function(dev);
374 /* Remap pci resources described by bar #pci_bar in uio resource n. */
376 igbuio_pci_setup_iomem(struct pci_dev *dev, struct uio_info *info,
377 int n, int pci_bar, const char *name)
379 unsigned long addr, len;
382 if (n >= ARRAY_SIZE(info->mem))
385 addr = pci_resource_start(dev, pci_bar);
386 len = pci_resource_len(dev, pci_bar);
387 if (addr == 0 || len == 0)
389 internal_addr = ioremap(addr, len);
390 if (internal_addr == NULL)
392 info->mem[n].name = name;
393 info->mem[n].addr = addr;
394 info->mem[n].internal_addr = internal_addr;
395 info->mem[n].size = len;
396 info->mem[n].memtype = UIO_MEM_PHYS;
400 /* Get pci port io resources described by bar #pci_bar in uio resource n. */
402 igbuio_pci_setup_ioport(struct pci_dev *dev, struct uio_info *info,
403 int n, int pci_bar, const char *name)
405 unsigned long addr, len;
407 if (n >= ARRAY_SIZE(info->port))
410 addr = pci_resource_start(dev, pci_bar);
411 len = pci_resource_len(dev, pci_bar);
412 if (addr == 0 || len == 0)
415 info->port[n].name = name;
416 info->port[n].start = addr;
417 info->port[n].size = len;
418 info->port[n].porttype = UIO_PORT_X86;
423 /* Unmap previously ioremap'd resources */
425 igbuio_pci_release_iomem(struct uio_info *info)
429 for (i = 0; i < MAX_UIO_MAPS; i++) {
430 if (info->mem[i].internal_addr)
431 iounmap(info->mem[i].internal_addr);
436 igbuio_setup_bars(struct pci_dev *dev, struct uio_info *info)
438 int i, iom, iop, ret;
440 static const char *bar_names[PCI_STD_RESOURCE_END + 1] = {
452 for (i = 0; i < ARRAY_SIZE(bar_names); i++) {
453 if (pci_resource_len(dev, i) != 0 &&
454 pci_resource_start(dev, i) != 0) {
455 flags = pci_resource_flags(dev, i);
456 if (flags & IORESOURCE_MEM) {
457 ret = igbuio_pci_setup_iomem(dev, info, iom,
462 } else if (flags & IORESOURCE_IO) {
463 ret = igbuio_pci_setup_ioport(dev, info, iop,
472 return (iom != 0 || iop != 0) ? ret : -ENOENT;
475 #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)
480 igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
482 struct rte_uio_pci_dev *udev;
483 dma_addr_t map_dma_addr;
487 udev = kzalloc(sizeof(struct rte_uio_pci_dev), GFP_KERNEL);
492 * enable device: ask low-level code to enable I/O and
495 err = pci_enable_device(dev);
497 dev_err(&dev->dev, "Cannot enable PCI device\n");
501 /* enable bus mastering on the device */
504 /* remap IO memory */
505 err = igbuio_setup_bars(dev, &udev->info);
507 goto fail_release_iomem;
509 /* set 64-bit DMA mask */
510 err = pci_set_dma_mask(dev, DMA_BIT_MASK(64));
512 dev_err(&dev->dev, "Cannot set DMA mask\n");
513 goto fail_release_iomem;
516 err = pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64));
518 dev_err(&dev->dev, "Cannot set consistent DMA mask\n");
519 goto fail_release_iomem;
523 udev->info.name = "igb_uio";
524 udev->info.version = "0.1";
525 udev->info.irqcontrol = igbuio_pci_irqcontrol;
526 udev->info.open = igbuio_pci_open;
527 udev->info.release = igbuio_pci_release;
528 udev->info.priv = udev;
531 err = sysfs_create_group(&dev->dev.kobj, &dev_attr_grp);
533 goto fail_release_iomem;
535 /* register uio driver */
536 err = uio_register_device(&dev->dev, &udev->info);
538 goto fail_remove_group;
540 pci_set_drvdata(dev, udev);
543 * Doing a harmless dma mapping for attaching the device to
544 * the iommu identity mapping if kernel boots with iommu=pt.
545 * Note this is not a problem if no IOMMU at all.
547 map_addr = dma_alloc_coherent(&dev->dev, 1024, &map_dma_addr,
550 memset(map_addr, 0, 1024);
553 dev_info(&dev->dev, "dma mapping failed\n");
555 dev_info(&dev->dev, "mapping 1K dma=%#llx host=%p\n",
556 (unsigned long long)map_dma_addr, map_addr);
558 dma_free_coherent(&dev->dev, 1024, map_addr, map_dma_addr);
559 dev_info(&dev->dev, "unmapping 1K dma=%#llx host=%p\n",
560 (unsigned long long)map_dma_addr, map_addr);
566 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
568 igbuio_pci_release_iomem(&udev->info);
569 pci_disable_device(dev);
577 igbuio_pci_remove(struct pci_dev *dev)
579 struct rte_uio_pci_dev *udev = pci_get_drvdata(dev);
581 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
582 uio_unregister_device(&udev->info);
583 igbuio_pci_release_iomem(&udev->info);
584 pci_disable_device(dev);
585 pci_set_drvdata(dev, NULL);
590 igbuio_config_intr_mode(char *intr_str)
593 pr_info("Use MSIX interrupt by default\n");
597 if (!strcmp(intr_str, RTE_INTR_MODE_MSIX_NAME)) {
598 igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
599 pr_info("Use MSIX interrupt\n");
600 } else if (!strcmp(intr_str, RTE_INTR_MODE_MSI_NAME)) {
601 igbuio_intr_mode_preferred = RTE_INTR_MODE_MSI;
602 pr_info("Use MSI interrupt\n");
603 } else if (!strcmp(intr_str, RTE_INTR_MODE_LEGACY_NAME)) {
604 igbuio_intr_mode_preferred = RTE_INTR_MODE_LEGACY;
605 pr_info("Use legacy interrupt\n");
607 pr_info("Error: bad parameter - %s\n", intr_str);
614 static struct pci_driver igbuio_pci_driver = {
617 .probe = igbuio_pci_probe,
618 .remove = igbuio_pci_remove,
622 igbuio_pci_init_module(void)
626 ret = igbuio_config_intr_mode(intr_mode);
630 return pci_register_driver(&igbuio_pci_driver);
634 igbuio_pci_exit_module(void)
636 pci_unregister_driver(&igbuio_pci_driver);
639 module_init(igbuio_pci_init_module);
640 module_exit(igbuio_pci_exit_module);
642 module_param(intr_mode, charp, S_IRUGO);
643 MODULE_PARM_DESC(intr_mode,
644 "igb_uio interrupt mode (default=msix):\n"
645 " " RTE_INTR_MODE_MSIX_NAME " Use MSIX interrupt\n"
646 " " RTE_INTR_MODE_MSI_NAME " Use MSI interrupt\n"
647 " " RTE_INTR_MODE_LEGACY_NAME " Use Legacy interrupt\n"
650 MODULE_DESCRIPTION("UIO driver for Intel IGB PCI cards");
651 MODULE_LICENSE("GPL");
652 MODULE_AUTHOR("Intel Corporation");