1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "LICENSE.GPL".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
29 * 82575EB Gigabit Network Connection
30 * 82575EB Gigabit Backplane Connection
31 * 82575GB Gigabit Network Connection
32 * 82576 Gigabit Network Connection
33 * 82576 Quad Port Gigabit Mezzanine Adapter
34 * 82580 Gigabit Network Connection
35 * I350 Gigabit Network Connection
38 #include "e1000_api.h"
39 #include "e1000_i210.h"
41 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
42 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
43 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw);
44 static void e1000_release_phy_82575(struct e1000_hw *hw);
45 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
46 static void e1000_release_nvm_82575(struct e1000_hw *hw);
47 static s32 e1000_check_for_link_82575(struct e1000_hw *hw);
48 static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw);
49 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
50 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
52 static s32 e1000_init_hw_82575(struct e1000_hw *hw);
53 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
54 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
56 static s32 e1000_reset_hw_82575(struct e1000_hw *hw);
57 static s32 e1000_reset_hw_82580(struct e1000_hw *hw);
58 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,
59 u32 offset, u16 *data);
60 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,
61 u32 offset, u16 data);
62 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
64 static s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
66 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
68 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
69 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
70 static s32 e1000_get_media_type_82575(struct e1000_hw *hw);
71 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
72 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
73 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
74 u32 offset, u16 data);
75 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
76 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
77 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
78 u16 *speed, u16 *duplex);
79 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
80 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
81 static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
82 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
83 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
84 static void e1000_config_collision_dist_82575(struct e1000_hw *hw);
85 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
86 static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
87 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
88 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
89 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
90 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
91 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
92 static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
94 static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
96 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
97 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
98 static void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);
99 static void e1000_clear_vfta_i350(struct e1000_hw *hw);
101 static void e1000_i2c_start(struct e1000_hw *hw);
102 static void e1000_i2c_stop(struct e1000_hw *hw);
103 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
104 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
105 static s32 e1000_get_i2c_ack(struct e1000_hw *hw);
106 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
107 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
108 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
109 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
110 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
111 static bool e1000_get_i2c_data(u32 *i2cctl);
113 static const u16 e1000_82580_rxpbs_table[] = {
114 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
115 #define E1000_82580_RXPBS_TABLE_SIZE \
116 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
120 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
121 * @hw: pointer to the HW structure
123 * Called to determine if the I2C pins are being used for I2C or as an
124 * external MDIO interface since the two options are mutually exclusive.
126 static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
129 bool ext_mdio = false;
131 DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
133 switch (hw->mac.type) {
136 reg = E1000_READ_REG(hw, E1000_MDIC);
137 ext_mdio = !!(reg & E1000_MDIC_DEST);
144 reg = E1000_READ_REG(hw, E1000_MDICNFG);
145 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
154 * e1000_init_phy_params_82575 - Init PHY func ptrs.
155 * @hw: pointer to the HW structure
157 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
159 struct e1000_phy_info *phy = &hw->phy;
160 s32 ret_val = E1000_SUCCESS;
163 DEBUGFUNC("e1000_init_phy_params_82575");
165 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
166 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
168 if (hw->phy.media_type != e1000_media_type_copper) {
169 phy->type = e1000_phy_none;
173 phy->ops.power_up = e1000_power_up_phy_copper;
174 phy->ops.power_down = e1000_power_down_phy_copper_82575;
176 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
177 phy->reset_delay_us = 100;
179 phy->ops.acquire = e1000_acquire_phy_82575;
180 phy->ops.check_reset_block = e1000_check_reset_block_generic;
181 phy->ops.commit = e1000_phy_sw_reset_generic;
182 phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
183 phy->ops.release = e1000_release_phy_82575;
185 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
187 if (e1000_sgmii_active_82575(hw)) {
188 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
189 ctrl_ext |= E1000_CTRL_I2C_ENA;
191 phy->ops.reset = e1000_phy_hw_reset_generic;
192 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
195 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
196 e1000_reset_mdicnfg_82580(hw);
198 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
199 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
200 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
202 switch (hw->mac.type) {
206 phy->ops.read_reg = e1000_read_phy_reg_82580;
207 phy->ops.write_reg = e1000_write_phy_reg_82580;
211 phy->ops.read_reg = e1000_read_phy_reg_gs40g;
212 phy->ops.write_reg = e1000_write_phy_reg_gs40g;
215 phy->ops.read_reg = e1000_read_phy_reg_igp;
216 phy->ops.write_reg = e1000_write_phy_reg_igp;
220 /* Set phy->phy_addr and phy->id. */
221 ret_val = e1000_get_phy_id_82575(hw);
223 /* Verify phy id and set remaining function pointers */
225 case M88E1543_E_PHY_ID:
226 case I347AT4_E_PHY_ID:
227 case M88E1112_E_PHY_ID:
228 case M88E1340M_E_PHY_ID:
229 case M88E1111_I_PHY_ID:
230 phy->type = e1000_phy_m88;
231 phy->ops.check_polarity = e1000_check_polarity_m88;
232 phy->ops.get_info = e1000_get_phy_info_m88;
233 if (phy->id == I347AT4_E_PHY_ID ||
234 phy->id == M88E1112_E_PHY_ID ||
235 phy->id == M88E1340M_E_PHY_ID)
236 phy->ops.get_cable_length =
237 e1000_get_cable_length_m88_gen2;
238 else if (phy->id == M88E1543_E_PHY_ID)
239 phy->ops.get_cable_length =
240 e1000_get_cable_length_m88_gen2;
242 phy->ops.get_cable_length = e1000_get_cable_length_m88;
243 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
244 /* Check if this PHY is configured for media swap. */
245 if (phy->id == M88E1112_E_PHY_ID) {
248 ret_val = phy->ops.write_reg(hw,
249 E1000_M88E1112_PAGE_ADDR,
254 ret_val = phy->ops.read_reg(hw,
255 E1000_M88E1112_MAC_CTRL_1,
260 data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
261 E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
262 if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
263 data == E1000_M88E1112_AUTO_COPPER_BASEX)
264 hw->mac.ops.check_for_link =
265 e1000_check_for_link_media_swap;
268 case IGP03E1000_E_PHY_ID:
269 case IGP04E1000_E_PHY_ID:
270 phy->type = e1000_phy_igp_3;
271 phy->ops.check_polarity = e1000_check_polarity_igp;
272 phy->ops.get_info = e1000_get_phy_info_igp;
273 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
274 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
275 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
276 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
278 case I82580_I_PHY_ID:
280 phy->type = e1000_phy_82580;
281 phy->ops.check_polarity = e1000_check_polarity_82577;
282 phy->ops.force_speed_duplex =
283 e1000_phy_force_speed_duplex_82577;
284 phy->ops.get_cable_length = e1000_get_cable_length_82577;
285 phy->ops.get_info = e1000_get_phy_info_82577;
286 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
287 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
290 phy->type = e1000_phy_i210;
291 phy->ops.check_polarity = e1000_check_polarity_m88;
292 phy->ops.get_info = e1000_get_phy_info_m88;
293 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
294 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
295 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
296 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
299 ret_val = -E1000_ERR_PHY;
308 * e1000_init_nvm_params_82575 - Init NVM func ptrs.
309 * @hw: pointer to the HW structure
311 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
313 struct e1000_nvm_info *nvm = &hw->nvm;
314 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
317 DEBUGFUNC("e1000_init_nvm_params_82575");
319 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
320 E1000_EECD_SIZE_EX_SHIFT);
322 * Added to a constant, "size" becomes the left-shift value
323 * for setting word_size.
325 size += NVM_WORD_SIZE_BASE_SHIFT;
327 /* Just in case size is out of range, cap it to the largest
328 * EEPROM size supported
333 nvm->word_size = 1 << size;
334 if (hw->mac.type < e1000_i210) {
335 nvm->opcode_bits = 8;
338 switch (nvm->override) {
339 case e1000_nvm_override_spi_large:
341 nvm->address_bits = 16;
343 case e1000_nvm_override_spi_small:
345 nvm->address_bits = 8;
348 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
349 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
353 if (nvm->word_size == (1 << 15))
354 nvm->page_size = 128;
356 nvm->type = e1000_nvm_eeprom_spi;
358 nvm->type = e1000_nvm_flash_hw;
361 /* Function Pointers */
362 nvm->ops.acquire = e1000_acquire_nvm_82575;
363 nvm->ops.release = e1000_release_nvm_82575;
364 if (nvm->word_size < (1 << 15))
365 nvm->ops.read = e1000_read_nvm_eerd;
367 nvm->ops.read = e1000_read_nvm_spi;
369 nvm->ops.write = e1000_write_nvm_spi;
370 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
371 nvm->ops.update = e1000_update_nvm_checksum_generic;
372 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
374 /* override generic family function pointers for specific descendants */
375 switch (hw->mac.type) {
377 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
378 nvm->ops.update = e1000_update_nvm_checksum_82580;
382 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
383 nvm->ops.update = e1000_update_nvm_checksum_i350;
389 return E1000_SUCCESS;
393 * e1000_init_mac_params_82575 - Init MAC func ptrs.
394 * @hw: pointer to the HW structure
396 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
398 struct e1000_mac_info *mac = &hw->mac;
399 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
401 DEBUGFUNC("e1000_init_mac_params_82575");
403 /* Derives media type */
404 e1000_get_media_type_82575(hw);
405 /* Set mta register count */
406 mac->mta_reg_count = 128;
407 /* Set uta register count */
408 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
409 /* Set rar entry count */
410 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
411 if (mac->type == e1000_82576)
412 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
413 if (mac->type == e1000_82580)
414 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
415 if (mac->type == e1000_i350 || mac->type == e1000_i354)
416 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
418 /* Enable EEE default settings for EEE supported devices */
419 if (mac->type >= e1000_i350)
420 dev_spec->eee_disable = false;
422 /* Allow a single clear of the SW semaphore on I210 and newer */
423 if (mac->type >= e1000_i210)
424 dev_spec->clear_semaphore_once = true;
426 /* Set if part includes ASF firmware */
427 mac->asf_firmware_present = true;
429 mac->has_fwsm = true;
430 /* ARC supported; valid only if manageability features are enabled. */
431 mac->arc_subsystem_valid =
432 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
434 /* Function pointers */
436 /* bus type/speed/width */
437 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
439 if (mac->type >= e1000_82580)
440 mac->ops.reset_hw = e1000_reset_hw_82580;
442 mac->ops.reset_hw = e1000_reset_hw_82575;
443 /* hw initialization */
444 mac->ops.init_hw = e1000_init_hw_82575;
446 mac->ops.setup_link = e1000_setup_link_generic;
447 /* physical interface link setup */
448 mac->ops.setup_physical_interface =
449 (hw->phy.media_type == e1000_media_type_copper)
450 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
451 /* physical interface shutdown */
452 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
453 /* physical interface power up */
454 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
456 mac->ops.check_for_link = e1000_check_for_link_82575;
457 /* read mac address */
458 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
459 /* configure collision distance */
460 mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
461 /* multicast address update */
462 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
463 if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
465 mac->ops.write_vfta = e1000_write_vfta_i350;
467 mac->ops.clear_vfta = e1000_clear_vfta_i350;
470 mac->ops.write_vfta = e1000_write_vfta_generic;
472 mac->ops.clear_vfta = e1000_clear_vfta_generic;
474 if (hw->mac.type >= e1000_82580)
475 mac->ops.validate_mdi_setting =
476 e1000_validate_mdi_setting_crossover_generic;
478 mac->ops.id_led_init = e1000_id_led_init_generic;
480 mac->ops.blink_led = e1000_blink_led_generic;
482 mac->ops.setup_led = e1000_setup_led_generic;
484 mac->ops.cleanup_led = e1000_cleanup_led_generic;
485 /* turn on/off LED */
486 mac->ops.led_on = e1000_led_on_generic;
487 mac->ops.led_off = e1000_led_off_generic;
488 /* clear hardware counters */
489 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
491 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
492 /* get thermal sensor data */
493 mac->ops.get_thermal_sensor_data =
494 e1000_get_thermal_sensor_data_generic;
495 mac->ops.init_thermal_sensor_thresh =
496 e1000_init_thermal_sensor_thresh_generic;
497 /* acquire SW_FW sync */
498 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
499 mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
500 if (mac->type >= e1000_i210) {
501 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
502 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
505 /* set lan id for port to determine which phy lock to use */
506 hw->mac.ops.set_lan_id(hw);
508 return E1000_SUCCESS;
512 * e1000_init_function_pointers_82575 - Init func ptrs.
513 * @hw: pointer to the HW structure
515 * Called to initialize all function pointers and parameters.
517 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
519 DEBUGFUNC("e1000_init_function_pointers_82575");
521 hw->mac.ops.init_params = e1000_init_mac_params_82575;
522 hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
523 hw->phy.ops.init_params = e1000_init_phy_params_82575;
524 hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
528 * e1000_acquire_phy_82575 - Acquire rights to access PHY
529 * @hw: pointer to the HW structure
531 * Acquire access rights to the correct PHY.
533 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
535 u16 mask = E1000_SWFW_PHY0_SM;
537 DEBUGFUNC("e1000_acquire_phy_82575");
539 if (hw->bus.func == E1000_FUNC_1)
540 mask = E1000_SWFW_PHY1_SM;
541 else if (hw->bus.func == E1000_FUNC_2)
542 mask = E1000_SWFW_PHY2_SM;
543 else if (hw->bus.func == E1000_FUNC_3)
544 mask = E1000_SWFW_PHY3_SM;
546 return hw->mac.ops.acquire_swfw_sync(hw, mask);
550 * e1000_release_phy_82575 - Release rights to access PHY
551 * @hw: pointer to the HW structure
553 * A wrapper to release access rights to the correct PHY.
555 static void e1000_release_phy_82575(struct e1000_hw *hw)
557 u16 mask = E1000_SWFW_PHY0_SM;
559 DEBUGFUNC("e1000_release_phy_82575");
561 if (hw->bus.func == E1000_FUNC_1)
562 mask = E1000_SWFW_PHY1_SM;
563 else if (hw->bus.func == E1000_FUNC_2)
564 mask = E1000_SWFW_PHY2_SM;
565 else if (hw->bus.func == E1000_FUNC_3)
566 mask = E1000_SWFW_PHY3_SM;
568 hw->mac.ops.release_swfw_sync(hw, mask);
572 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
573 * @hw: pointer to the HW structure
574 * @offset: register offset to be read
575 * @data: pointer to the read data
577 * Reads the PHY register at offset using the serial gigabit media independent
578 * interface and stores the retrieved information in data.
580 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
583 s32 ret_val = -E1000_ERR_PARAM;
585 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
587 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
588 DEBUGOUT1("PHY Address %u is out of range\n", offset);
592 ret_val = hw->phy.ops.acquire(hw);
596 ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
598 hw->phy.ops.release(hw);
605 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
606 * @hw: pointer to the HW structure
607 * @offset: register offset to write to
608 * @data: data to write at register offset
610 * Writes the data to PHY register at the offset using the serial gigabit
611 * media independent interface.
613 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
616 s32 ret_val = -E1000_ERR_PARAM;
618 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
620 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
621 DEBUGOUT1("PHY Address %d is out of range\n", offset);
625 ret_val = hw->phy.ops.acquire(hw);
629 ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
631 hw->phy.ops.release(hw);
638 * e1000_get_phy_id_82575 - Retrieve PHY addr and id
639 * @hw: pointer to the HW structure
641 * Retrieves the PHY address and ID for both PHY's which do and do not use
644 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
646 struct e1000_phy_info *phy = &hw->phy;
647 s32 ret_val = E1000_SUCCESS;
652 DEBUGFUNC("e1000_get_phy_id_82575");
654 /* i354 devices can have a PHY that needs an extra read for id */
655 if (hw->mac.type == e1000_i354)
656 e1000_get_phy_id(hw);
660 * For SGMII PHYs, we try the list of possible addresses until
661 * we find one that works. For non-SGMII PHYs
662 * (e.g. integrated copper PHYs), an address of 1 should
663 * work. The result of this function should mean phy->phy_addr
664 * and phy->id are set correctly.
666 if (!e1000_sgmii_active_82575(hw)) {
668 ret_val = e1000_get_phy_id(hw);
672 if (e1000_sgmii_uses_mdio_82575(hw)) {
673 switch (hw->mac.type) {
676 mdic = E1000_READ_REG(hw, E1000_MDIC);
677 mdic &= E1000_MDIC_PHY_MASK;
678 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
685 mdic = E1000_READ_REG(hw, E1000_MDICNFG);
686 mdic &= E1000_MDICNFG_PHY_MASK;
687 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
690 ret_val = -E1000_ERR_PHY;
694 ret_val = e1000_get_phy_id(hw);
698 /* Power on sgmii phy if it is disabled */
699 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
700 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
701 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
702 E1000_WRITE_FLUSH(hw);
706 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
707 * Therefore, we need to test 1-7
709 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
710 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
711 if (ret_val == E1000_SUCCESS) {
712 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
715 * At the time of this writing, The M88 part is
716 * the only supported SGMII PHY product.
718 if (phy_id == M88_VENDOR)
721 DEBUGOUT1("PHY address %u was unreadable\n",
726 /* A valid PHY type couldn't be found. */
727 if (phy->addr == 8) {
729 ret_val = -E1000_ERR_PHY;
731 ret_val = e1000_get_phy_id(hw);
734 /* restore previous sfp cage power state */
735 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
742 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
743 * @hw: pointer to the HW structure
745 * Resets the PHY using the serial gigabit media independent interface.
747 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
749 s32 ret_val = E1000_SUCCESS;
751 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
754 * This isn't a true "hard" reset, but is the only reset
755 * available to us at this time.
758 DEBUGOUT("Soft resetting SGMII attached PHY...\n");
760 if (!(hw->phy.ops.write_reg))
764 * SFP documentation requires the following to configure the SPF module
765 * to work on SGMII. No further documentation is given.
767 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
771 ret_val = hw->phy.ops.commit(hw);
778 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
779 * @hw: pointer to the HW structure
780 * @active: true to enable LPLU, false to disable
782 * Sets the LPLU D0 state according to the active flag. When
783 * activating LPLU this function also disables smart speed
784 * and vice versa. LPLU will not be activated unless the
785 * device autonegotiation advertisement meets standards of
786 * either 10 or 10/100 or 10/100/1000 at all duplexes.
787 * This is a function pointer entry point only called by
788 * PHY setup routines.
790 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
792 struct e1000_phy_info *phy = &hw->phy;
793 s32 ret_val = E1000_SUCCESS;
796 DEBUGFUNC("e1000_set_d0_lplu_state_82575");
798 if (!(hw->phy.ops.read_reg))
801 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
806 data |= IGP02E1000_PM_D0_LPLU;
807 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
812 /* When LPLU is enabled, we should disable SmartSpeed */
813 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
815 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
816 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
821 data &= ~IGP02E1000_PM_D0_LPLU;
822 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
825 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
826 * during Dx states where the power conservation is most
827 * important. During driver activity we should enable
828 * SmartSpeed, so performance is maintained.
830 if (phy->smart_speed == e1000_smart_speed_on) {
831 ret_val = phy->ops.read_reg(hw,
832 IGP01E1000_PHY_PORT_CONFIG,
837 data |= IGP01E1000_PSCFR_SMART_SPEED;
838 ret_val = phy->ops.write_reg(hw,
839 IGP01E1000_PHY_PORT_CONFIG,
843 } else if (phy->smart_speed == e1000_smart_speed_off) {
844 ret_val = phy->ops.read_reg(hw,
845 IGP01E1000_PHY_PORT_CONFIG,
850 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
851 ret_val = phy->ops.write_reg(hw,
852 IGP01E1000_PHY_PORT_CONFIG,
864 * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
865 * @hw: pointer to the HW structure
866 * @active: true to enable LPLU, false to disable
868 * Sets the LPLU D0 state according to the active flag. When
869 * activating LPLU this function also disables smart speed
870 * and vice versa. LPLU will not be activated unless the
871 * device autonegotiation advertisement meets standards of
872 * either 10 or 10/100 or 10/100/1000 at all duplexes.
873 * This is a function pointer entry point only called by
874 * PHY setup routines.
876 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
878 struct e1000_phy_info *phy = &hw->phy;
879 s32 ret_val = E1000_SUCCESS;
882 DEBUGFUNC("e1000_set_d0_lplu_state_82580");
884 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
887 data |= E1000_82580_PM_D0_LPLU;
889 /* When LPLU is enabled, we should disable SmartSpeed */
890 data &= ~E1000_82580_PM_SPD;
892 data &= ~E1000_82580_PM_D0_LPLU;
895 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
896 * during Dx states where the power conservation is most
897 * important. During driver activity we should enable
898 * SmartSpeed, so performance is maintained.
900 if (phy->smart_speed == e1000_smart_speed_on)
901 data |= E1000_82580_PM_SPD;
902 else if (phy->smart_speed == e1000_smart_speed_off)
903 data &= ~E1000_82580_PM_SPD;
906 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
911 * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
912 * @hw: pointer to the HW structure
913 * @active: boolean used to enable/disable lplu
915 * Success returns 0, Failure returns 1
917 * The low power link up (lplu) state is set to the power management level D3
918 * and SmartSpeed is disabled when active is true, else clear lplu for D3
919 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
920 * is used during Dx states where the power conservation is most important.
921 * During driver activity, SmartSpeed should be enabled so performance is
924 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
926 struct e1000_phy_info *phy = &hw->phy;
927 s32 ret_val = E1000_SUCCESS;
930 DEBUGFUNC("e1000_set_d3_lplu_state_82580");
932 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
935 data &= ~E1000_82580_PM_D3_LPLU;
937 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
938 * during Dx states where the power conservation is most
939 * important. During driver activity we should enable
940 * SmartSpeed, so performance is maintained.
942 if (phy->smart_speed == e1000_smart_speed_on)
943 data |= E1000_82580_PM_SPD;
944 else if (phy->smart_speed == e1000_smart_speed_off)
945 data &= ~E1000_82580_PM_SPD;
946 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
947 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
948 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
949 data |= E1000_82580_PM_D3_LPLU;
950 /* When LPLU is enabled, we should disable SmartSpeed */
951 data &= ~E1000_82580_PM_SPD;
954 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
959 * e1000_acquire_nvm_82575 - Request for access to EEPROM
960 * @hw: pointer to the HW structure
962 * Acquire the necessary semaphores for exclusive access to the EEPROM.
963 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
964 * Return successful if access grant bit set, else clear the request for
965 * EEPROM access and return -E1000_ERR_NVM (-1).
967 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
971 DEBUGFUNC("e1000_acquire_nvm_82575");
973 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
978 * Check if there is some access
979 * error this access may hook on
981 if (hw->mac.type == e1000_i350) {
982 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
983 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
984 E1000_EECD_TIMEOUT)) {
985 /* Clear all access error flags */
986 E1000_WRITE_REG(hw, E1000_EECD, eecd |
987 E1000_EECD_ERROR_CLR);
988 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
991 if (hw->mac.type == e1000_82580) {
992 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
993 if (eecd & E1000_EECD_BLOCKED) {
994 /* Clear access error flag */
995 E1000_WRITE_REG(hw, E1000_EECD, eecd |
997 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1002 ret_val = e1000_acquire_nvm_generic(hw);
1004 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1011 * e1000_release_nvm_82575 - Release exclusive access to EEPROM
1012 * @hw: pointer to the HW structure
1014 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
1015 * then release the semaphores acquired.
1017 static void e1000_release_nvm_82575(struct e1000_hw *hw)
1019 DEBUGFUNC("e1000_release_nvm_82575");
1021 e1000_release_nvm_generic(hw);
1023 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1027 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1028 * @hw: pointer to the HW structure
1029 * @mask: specifies which semaphore to acquire
1031 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
1032 * will also specify which port we're acquiring the lock for.
1034 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1038 u32 fwmask = mask << 16;
1039 s32 ret_val = E1000_SUCCESS;
1040 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
1042 DEBUGFUNC("e1000_acquire_swfw_sync_82575");
1044 while (i < timeout) {
1045 if (e1000_get_hw_semaphore_generic(hw)) {
1046 ret_val = -E1000_ERR_SWFW_SYNC;
1050 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1051 if (!(swfw_sync & (fwmask | swmask)))
1055 * Firmware currently using resource (fwmask)
1056 * or other software thread using resource (swmask)
1058 e1000_put_hw_semaphore_generic(hw);
1064 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1065 ret_val = -E1000_ERR_SWFW_SYNC;
1069 swfw_sync |= swmask;
1070 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1072 e1000_put_hw_semaphore_generic(hw);
1079 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore
1080 * @hw: pointer to the HW structure
1081 * @mask: specifies which semaphore to acquire
1083 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1084 * will also specify which port we're releasing the lock for.
1086 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1090 DEBUGFUNC("e1000_release_swfw_sync_82575");
1092 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1095 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1097 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1099 e1000_put_hw_semaphore_generic(hw);
1103 * e1000_get_cfg_done_82575 - Read config done bit
1104 * @hw: pointer to the HW structure
1106 * Read the management control register for the config done bit for
1107 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1108 * to read the config done bit, so an error is *ONLY* logged and returns
1109 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
1110 * would not be able to be reset or change link.
1112 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1114 s32 timeout = PHY_CFG_TIMEOUT;
1115 s32 ret_val = E1000_SUCCESS;
1116 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1118 DEBUGFUNC("e1000_get_cfg_done_82575");
1120 if (hw->bus.func == E1000_FUNC_1)
1121 mask = E1000_NVM_CFG_DONE_PORT_1;
1122 else if (hw->bus.func == E1000_FUNC_2)
1123 mask = E1000_NVM_CFG_DONE_PORT_2;
1124 else if (hw->bus.func == E1000_FUNC_3)
1125 mask = E1000_NVM_CFG_DONE_PORT_3;
1127 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1133 DEBUGOUT("MNG configuration cycle has not completed.\n");
1135 /* If EEPROM is not marked present, init the PHY manually */
1136 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1137 (hw->phy.type == e1000_phy_igp_3))
1138 e1000_phy_init_script_igp3(hw);
1144 * e1000_get_link_up_info_82575 - Get link speed/duplex info
1145 * @hw: pointer to the HW structure
1146 * @speed: stores the current speed
1147 * @duplex: stores the current duplex
1149 * This is a wrapper function, if using the serial gigabit media independent
1150 * interface, use PCS to retrieve the link speed and duplex information.
1151 * Otherwise, use the generic function to get the link speed and duplex info.
1153 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1158 DEBUGFUNC("e1000_get_link_up_info_82575");
1160 if (hw->phy.media_type != e1000_media_type_copper)
1161 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1164 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1171 * e1000_check_for_link_82575 - Check for link
1172 * @hw: pointer to the HW structure
1174 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1175 * use the generic interface for determining link.
1177 static s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1182 DEBUGFUNC("e1000_check_for_link_82575");
1184 if (hw->phy.media_type != e1000_media_type_copper) {
1185 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1188 * Use this flag to determine if link needs to be checked or
1189 * not. If we have link clear the flag so that we do not
1190 * continue to check for link.
1192 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1195 * Configure Flow Control now that Auto-Neg has completed.
1196 * First, we need to restore the desired flow control
1197 * settings because we may have had to re-autoneg with a
1198 * different link partner.
1200 ret_val = e1000_config_fc_after_link_up_generic(hw);
1202 DEBUGOUT("Error configuring flow control\n");
1204 ret_val = e1000_check_for_copper_link_generic(hw);
1211 * e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1212 * @hw: pointer to the HW structure
1214 * Poll the M88E1112 interfaces to see which interface achieved link.
1216 static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1218 struct e1000_phy_info *phy = &hw->phy;
1223 DEBUGFUNC("e1000_check_for_link_media_swap");
1225 /* Check the copper medium. */
1226 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1230 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1234 if (data & E1000_M88E1112_STATUS_LINK)
1235 port = E1000_MEDIA_PORT_COPPER;
1237 /* Check the other medium. */
1238 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1242 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1246 if (data & E1000_M88E1112_STATUS_LINK)
1247 port = E1000_MEDIA_PORT_OTHER;
1249 /* Determine if a swap needs to happen. */
1250 if (port && (hw->dev_spec._82575.media_port != port)) {
1251 hw->dev_spec._82575.media_port = port;
1252 hw->dev_spec._82575.media_changed = true;
1254 ret_val = e1000_check_for_link_82575(hw);
1257 return E1000_SUCCESS;
1261 * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1262 * @hw: pointer to the HW structure
1264 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1268 DEBUGFUNC("e1000_power_up_serdes_link_82575");
1270 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1271 !e1000_sgmii_active_82575(hw))
1274 /* Enable PCS to turn on link */
1275 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1276 reg |= E1000_PCS_CFG_PCS_EN;
1277 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1279 /* Power up the laser */
1280 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1281 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1282 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1284 /* flush the write to verify completion */
1285 E1000_WRITE_FLUSH(hw);
1290 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1291 * @hw: pointer to the HW structure
1292 * @speed: stores the current speed
1293 * @duplex: stores the current duplex
1295 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1296 * duplex, then store the values in the pointers provided.
1298 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1299 u16 *speed, u16 *duplex)
1301 struct e1000_mac_info *mac = &hw->mac;
1305 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1308 * Read the PCS Status register for link state. For non-copper mode,
1309 * the status register is not accurate. The PCS status register is
1312 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1315 * The link up bit determines when link is up on autoneg.
1317 if (pcs & E1000_PCS_LSTS_LINK_OK) {
1318 mac->serdes_has_link = true;
1320 /* Detect and store PCS speed */
1321 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1322 *speed = SPEED_1000;
1323 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1328 /* Detect and store PCS duplex */
1329 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1330 *duplex = FULL_DUPLEX;
1332 *duplex = HALF_DUPLEX;
1334 /* Check if it is an I354 2.5Gb backplane connection. */
1335 if (mac->type == e1000_i354) {
1336 status = E1000_READ_REG(hw, E1000_STATUS);
1337 if ((status & E1000_STATUS_2P5_SKU) &&
1338 !(status & E1000_STATUS_2P5_SKU_OVER)) {
1339 *speed = SPEED_2500;
1340 *duplex = FULL_DUPLEX;
1341 DEBUGOUT("2500 Mbs, ");
1342 DEBUGOUT("Full Duplex\n");
1347 mac->serdes_has_link = false;
1352 return E1000_SUCCESS;
1356 * e1000_shutdown_serdes_link_82575 - Remove link during power down
1357 * @hw: pointer to the HW structure
1359 * In the case of serdes shut down sfp and PCS on driver unload
1360 * when management pass through is not enabled.
1362 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1366 DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1368 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1369 !e1000_sgmii_active_82575(hw))
1372 if (!e1000_enable_mng_pass_thru(hw)) {
1373 /* Disable PCS to turn off link */
1374 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1375 reg &= ~E1000_PCS_CFG_PCS_EN;
1376 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1378 /* shutdown the laser */
1379 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1380 reg |= E1000_CTRL_EXT_SDP3_DATA;
1381 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1383 /* flush the write to verify completion */
1384 E1000_WRITE_FLUSH(hw);
1392 * e1000_reset_hw_82575 - Reset hardware
1393 * @hw: pointer to the HW structure
1395 * This resets the hardware into a known state.
1397 static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1402 DEBUGFUNC("e1000_reset_hw_82575");
1405 * Prevent the PCI-E bus from sticking if there is no TLP connection
1406 * on the last TLP read/write transaction when MAC is reset.
1408 ret_val = e1000_disable_pcie_master_generic(hw);
1410 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1412 /* set the completion timeout for interface */
1413 ret_val = e1000_set_pcie_completion_timeout(hw);
1415 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1417 DEBUGOUT("Masking off all interrupts\n");
1418 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1420 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1421 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1422 E1000_WRITE_FLUSH(hw);
1426 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1428 DEBUGOUT("Issuing a global reset to MAC\n");
1429 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1431 ret_val = e1000_get_auto_rd_done_generic(hw);
1434 * When auto config read does not complete, do not
1435 * return with an error. This can happen in situations
1436 * where there is no eeprom and prevents getting link.
1438 DEBUGOUT("Auto Read Done did not complete\n");
1441 /* If EEPROM is not present, run manual init scripts */
1442 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1443 e1000_reset_init_script_82575(hw);
1445 /* Clear any pending interrupt events. */
1446 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1447 E1000_READ_REG(hw, E1000_ICR);
1449 /* Install any alternate MAC address into RAR0 */
1450 ret_val = e1000_check_alt_mac_addr_generic(hw);
1456 * e1000_init_hw_82575 - Initialize hardware
1457 * @hw: pointer to the HW structure
1459 * This inits the hardware readying it for operation.
1461 static s32 e1000_init_hw_82575(struct e1000_hw *hw)
1463 struct e1000_mac_info *mac = &hw->mac;
1465 u16 i, rar_count = mac->rar_entry_count;
1467 DEBUGFUNC("e1000_init_hw_82575");
1469 /* Initialize identification LED */
1470 ret_val = mac->ops.id_led_init(hw);
1472 DEBUGOUT("Error initializing identification LED\n");
1473 /* This is not fatal and we should not stop init due to this */
1476 /* Disabling VLAN filtering */
1477 DEBUGOUT("Initializing the IEEE VLAN\n");
1478 mac->ops.clear_vfta(hw);
1480 /* Setup the receive address */
1481 e1000_init_rx_addrs_generic(hw, rar_count);
1483 /* Zero out the Multicast HASH table */
1484 DEBUGOUT("Zeroing the MTA\n");
1485 for (i = 0; i < mac->mta_reg_count; i++)
1486 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1488 /* Zero out the Unicast HASH table */
1489 DEBUGOUT("Zeroing the UTA\n");
1490 for (i = 0; i < mac->uta_reg_count; i++)
1491 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1493 /* Setup link and flow control */
1494 ret_val = mac->ops.setup_link(hw);
1496 /* Set the default MTU size */
1497 hw->dev_spec._82575.mtu = 1500;
1500 * Clear all of the statistics registers (clear on read). It is
1501 * important that we do this after we have tried to establish link
1502 * because the symbol error count will increment wildly if there
1505 e1000_clear_hw_cntrs_82575(hw);
1511 * e1000_setup_copper_link_82575 - Configure copper link settings
1512 * @hw: pointer to the HW structure
1514 * Configures the link for auto-neg or forced speed and duplex. Then we check
1515 * for link, once link is established calls to configure collision distance
1516 * and flow control are called.
1518 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1524 DEBUGFUNC("e1000_setup_copper_link_82575");
1526 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1527 ctrl |= E1000_CTRL_SLU;
1528 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1529 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1531 /* Clear Go Link Disconnect bit on supported devices */
1532 switch (hw->mac.type) {
1537 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1538 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1539 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1545 ret_val = e1000_setup_serdes_link_82575(hw);
1549 if (e1000_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1550 /* allow time for SFP cage time to power up phy */
1553 ret_val = hw->phy.ops.reset(hw);
1555 DEBUGOUT("Error resetting the PHY.\n");
1559 switch (hw->phy.type) {
1560 case e1000_phy_i210:
1562 switch (hw->phy.id) {
1563 case I347AT4_E_PHY_ID:
1564 case M88E1112_E_PHY_ID:
1565 case M88E1340M_E_PHY_ID:
1566 case M88E1543_E_PHY_ID:
1568 ret_val = e1000_copper_link_setup_m88_gen2(hw);
1571 ret_val = e1000_copper_link_setup_m88(hw);
1575 case e1000_phy_igp_3:
1576 ret_val = e1000_copper_link_setup_igp(hw);
1578 case e1000_phy_82580:
1579 ret_val = e1000_copper_link_setup_82577(hw);
1582 ret_val = -E1000_ERR_PHY;
1589 ret_val = e1000_setup_copper_link_generic(hw);
1595 * e1000_setup_serdes_link_82575 - Setup link for serdes
1596 * @hw: pointer to the HW structure
1598 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1599 * used on copper connections where the serialized gigabit media independent
1600 * interface (sgmii), or serdes fiber is being used. Configures the link
1601 * for auto-negotiation or forces speed/duplex.
1603 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1605 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1607 s32 ret_val = E1000_SUCCESS;
1610 DEBUGFUNC("e1000_setup_serdes_link_82575");
1612 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1613 !e1000_sgmii_active_82575(hw))
1617 * On the 82575, SerDes loopback mode persists until it is
1618 * explicitly turned off or a power cycle is performed. A read to
1619 * the register does not indicate its status. Therefore, we ensure
1620 * loopback mode is disabled during initialization.
1622 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1624 /* power on the sfp cage if present */
1625 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1626 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1627 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1629 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1630 ctrl_reg |= E1000_CTRL_SLU;
1632 /* set both sw defined pins on 82575/82576*/
1633 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1634 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1636 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1638 /* default pcs_autoneg to the same setting as mac autoneg */
1639 pcs_autoneg = hw->mac.autoneg;
1641 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1642 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1643 /* sgmii mode lets the phy handle forcing speed/duplex */
1645 /* autoneg time out should be disabled for SGMII mode */
1646 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1648 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1649 /* disable PCS autoneg and support parallel detect only */
1650 pcs_autoneg = false;
1651 /* fall through to default case */
1653 if (hw->mac.type == e1000_82575 ||
1654 hw->mac.type == e1000_82576) {
1655 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1657 DEBUGOUT("NVM Read Error\n");
1661 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1662 pcs_autoneg = false;
1666 * non-SGMII modes only supports a speed of 1000/Full for the
1667 * link so it is best to just force the MAC and let the pcs
1668 * link either autoneg or be forced to 1000/Full
1670 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1671 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1673 /* set speed of 1000/Full if speed/duplex is forced */
1674 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1678 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1681 * New SerDes mode allows for forcing speed or autonegotiating speed
1682 * at 1gb. Autoneg should be default set by most drivers. This is the
1683 * mode that will be compatible with older link partners and switches.
1684 * However, both are supported by the hardware and some drivers/tools.
1686 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1687 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1690 /* Set PCS register for autoneg */
1691 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1692 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1694 /* Disable force flow control for autoneg */
1695 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1697 /* Configure flow control advertisement for autoneg */
1698 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1699 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1701 switch (hw->fc.requested_mode) {
1703 case e1000_fc_rx_pause:
1704 anadv_reg |= E1000_TXCW_ASM_DIR;
1705 anadv_reg |= E1000_TXCW_PAUSE;
1707 case e1000_fc_tx_pause:
1708 anadv_reg |= E1000_TXCW_ASM_DIR;
1714 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1716 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1718 /* Set PCS register for forced link */
1719 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1721 /* Force flow control for forced link */
1722 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1724 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1727 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1729 if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1730 e1000_force_mac_fc_generic(hw);
1736 * e1000_get_media_type_82575 - derives current media type.
1737 * @hw: pointer to the HW structure
1739 * The media type is chosen reflecting few settings.
1740 * The following are taken into account:
1741 * - link mode set in the current port Init Control Word #3
1742 * - current link mode settings in CSR register
1743 * - MDIO vs. I2C PHY control interface chosen
1744 * - SFP module media type
1746 static s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1748 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1749 s32 ret_val = E1000_SUCCESS;
1753 /* Set internal phy as default */
1754 dev_spec->sgmii_active = false;
1755 dev_spec->module_plugged = false;
1757 /* Get CSR setting */
1758 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1760 /* extract link mode setting */
1761 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1763 switch (link_mode) {
1764 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1765 hw->phy.media_type = e1000_media_type_internal_serdes;
1767 case E1000_CTRL_EXT_LINK_MODE_GMII:
1768 hw->phy.media_type = e1000_media_type_copper;
1770 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1771 /* Get phy control interface type set (MDIO vs. I2C)*/
1772 if (e1000_sgmii_uses_mdio_82575(hw)) {
1773 hw->phy.media_type = e1000_media_type_copper;
1774 dev_spec->sgmii_active = true;
1777 /* fall through for I2C based SGMII */
1778 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1779 /* read media type from SFP EEPROM */
1780 ret_val = e1000_set_sfp_media_type_82575(hw);
1781 if ((ret_val != E1000_SUCCESS) ||
1782 (hw->phy.media_type == e1000_media_type_unknown)) {
1784 * If media type was not identified then return media
1785 * type defined by the CTRL_EXT settings.
1787 hw->phy.media_type = e1000_media_type_internal_serdes;
1789 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1790 hw->phy.media_type = e1000_media_type_copper;
1791 dev_spec->sgmii_active = true;
1797 /* do not change link mode for 100BaseFX */
1798 if (dev_spec->eth_flags.e100_base_fx)
1801 /* change current link mode setting */
1802 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1804 if (hw->phy.media_type == e1000_media_type_copper)
1805 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1807 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1809 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1818 * e1000_set_sfp_media_type_82575 - derives SFP module media type.
1819 * @hw: pointer to the HW structure
1821 * The media type is chosen based on SFP module.
1822 * compatibility flags retrieved from SFP ID EEPROM.
1824 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1826 s32 ret_val = E1000_ERR_CONFIG;
1828 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1829 struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1830 u8 tranceiver_type = 0;
1833 /* Turn I2C interface ON and power on sfp cage */
1834 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1835 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1836 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1838 E1000_WRITE_FLUSH(hw);
1840 /* Read SFP module data */
1842 ret_val = e1000_read_sfp_data_byte(hw,
1843 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1845 if (ret_val == E1000_SUCCESS)
1850 if (ret_val != E1000_SUCCESS)
1853 ret_val = e1000_read_sfp_data_byte(hw,
1854 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1856 if (ret_val != E1000_SUCCESS)
1859 /* Check if there is some SFP module plugged and powered */
1860 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1861 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1862 dev_spec->module_plugged = true;
1863 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1864 hw->phy.media_type = e1000_media_type_internal_serdes;
1865 } else if (eth_flags->e100_base_fx) {
1866 dev_spec->sgmii_active = true;
1867 hw->phy.media_type = e1000_media_type_internal_serdes;
1868 } else if (eth_flags->e1000_base_t) {
1869 dev_spec->sgmii_active = true;
1870 hw->phy.media_type = e1000_media_type_copper;
1872 hw->phy.media_type = e1000_media_type_unknown;
1873 DEBUGOUT("PHY module has not been recognized\n");
1877 hw->phy.media_type = e1000_media_type_unknown;
1879 ret_val = E1000_SUCCESS;
1881 /* Restore I2C interface setting */
1882 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1887 * e1000_valid_led_default_82575 - Verify a valid default LED config
1888 * @hw: pointer to the HW structure
1889 * @data: pointer to the NVM (EEPROM)
1891 * Read the EEPROM for the current default LED configuration. If the
1892 * LED configuration is not valid, set to a valid LED configuration.
1894 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1898 DEBUGFUNC("e1000_valid_led_default_82575");
1900 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1902 DEBUGOUT("NVM Read Error\n");
1906 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1907 switch (hw->phy.media_type) {
1908 case e1000_media_type_internal_serdes:
1909 *data = ID_LED_DEFAULT_82575_SERDES;
1911 case e1000_media_type_copper:
1913 *data = ID_LED_DEFAULT;
1922 * e1000_sgmii_active_82575 - Return sgmii state
1923 * @hw: pointer to the HW structure
1925 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1926 * which can be enabled for use in the embedded applications. Simply
1927 * return the current state of the sgmii interface.
1929 static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1931 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1932 return dev_spec->sgmii_active;
1936 * e1000_reset_init_script_82575 - Inits HW defaults after reset
1937 * @hw: pointer to the HW structure
1939 * Inits recommended HW defaults after a reset when there is no EEPROM
1940 * detected. This is only for the 82575.
1942 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1944 DEBUGFUNC("e1000_reset_init_script_82575");
1946 if (hw->mac.type == e1000_82575) {
1947 DEBUGOUT("Running reset init script for 82575\n");
1948 /* SerDes configuration via SERDESCTRL */
1949 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1950 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1951 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1952 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1954 /* CCM configuration via CCMCTL register */
1955 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1956 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1958 /* PCIe lanes configuration */
1959 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1960 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1961 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1962 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1964 /* PCIe PLL Configuration */
1965 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1966 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1967 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1970 return E1000_SUCCESS;
1974 * e1000_read_mac_addr_82575 - Read device MAC address
1975 * @hw: pointer to the HW structure
1977 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1979 s32 ret_val = E1000_SUCCESS;
1981 DEBUGFUNC("e1000_read_mac_addr_82575");
1984 * If there's an alternate MAC address place it in RAR0
1985 * so that it will override the Si installed default perm
1988 ret_val = e1000_check_alt_mac_addr_generic(hw);
1992 ret_val = e1000_read_mac_addr_generic(hw);
1999 * e1000_config_collision_dist_82575 - Configure collision distance
2000 * @hw: pointer to the HW structure
2002 * Configures the collision distance to the default value and is used
2003 * during link setup.
2005 static void e1000_config_collision_dist_82575(struct e1000_hw *hw)
2009 DEBUGFUNC("e1000_config_collision_dist_82575");
2011 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
2013 tctl_ext &= ~E1000_TCTL_EXT_COLD;
2014 tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
2016 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
2017 E1000_WRITE_FLUSH(hw);
2021 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
2022 * @hw: pointer to the HW structure
2024 * In the case of a PHY power down to save power, or to turn off link during a
2025 * driver unload, or wake on lan is not enabled, remove the link.
2027 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
2029 struct e1000_phy_info *phy = &hw->phy;
2031 if (!(phy->ops.check_reset_block))
2034 /* If the management interface is not enabled, then power down */
2035 if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
2036 e1000_power_down_phy_copper(hw);
2042 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
2043 * @hw: pointer to the HW structure
2045 * Clears the hardware counters by reading the counter registers.
2047 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
2049 DEBUGFUNC("e1000_clear_hw_cntrs_82575");
2051 e1000_clear_hw_cntrs_base_generic(hw);
2053 E1000_READ_REG(hw, E1000_PRC64);
2054 E1000_READ_REG(hw, E1000_PRC127);
2055 E1000_READ_REG(hw, E1000_PRC255);
2056 E1000_READ_REG(hw, E1000_PRC511);
2057 E1000_READ_REG(hw, E1000_PRC1023);
2058 E1000_READ_REG(hw, E1000_PRC1522);
2059 E1000_READ_REG(hw, E1000_PTC64);
2060 E1000_READ_REG(hw, E1000_PTC127);
2061 E1000_READ_REG(hw, E1000_PTC255);
2062 E1000_READ_REG(hw, E1000_PTC511);
2063 E1000_READ_REG(hw, E1000_PTC1023);
2064 E1000_READ_REG(hw, E1000_PTC1522);
2066 E1000_READ_REG(hw, E1000_ALGNERRC);
2067 E1000_READ_REG(hw, E1000_RXERRC);
2068 E1000_READ_REG(hw, E1000_TNCRS);
2069 E1000_READ_REG(hw, E1000_CEXTERR);
2070 E1000_READ_REG(hw, E1000_TSCTC);
2071 E1000_READ_REG(hw, E1000_TSCTFC);
2073 E1000_READ_REG(hw, E1000_MGTPRC);
2074 E1000_READ_REG(hw, E1000_MGTPDC);
2075 E1000_READ_REG(hw, E1000_MGTPTC);
2077 E1000_READ_REG(hw, E1000_IAC);
2078 E1000_READ_REG(hw, E1000_ICRXOC);
2080 E1000_READ_REG(hw, E1000_ICRXPTC);
2081 E1000_READ_REG(hw, E1000_ICRXATC);
2082 E1000_READ_REG(hw, E1000_ICTXPTC);
2083 E1000_READ_REG(hw, E1000_ICTXATC);
2084 E1000_READ_REG(hw, E1000_ICTXQEC);
2085 E1000_READ_REG(hw, E1000_ICTXQMTC);
2086 E1000_READ_REG(hw, E1000_ICRXDMTC);
2088 E1000_READ_REG(hw, E1000_CBTMPC);
2089 E1000_READ_REG(hw, E1000_HTDPMC);
2090 E1000_READ_REG(hw, E1000_CBRMPC);
2091 E1000_READ_REG(hw, E1000_RPTHC);
2092 E1000_READ_REG(hw, E1000_HGPTC);
2093 E1000_READ_REG(hw, E1000_HTCBDPC);
2094 E1000_READ_REG(hw, E1000_HGORCL);
2095 E1000_READ_REG(hw, E1000_HGORCH);
2096 E1000_READ_REG(hw, E1000_HGOTCL);
2097 E1000_READ_REG(hw, E1000_HGOTCH);
2098 E1000_READ_REG(hw, E1000_LENERRS);
2100 /* This register should not be read in copper configurations */
2101 if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
2102 e1000_sgmii_active_82575(hw))
2103 E1000_READ_REG(hw, E1000_SCVPC);
2107 * e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
2108 * @hw: pointer to the HW structure
2110 * After rx enable if managability is enabled then there is likely some
2111 * bad data at the start of the fifo and possibly in the DMA fifo. This
2112 * function clears the fifos and flushes any packets that came in as rx was
2115 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
2117 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
2120 DEBUGFUNC("e1000_rx_fifo_workaround_82575");
2121 if (hw->mac.type != e1000_82575 ||
2122 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
2125 /* Disable all Rx queues */
2126 for (i = 0; i < 4; i++) {
2127 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
2128 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
2129 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
2131 /* Poll all queues to verify they have shut down */
2132 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
2135 for (i = 0; i < 4; i++)
2136 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2137 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
2142 DEBUGOUT("Queue disable timed out after 10ms\n");
2144 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
2145 * incoming packets are rejected. Set enable and wait 2ms so that
2146 * any packet that was coming in as RCTL.EN was set is flushed
2148 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2149 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2151 rlpml = E1000_READ_REG(hw, E1000_RLPML);
2152 E1000_WRITE_REG(hw, E1000_RLPML, 0);
2154 rctl = E1000_READ_REG(hw, E1000_RCTL);
2155 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2156 temp_rctl |= E1000_RCTL_LPE;
2158 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
2159 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2160 E1000_WRITE_FLUSH(hw);
2163 /* Enable Rx queues that were previously enabled and restore our
2166 for (i = 0; i < 4; i++)
2167 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
2168 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2169 E1000_WRITE_FLUSH(hw);
2171 E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
2172 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2174 /* Flush receive errors generated by workaround */
2175 E1000_READ_REG(hw, E1000_ROC);
2176 E1000_READ_REG(hw, E1000_RNBC);
2177 E1000_READ_REG(hw, E1000_MPC);
2181 * e1000_set_pcie_completion_timeout - set pci-e completion timeout
2182 * @hw: pointer to the HW structure
2184 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2185 * however the hardware default for these parts is 500us to 1ms which is less
2186 * than the 10ms recommended by the pci-e spec. To address this we need to
2187 * increase the value to either 10ms to 200ms for capability version 1 config,
2188 * or 16ms to 55ms for version 2.
2190 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2192 u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2193 s32 ret_val = E1000_SUCCESS;
2196 /* only take action if timeout value is defaulted to 0 */
2197 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2201 * if capababilities version is type 1 we can write the
2202 * timeout of 10ms to 200ms through the GCR register
2204 if (!(gcr & E1000_GCR_CAP_VER2)) {
2205 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2210 * for version 2 capabilities we need to write the config space
2211 * directly in order to set the completion timeout value for
2214 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2219 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2221 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2224 /* disable completion timeout resend */
2225 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2227 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2232 * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2233 * @hw: pointer to the hardware struct
2234 * @enable: state to enter, either enabled or disabled
2235 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2237 * enables/disables L2 switch anti-spoofing functionality.
2239 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2241 u32 reg_val, reg_offset;
2243 switch (hw->mac.type) {
2245 reg_offset = E1000_DTXSWC;
2249 reg_offset = E1000_TXSWC;
2255 reg_val = E1000_READ_REG(hw, reg_offset);
2257 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2258 E1000_DTXSWC_VLAN_SPOOF_MASK);
2259 /* The PF can spoof - it has to in order to
2260 * support emulation mode NICs
2262 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2264 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2265 E1000_DTXSWC_VLAN_SPOOF_MASK);
2267 E1000_WRITE_REG(hw, reg_offset, reg_val);
2271 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2272 * @hw: pointer to the hardware struct
2273 * @enable: state to enter, either enabled or disabled
2275 * enables/disables L2 switch loopback functionality.
2277 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2281 switch (hw->mac.type) {
2283 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2285 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2287 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2288 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2292 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2294 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2296 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2297 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2300 /* Currently no other hardware supports loopback */
2308 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2309 * @hw: pointer to the hardware struct
2310 * @enable: state to enter, either enabled or disabled
2312 * enables/disables replication of packets across multiple pools.
2314 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2316 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2319 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2321 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2323 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2327 * e1000_read_phy_reg_82580 - Read 82580 MDI control register
2328 * @hw: pointer to the HW structure
2329 * @offset: register offset to be read
2330 * @data: pointer to the read data
2332 * Reads the MDI control register in the PHY at offset and stores the
2333 * information read to data.
2335 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2339 DEBUGFUNC("e1000_read_phy_reg_82580");
2341 ret_val = hw->phy.ops.acquire(hw);
2345 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2347 hw->phy.ops.release(hw);
2354 * e1000_write_phy_reg_82580 - Write 82580 MDI control register
2355 * @hw: pointer to the HW structure
2356 * @offset: register offset to write to
2357 * @data: data to write to register at offset
2359 * Writes data to MDI control register in the PHY at offset.
2361 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2365 DEBUGFUNC("e1000_write_phy_reg_82580");
2367 ret_val = hw->phy.ops.acquire(hw);
2371 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2373 hw->phy.ops.release(hw);
2380 * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2381 * @hw: pointer to the HW structure
2383 * This resets the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2384 * the values found in the EEPROM. This addresses an issue in which these
2385 * bits are not restored from EEPROM after reset.
2387 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2389 s32 ret_val = E1000_SUCCESS;
2393 DEBUGFUNC("e1000_reset_mdicnfg_82580");
2395 if (hw->mac.type != e1000_82580)
2397 if (!e1000_sgmii_active_82575(hw))
2400 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2401 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2404 DEBUGOUT("NVM Read Error\n");
2408 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2409 if (nvm_data & NVM_WORD24_EXT_MDIO)
2410 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2411 if (nvm_data & NVM_WORD24_COM_MDIO)
2412 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2413 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2419 * e1000_reset_hw_82580 - Reset hardware
2420 * @hw: pointer to the HW structure
2422 * This resets function or entire device (all ports, etc.)
2425 static s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2427 s32 ret_val = E1000_SUCCESS;
2428 /* BH SW mailbox bit in SW_FW_SYNC */
2429 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2431 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2433 DEBUGFUNC("e1000_reset_hw_82580");
2435 hw->dev_spec._82575.global_device_reset = false;
2437 /* 82580 does not reliably do global_device_reset due to hw errata */
2438 if (hw->mac.type == e1000_82580)
2439 global_device_reset = false;
2441 /* Get current control state. */
2442 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2445 * Prevent the PCI-E bus from sticking if there is no TLP connection
2446 * on the last TLP read/write transaction when MAC is reset.
2448 ret_val = e1000_disable_pcie_master_generic(hw);
2450 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2452 DEBUGOUT("Masking off all interrupts\n");
2453 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2454 E1000_WRITE_REG(hw, E1000_RCTL, 0);
2455 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2456 E1000_WRITE_FLUSH(hw);
2460 /* Determine whether or not a global dev reset is requested */
2461 if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2463 global_device_reset = false;
2465 if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2466 E1000_STAT_DEV_RST_SET))
2467 ctrl |= E1000_CTRL_DEV_RST;
2469 ctrl |= E1000_CTRL_RST;
2471 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2472 E1000_WRITE_FLUSH(hw);
2474 /* Add delay to insure DEV_RST has time to complete */
2475 if (global_device_reset)
2478 ret_val = e1000_get_auto_rd_done_generic(hw);
2481 * When auto config read does not complete, do not
2482 * return with an error. This can happen in situations
2483 * where there is no eeprom and prevents getting link.
2485 DEBUGOUT("Auto Read Done did not complete\n");
2488 /* clear global device reset status bit */
2489 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2491 /* Clear any pending interrupt events. */
2492 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2493 E1000_READ_REG(hw, E1000_ICR);
2495 ret_val = e1000_reset_mdicnfg_82580(hw);
2497 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2499 /* Install any alternate MAC address into RAR0 */
2500 ret_val = e1000_check_alt_mac_addr_generic(hw);
2502 /* Release semaphore */
2503 if (global_device_reset)
2504 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2510 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2511 * @data: data received by reading RXPBS register
2513 * The 82580 uses a table based approach for packet buffer allocation sizes.
2514 * This function converts the retrieved value into the correct table value
2515 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2516 * 0x0 36 72 144 1 2 4 8 16
2517 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2519 u16 e1000_rxpbs_adjust_82580(u32 data)
2523 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2524 ret_val = e1000_82580_rxpbs_table[data];
2530 * e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2532 * @hw: pointer to the HW structure
2533 * @offset: offset in words of the checksum protected region
2535 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2536 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2538 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2540 s32 ret_val = E1000_SUCCESS;
2544 DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2546 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2547 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2549 DEBUGOUT("NVM Read Error\n");
2552 checksum += nvm_data;
2555 if (checksum != (u16) NVM_SUM) {
2556 DEBUGOUT("NVM Checksum Invalid\n");
2557 ret_val = -E1000_ERR_NVM;
2566 * e1000_update_nvm_checksum_with_offset - Update EEPROM
2568 * @hw: pointer to the HW structure
2569 * @offset: offset in words of the checksum protected region
2571 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2572 * up to the checksum. Then calculates the EEPROM checksum and writes the
2573 * value to the EEPROM.
2575 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2581 DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2583 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2584 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2586 DEBUGOUT("NVM Read Error while updating checksum.\n");
2589 checksum += nvm_data;
2591 checksum = (u16) NVM_SUM - checksum;
2592 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2595 DEBUGOUT("NVM Write Error while updating checksum.\n");
2602 * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2603 * @hw: pointer to the HW structure
2605 * Calculates the EEPROM section checksum by reading/adding each word of
2606 * the EEPROM and then verifies that the sum of the EEPROM is
2609 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2611 s32 ret_val = E1000_SUCCESS;
2612 u16 eeprom_regions_count = 1;
2616 DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2618 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2620 DEBUGOUT("NVM Read Error\n");
2624 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2625 /* if chekcsums compatibility bit is set validate checksums
2626 * for all 4 ports. */
2627 eeprom_regions_count = 4;
2630 for (j = 0; j < eeprom_regions_count; j++) {
2631 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2632 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2634 if (ret_val != E1000_SUCCESS)
2643 * e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2644 * @hw: pointer to the HW structure
2646 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2647 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2648 * checksum and writes the value to the EEPROM.
2650 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2656 DEBUGFUNC("e1000_update_nvm_checksum_82580");
2658 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2660 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2664 if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2665 /* set compatibility bit to validate checksums appropriately */
2666 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2667 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2670 DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2675 for (j = 0; j < 4; j++) {
2676 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2677 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2687 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2688 * @hw: pointer to the HW structure
2690 * Calculates the EEPROM section checksum by reading/adding each word of
2691 * the EEPROM and then verifies that the sum of the EEPROM is
2694 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2696 s32 ret_val = E1000_SUCCESS;
2700 DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2702 for (j = 0; j < 4; j++) {
2703 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2704 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2706 if (ret_val != E1000_SUCCESS)
2715 * e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2716 * @hw: pointer to the HW structure
2718 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2719 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2720 * checksum and writes the value to the EEPROM.
2722 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2724 s32 ret_val = E1000_SUCCESS;
2728 DEBUGFUNC("e1000_update_nvm_checksum_i350");
2730 for (j = 0; j < 4; j++) {
2731 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2732 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2733 if (ret_val != E1000_SUCCESS)
2742 * __e1000_access_emi_reg - Read/write EMI register
2743 * @hw: pointer to the HW structure
2744 * @addr: EMI address to program
2745 * @data: pointer to value to read/write from/to the EMI address
2746 * @read: boolean flag to indicate read or write
2748 static s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
2749 u16 *data, bool read)
2751 s32 ret_val = E1000_SUCCESS;
2753 DEBUGFUNC("__e1000_access_emi_reg");
2755 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2760 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2762 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2768 * e1000_read_emi_reg - Read Extended Management Interface register
2769 * @hw: pointer to the HW structure
2770 * @addr: EMI address to program
2771 * @data: value to be read from the EMI address
2773 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2775 DEBUGFUNC("e1000_read_emi_reg");
2777 return __e1000_access_emi_reg(hw, addr, data, true);
2781 * e1000_set_eee_i350 - Enable/disable EEE support
2782 * @hw: pointer to the HW structure
2784 * Enable/disable EEE based on setting in dev_spec structure.
2787 s32 e1000_set_eee_i350(struct e1000_hw *hw)
2789 s32 ret_val = E1000_SUCCESS;
2792 DEBUGFUNC("e1000_set_eee_i350");
2794 if ((hw->mac.type < e1000_i350) ||
2795 (hw->phy.media_type != e1000_media_type_copper))
2797 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2798 eeer = E1000_READ_REG(hw, E1000_EEER);
2800 /* enable or disable per user setting */
2801 if (!(hw->dev_spec._82575.eee_disable)) {
2802 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
2804 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2805 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2808 /* This bit should not be set in normal operation. */
2809 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2810 DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
2812 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2813 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2816 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2817 E1000_WRITE_REG(hw, E1000_EEER, eeer);
2818 E1000_READ_REG(hw, E1000_IPCNFG);
2819 E1000_READ_REG(hw, E1000_EEER);
2826 * e1000_set_eee_i354 - Enable/disable EEE support
2827 * @hw: pointer to the HW structure
2829 * Enable/disable EEE legacy mode based on setting in dev_spec structure.
2832 s32 e1000_set_eee_i354(struct e1000_hw *hw)
2834 struct e1000_phy_info *phy = &hw->phy;
2835 s32 ret_val = E1000_SUCCESS;
2838 DEBUGFUNC("e1000_set_eee_i354");
2840 if ((hw->phy.media_type != e1000_media_type_copper) ||
2841 ((phy->id != M88E1543_E_PHY_ID)))
2844 if (!hw->dev_spec._82575.eee_disable) {
2845 /* Switch to PHY page 18. */
2846 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2850 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2855 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2856 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2861 /* Return the PHY to page 0. */
2862 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2866 /* Turn on EEE advertisement. */
2867 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2868 E1000_EEE_ADV_DEV_I354,
2873 phy_data |= E1000_EEE_ADV_100_SUPPORTED |
2874 E1000_EEE_ADV_1000_SUPPORTED;
2875 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2876 E1000_EEE_ADV_DEV_I354,
2879 /* Turn off EEE advertisement. */
2880 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2881 E1000_EEE_ADV_DEV_I354,
2886 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2887 E1000_EEE_ADV_1000_SUPPORTED);
2888 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2889 E1000_EEE_ADV_DEV_I354,
2898 * e1000_get_eee_status_i354 - Get EEE status
2899 * @hw: pointer to the HW structure
2900 * @status: EEE status
2902 * Get EEE status by guessing based on whether Tx or Rx LPI indications have
2905 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2907 struct e1000_phy_info *phy = &hw->phy;
2908 s32 ret_val = E1000_SUCCESS;
2911 DEBUGFUNC("e1000_get_eee_status_i354");
2913 /* Check if EEE is supported on this device. */
2914 if ((hw->phy.media_type != e1000_media_type_copper) ||
2915 ((phy->id != M88E1543_E_PHY_ID)))
2918 ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2919 E1000_PCS_STATUS_DEV_I354,
2924 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2925 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2931 /* Due to a hw errata, if the host tries to configure the VFTA register
2932 * while performing queries from the BMC or DMA, then the VFTA in some
2933 * cases won't be written.
2937 * e1000_clear_vfta_i350 - Clear VLAN filter table
2938 * @hw: pointer to the HW structure
2940 * Clears the register array which contains the VLAN filter table by
2941 * setting all the values to 0.
2943 void e1000_clear_vfta_i350(struct e1000_hw *hw)
2948 DEBUGFUNC("e1000_clear_vfta_350");
2950 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
2951 for (i = 0; i < 10; i++)
2952 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
2954 E1000_WRITE_FLUSH(hw);
2959 * e1000_write_vfta_i350 - Write value to VLAN filter table
2960 * @hw: pointer to the HW structure
2961 * @offset: register offset in VLAN filter table
2962 * @value: register value written to VLAN filter table
2964 * Writes value at the given offset in the register array which stores
2965 * the VLAN filter table.
2967 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
2971 DEBUGFUNC("e1000_write_vfta_350");
2973 for (i = 0; i < 10; i++)
2974 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
2976 E1000_WRITE_FLUSH(hw);
2981 * e1000_set_i2c_bb - Enable I2C bit-bang
2982 * @hw: pointer to the HW structure
2984 * Enable I2C bit-bang interface
2987 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
2989 s32 ret_val = E1000_SUCCESS;
2990 u32 ctrl_ext, i2cparams;
2992 DEBUGFUNC("e1000_set_i2c_bb");
2994 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2995 ctrl_ext |= E1000_CTRL_I2C_ENA;
2996 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2997 E1000_WRITE_FLUSH(hw);
2999 i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
3000 i2cparams |= E1000_I2CBB_EN;
3001 i2cparams |= E1000_I2C_DATA_OE_N;
3002 i2cparams |= E1000_I2C_CLK_OE_N;
3003 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
3004 E1000_WRITE_FLUSH(hw);
3010 * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
3011 * @hw: pointer to hardware structure
3012 * @byte_offset: byte offset to read
3013 * @dev_addr: device address
3016 * Performs byte read operation over I2C interface at
3017 * a specified device address.
3019 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3020 u8 dev_addr, u8 *data)
3022 s32 status = E1000_SUCCESS;
3029 DEBUGFUNC("e1000_read_i2c_byte_generic");
3031 swfw_mask = E1000_SWFW_PHY0_SM;
3034 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
3036 status = E1000_ERR_SWFW_SYNC;
3040 e1000_i2c_start(hw);
3042 /* Device Address and write indication */
3043 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3044 if (status != E1000_SUCCESS)
3047 status = e1000_get_i2c_ack(hw);
3048 if (status != E1000_SUCCESS)
3051 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3052 if (status != E1000_SUCCESS)
3055 status = e1000_get_i2c_ack(hw);
3056 if (status != E1000_SUCCESS)
3059 e1000_i2c_start(hw);
3061 /* Device Address and read indication */
3062 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
3063 if (status != E1000_SUCCESS)
3066 status = e1000_get_i2c_ack(hw);
3067 if (status != E1000_SUCCESS)
3070 status = e1000_clock_in_i2c_byte(hw, data);
3071 if (status != E1000_SUCCESS)
3074 status = e1000_clock_out_i2c_bit(hw, nack);
3075 if (status != E1000_SUCCESS)
3082 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3084 e1000_i2c_bus_clear(hw);
3086 if (retry < max_retry)
3087 DEBUGOUT("I2C byte read error - Retrying.\n");
3089 DEBUGOUT("I2C byte read error.\n");
3091 } while (retry < max_retry);
3093 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3101 * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
3102 * @hw: pointer to hardware structure
3103 * @byte_offset: byte offset to write
3104 * @dev_addr: device address
3105 * @data: value to write
3107 * Performs byte write operation over I2C interface at
3108 * a specified device address.
3110 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3111 u8 dev_addr, u8 data)
3113 s32 status = E1000_SUCCESS;
3118 DEBUGFUNC("e1000_write_i2c_byte_generic");
3120 swfw_mask = E1000_SWFW_PHY0_SM;
3122 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
3123 status = E1000_ERR_SWFW_SYNC;
3124 goto write_byte_out;
3128 e1000_i2c_start(hw);
3130 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3131 if (status != E1000_SUCCESS)
3134 status = e1000_get_i2c_ack(hw);
3135 if (status != E1000_SUCCESS)
3138 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3139 if (status != E1000_SUCCESS)
3142 status = e1000_get_i2c_ack(hw);
3143 if (status != E1000_SUCCESS)
3146 status = e1000_clock_out_i2c_byte(hw, data);
3147 if (status != E1000_SUCCESS)
3150 status = e1000_get_i2c_ack(hw);
3151 if (status != E1000_SUCCESS)
3158 e1000_i2c_bus_clear(hw);
3160 if (retry < max_retry)
3161 DEBUGOUT("I2C byte write error - Retrying.\n");
3163 DEBUGOUT("I2C byte write error.\n");
3164 } while (retry < max_retry);
3166 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3174 * e1000_i2c_start - Sets I2C start condition
3175 * @hw: pointer to hardware structure
3177 * Sets I2C start condition (High -> Low on SDA while SCL is High)
3179 static void e1000_i2c_start(struct e1000_hw *hw)
3181 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3183 DEBUGFUNC("e1000_i2c_start");
3185 /* Start condition must begin with data and clock high */
3186 e1000_set_i2c_data(hw, &i2cctl, 1);
3187 e1000_raise_i2c_clk(hw, &i2cctl);
3189 /* Setup time for start condition (4.7us) */
3190 usec_delay(E1000_I2C_T_SU_STA);
3192 e1000_set_i2c_data(hw, &i2cctl, 0);
3194 /* Hold time for start condition (4us) */
3195 usec_delay(E1000_I2C_T_HD_STA);
3197 e1000_lower_i2c_clk(hw, &i2cctl);
3199 /* Minimum low period of clock is 4.7 us */
3200 usec_delay(E1000_I2C_T_LOW);
3205 * e1000_i2c_stop - Sets I2C stop condition
3206 * @hw: pointer to hardware structure
3208 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
3210 static void e1000_i2c_stop(struct e1000_hw *hw)
3212 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3214 DEBUGFUNC("e1000_i2c_stop");
3216 /* Stop condition must begin with data low and clock high */
3217 e1000_set_i2c_data(hw, &i2cctl, 0);
3218 e1000_raise_i2c_clk(hw, &i2cctl);
3220 /* Setup time for stop condition (4us) */
3221 usec_delay(E1000_I2C_T_SU_STO);
3223 e1000_set_i2c_data(hw, &i2cctl, 1);
3225 /* bus free time between stop and start (4.7us)*/
3226 usec_delay(E1000_I2C_T_BUF);
3230 * e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3231 * @hw: pointer to hardware structure
3232 * @data: data byte to clock in
3234 * Clocks in one byte data via I2C data/clock
3236 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3241 DEBUGFUNC("e1000_clock_in_i2c_byte");
3244 for (i = 7; i >= 0; i--) {
3245 e1000_clock_in_i2c_bit(hw, &bit);
3249 return E1000_SUCCESS;
3253 * e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3254 * @hw: pointer to hardware structure
3255 * @data: data byte clocked out
3257 * Clocks out one byte data via I2C data/clock
3259 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3261 s32 status = E1000_SUCCESS;
3266 DEBUGFUNC("e1000_clock_out_i2c_byte");
3268 for (i = 7; i >= 0; i--) {
3269 bit = (data >> i) & 0x1;
3270 status = e1000_clock_out_i2c_bit(hw, bit);
3272 if (status != E1000_SUCCESS)
3276 /* Release SDA line (set high) */
3277 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3279 i2cctl |= E1000_I2C_DATA_OE_N;
3280 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3281 E1000_WRITE_FLUSH(hw);
3287 * e1000_get_i2c_ack - Polls for I2C ACK
3288 * @hw: pointer to hardware structure
3290 * Clocks in/out one bit via I2C data/clock
3292 static s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3294 s32 status = E1000_SUCCESS;
3296 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3300 DEBUGFUNC("e1000_get_i2c_ack");
3302 e1000_raise_i2c_clk(hw, &i2cctl);
3304 /* Minimum high period of clock is 4us */
3305 usec_delay(E1000_I2C_T_HIGH);
3307 /* Wait until SCL returns high */
3308 for (i = 0; i < timeout; i++) {
3310 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3311 if (i2cctl & E1000_I2C_CLK_IN)
3314 if (!(i2cctl & E1000_I2C_CLK_IN))
3315 return E1000_ERR_I2C;
3317 ack = e1000_get_i2c_data(&i2cctl);
3319 DEBUGOUT("I2C ack was not received.\n");
3320 status = E1000_ERR_I2C;
3323 e1000_lower_i2c_clk(hw, &i2cctl);
3325 /* Minimum low period of clock is 4.7 us */
3326 usec_delay(E1000_I2C_T_LOW);
3332 * e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3333 * @hw: pointer to hardware structure
3334 * @data: read data value
3336 * Clocks in one bit via I2C data/clock
3338 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3340 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3342 DEBUGFUNC("e1000_clock_in_i2c_bit");
3344 e1000_raise_i2c_clk(hw, &i2cctl);
3346 /* Minimum high period of clock is 4us */
3347 usec_delay(E1000_I2C_T_HIGH);
3349 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3350 *data = e1000_get_i2c_data(&i2cctl);
3352 e1000_lower_i2c_clk(hw, &i2cctl);
3354 /* Minimum low period of clock is 4.7 us */
3355 usec_delay(E1000_I2C_T_LOW);
3357 return E1000_SUCCESS;
3361 * e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3362 * @hw: pointer to hardware structure
3363 * @data: data value to write
3365 * Clocks out one bit via I2C data/clock
3367 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3370 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3372 DEBUGFUNC("e1000_clock_out_i2c_bit");
3374 status = e1000_set_i2c_data(hw, &i2cctl, data);
3375 if (status == E1000_SUCCESS) {
3376 e1000_raise_i2c_clk(hw, &i2cctl);
3378 /* Minimum high period of clock is 4us */
3379 usec_delay(E1000_I2C_T_HIGH);
3381 e1000_lower_i2c_clk(hw, &i2cctl);
3383 /* Minimum low period of clock is 4.7 us.
3384 * This also takes care of the data hold time.
3386 usec_delay(E1000_I2C_T_LOW);
3388 status = E1000_ERR_I2C;
3389 DEBUGOUT1("I2C data was not set to %X\n", data);
3395 * e1000_raise_i2c_clk - Raises the I2C SCL clock
3396 * @hw: pointer to hardware structure
3397 * @i2cctl: Current value of I2CCTL register
3399 * Raises the I2C clock line '0'->'1'
3401 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3403 DEBUGFUNC("e1000_raise_i2c_clk");
3405 *i2cctl |= E1000_I2C_CLK_OUT;
3406 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3407 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3408 E1000_WRITE_FLUSH(hw);
3410 /* SCL rise time (1000ns) */
3411 usec_delay(E1000_I2C_T_RISE);
3415 * e1000_lower_i2c_clk - Lowers the I2C SCL clock
3416 * @hw: pointer to hardware structure
3417 * @i2cctl: Current value of I2CCTL register
3419 * Lowers the I2C clock line '1'->'0'
3421 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3424 DEBUGFUNC("e1000_lower_i2c_clk");
3426 *i2cctl &= ~E1000_I2C_CLK_OUT;
3427 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3428 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3429 E1000_WRITE_FLUSH(hw);
3431 /* SCL fall time (300ns) */
3432 usec_delay(E1000_I2C_T_FALL);
3436 * e1000_set_i2c_data - Sets the I2C data bit
3437 * @hw: pointer to hardware structure
3438 * @i2cctl: Current value of I2CCTL register
3439 * @data: I2C data value (0 or 1) to set
3441 * Sets the I2C data bit
3443 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3445 s32 status = E1000_SUCCESS;
3447 DEBUGFUNC("e1000_set_i2c_data");
3450 *i2cctl |= E1000_I2C_DATA_OUT;
3452 *i2cctl &= ~E1000_I2C_DATA_OUT;
3454 *i2cctl &= ~E1000_I2C_DATA_OE_N;
3455 *i2cctl |= E1000_I2C_CLK_OE_N;
3456 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3457 E1000_WRITE_FLUSH(hw);
3459 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3460 usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3462 *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3463 if (data != e1000_get_i2c_data(i2cctl)) {
3464 status = E1000_ERR_I2C;
3465 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3472 * e1000_get_i2c_data - Reads the I2C SDA data bit
3473 * @hw: pointer to hardware structure
3474 * @i2cctl: Current value of I2CCTL register
3476 * Returns the I2C data bit value
3478 static bool e1000_get_i2c_data(u32 *i2cctl)
3482 DEBUGFUNC("e1000_get_i2c_data");
3484 if (*i2cctl & E1000_I2C_DATA_IN)
3493 * e1000_i2c_bus_clear - Clears the I2C bus
3494 * @hw: pointer to hardware structure
3496 * Clears the I2C bus by sending nine clock pulses.
3497 * Used when data line is stuck low.
3499 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3501 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3504 DEBUGFUNC("e1000_i2c_bus_clear");
3506 e1000_i2c_start(hw);
3508 e1000_set_i2c_data(hw, &i2cctl, 1);
3510 for (i = 0; i < 9; i++) {
3511 e1000_raise_i2c_clk(hw, &i2cctl);
3513 /* Min high period of clock is 4us */
3514 usec_delay(E1000_I2C_T_HIGH);
3516 e1000_lower_i2c_clk(hw, &i2cctl);
3518 /* Min low period of clock is 4.7us*/
3519 usec_delay(E1000_I2C_T_LOW);
3522 e1000_i2c_start(hw);
3524 /* Put the i2c bus back to default state */
3528 static const u8 e1000_emc_temp_data[4] = {
3529 E1000_EMC_INTERNAL_DATA,
3530 E1000_EMC_DIODE1_DATA,
3531 E1000_EMC_DIODE2_DATA,
3532 E1000_EMC_DIODE3_DATA
3534 static const u8 e1000_emc_therm_limit[4] = {
3535 E1000_EMC_INTERNAL_THERM_LIMIT,
3536 E1000_EMC_DIODE1_THERM_LIMIT,
3537 E1000_EMC_DIODE2_THERM_LIMIT,
3538 E1000_EMC_DIODE3_THERM_LIMIT
3542 * e1000_get_thermal_sensor_data_generic - Gathers thermal sensor data
3543 * @hw: pointer to hardware structure
3545 * Updates the temperatures in mac.thermal_sensor_data
3547 s32 e1000_get_thermal_sensor_data_generic(struct e1000_hw *hw)
3549 s32 status = E1000_SUCCESS;
3557 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3559 DEBUGFUNC("e1000_get_thermal_sensor_data_generic");
3561 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
3562 return E1000_NOT_IMPLEMENTED;
3564 data->sensor[0].temp = (E1000_READ_REG(hw, E1000_THMJT) & 0xFF);
3566 /* Return the internal sensor only if ETS is unsupported */
3567 e1000_read_nvm(hw, NVM_ETS_CFG, 1, &ets_offset);
3568 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
3571 e1000_read_nvm(hw, ets_offset, 1, &ets_cfg);
3572 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
3573 != NVM_ETS_TYPE_EMC)
3574 return E1000_NOT_IMPLEMENTED;
3576 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
3577 if (num_sensors > E1000_MAX_SENSORS)
3578 num_sensors = E1000_MAX_SENSORS;
3580 for (i = 1; i < num_sensors; i++) {
3581 e1000_read_nvm(hw, (ets_offset + i), 1, &ets_sensor);
3582 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
3583 NVM_ETS_DATA_INDEX_SHIFT);
3584 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
3585 NVM_ETS_DATA_LOC_SHIFT);
3587 if (sensor_location != 0)
3588 hw->phy.ops.read_i2c_byte(hw,
3589 e1000_emc_temp_data[sensor_index],
3590 E1000_I2C_THERMAL_SENSOR_ADDR,
3591 &data->sensor[i].temp);
3597 * e1000_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
3598 * @hw: pointer to hardware structure
3600 * Sets the thermal sensor thresholds according to the NVM map
3601 * and save off the threshold and location values into mac.thermal_sensor_data
3603 s32 e1000_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
3605 s32 status = E1000_SUCCESS;
3609 u8 low_thresh_delta;
3615 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3617 DEBUGFUNC("e1000_init_thermal_sensor_thresh_generic");
3619 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
3620 return E1000_NOT_IMPLEMENTED;
3622 memset(data, 0, sizeof(struct e1000_thermal_sensor_data));
3624 data->sensor[0].location = 0x1;
3625 data->sensor[0].caution_thresh =
3626 (E1000_READ_REG(hw, E1000_THHIGHTC) & 0xFF);
3627 data->sensor[0].max_op_thresh =
3628 (E1000_READ_REG(hw, E1000_THLOWTC) & 0xFF);
3630 /* Return the internal sensor only if ETS is unsupported */
3631 e1000_read_nvm(hw, NVM_ETS_CFG, 1, &ets_offset);
3632 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
3635 e1000_read_nvm(hw, ets_offset, 1, &ets_cfg);
3636 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
3637 != NVM_ETS_TYPE_EMC)
3638 return E1000_NOT_IMPLEMENTED;
3640 low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >>
3641 NVM_ETS_LTHRES_DELTA_SHIFT);
3642 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
3644 for (i = 1; i <= num_sensors; i++) {
3645 e1000_read_nvm(hw, (ets_offset + i), 1, &ets_sensor);
3646 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
3647 NVM_ETS_DATA_INDEX_SHIFT);
3648 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
3649 NVM_ETS_DATA_LOC_SHIFT);
3650 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;
3652 hw->phy.ops.write_i2c_byte(hw,
3653 e1000_emc_therm_limit[sensor_index],
3654 E1000_I2C_THERMAL_SENSOR_ADDR,
3657 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {
3658 data->sensor[i].location = sensor_location;
3659 data->sensor[i].caution_thresh = therm_limit;
3660 data->sensor[i].max_op_thresh = therm_limit -