1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "LICENSE.GPL".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #ifndef _E1000_82575_H_
29 #define _E1000_82575_H_
31 #define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \
32 (ID_LED_DEF1_DEF2 << 8) | \
33 (ID_LED_DEF1_DEF2 << 4) | \
36 * Receive Address Register Count
37 * Number of high/low register pairs in the RAR. The RAR (Receive Address
38 * Registers) holds the directed and multicast addresses that we monitor.
39 * These entries are also used for MAC-based filtering.
42 * For 82576, there are an additional set of RARs that begin at an offset
43 * separate from the first set of RARs.
45 #define E1000_RAR_ENTRIES_82575 16
46 #define E1000_RAR_ENTRIES_82576 24
47 #define E1000_RAR_ENTRIES_82580 24
48 #define E1000_RAR_ENTRIES_I350 32
49 #define E1000_SW_SYNCH_MB 0x00000100
50 #define E1000_STAT_DEV_RST_SET 0x00100000
51 #define E1000_CTRL_DEV_RST 0x20000000
53 struct e1000_adv_data_desc {
54 __le64 buffer_addr; /* Address of the descriptor's data buffer */
58 u32 datalen:16; /* Data buffer length */
60 u32 dtyp:4; /* Descriptor type */
61 u32 dcmd:8; /* Descriptor command */
67 u32 status:4; /* Descriptor status */
69 u32 popts:6; /* Packet Options */
70 u32 paylen:18; /* Payload length */
75 #define E1000_TXD_DTYP_ADV_C 0x2 /* Advanced Context Descriptor */
76 #define E1000_TXD_DTYP_ADV_D 0x3 /* Advanced Data Descriptor */
77 #define E1000_ADV_TXD_CMD_DEXT 0x20 /* Descriptor extension (0 = legacy) */
78 #define E1000_ADV_TUCMD_IPV4 0x2 /* IP Packet Type: 1=IPv4 */
79 #define E1000_ADV_TUCMD_IPV6 0x0 /* IP Packet Type: 0=IPv6 */
80 #define E1000_ADV_TUCMD_L4T_UDP 0x0 /* L4 Packet TYPE of UDP */
81 #define E1000_ADV_TUCMD_L4T_TCP 0x4 /* L4 Packet TYPE of TCP */
82 #define E1000_ADV_TUCMD_MKRREQ 0x10 /* Indicates markers are required */
83 #define E1000_ADV_DCMD_EOP 0x1 /* End of Packet */
84 #define E1000_ADV_DCMD_IFCS 0x2 /* Insert FCS (Ethernet CRC) */
85 #define E1000_ADV_DCMD_RS 0x8 /* Report Status */
86 #define E1000_ADV_DCMD_VLE 0x40 /* Add VLAN tag */
87 #define E1000_ADV_DCMD_TSE 0x80 /* TCP Seg enable */
88 /* Extended Device Control */
89 #define E1000_CTRL_EXT_NSICR 0x00000001 /* Disable Intr Clear all on read */
91 struct e1000_adv_context_desc {
116 /* SRRCTL bit definitions */
117 #define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
118 #define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00
119 #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */
120 #define E1000_SRRCTL_DESCTYPE_LEGACY 0x00000000
121 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
122 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
123 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
124 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION 0x06000000
125 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
126 #define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000
127 #define E1000_SRRCTL_TIMESTAMP 0x40000000
128 #define E1000_SRRCTL_DROP_EN 0x80000000
130 #define E1000_SRRCTL_BSIZEPKT_MASK 0x0000007F
131 #define E1000_SRRCTL_BSIZEHDR_MASK 0x00003F00
133 #define E1000_TX_HEAD_WB_ENABLE 0x1
134 #define E1000_TX_SEQNUM_WB_ENABLE 0x2
136 #define E1000_MRQC_ENABLE_RSS_4Q 0x00000002
137 #define E1000_MRQC_ENABLE_VMDQ 0x00000003
138 #define E1000_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005
139 #define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
140 #define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
141 #define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000
142 #define E1000_MRQC_ENABLE_RSS_8Q 0x00000002
144 #define E1000_VMRCTL_MIRROR_PORT_SHIFT 8
145 #define E1000_VMRCTL_MIRROR_DSTPORT_MASK (7 << \
146 E1000_VMRCTL_MIRROR_PORT_SHIFT)
147 #define E1000_VMRCTL_POOL_MIRROR_ENABLE (1 << 0)
148 #define E1000_VMRCTL_UPLINK_MIRROR_ENABLE (1 << 1)
149 #define E1000_VMRCTL_DOWNLINK_MIRROR_ENABLE (1 << 2)
151 #define E1000_EICR_TX_QUEUE ( \
152 E1000_EICR_TX_QUEUE0 | \
153 E1000_EICR_TX_QUEUE1 | \
154 E1000_EICR_TX_QUEUE2 | \
155 E1000_EICR_TX_QUEUE3)
157 #define E1000_EICR_RX_QUEUE ( \
158 E1000_EICR_RX_QUEUE0 | \
159 E1000_EICR_RX_QUEUE1 | \
160 E1000_EICR_RX_QUEUE2 | \
161 E1000_EICR_RX_QUEUE3)
163 #define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE
164 #define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE
166 #define EIMS_ENABLE_MASK ( \
167 E1000_EIMS_RX_QUEUE | \
168 E1000_EIMS_TX_QUEUE | \
169 E1000_EIMS_TCP_TIMER | \
172 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
173 #define E1000_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */
174 #define E1000_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */
175 #define E1000_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
176 #define E1000_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */
177 #define E1000_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */
178 #define E1000_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */
179 #define E1000_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */
180 #define E1000_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */
181 #define E1000_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */
182 #define E1000_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */
184 /* Receive Descriptor - Advanced */
185 union e1000_adv_rx_desc {
187 __le64 pkt_addr; /* Packet buffer address */
188 __le64 hdr_addr; /* Header buffer address */
195 __le16 pkt_info; /*RSS type, Pkt type*/
196 /* Split Header, header buffer len */
201 __le32 rss; /* RSS Hash */
203 __le16 ip_id; /* IP id */
204 __le16 csum; /* Packet Checksum */
209 __le32 status_error; /* ext status/error */
210 __le16 length; /* Packet length */
211 __le16 vlan; /* VLAN tag */
213 } wb; /* writeback */
216 #define E1000_RXDADV_RSSTYPE_MASK 0x0000000F
217 #define E1000_RXDADV_RSSTYPE_SHIFT 12
218 #define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
219 #define E1000_RXDADV_HDRBUFLEN_SHIFT 5
220 #define E1000_RXDADV_SPLITHEADER_EN 0x00001000
221 #define E1000_RXDADV_SPH 0x8000
222 #define E1000_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */
223 #define E1000_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */
224 #define E1000_RXDADV_ERR_HBO 0x00800000
226 /* RSS Hash results */
227 #define E1000_RXDADV_RSSTYPE_NONE 0x00000000
228 #define E1000_RXDADV_RSSTYPE_IPV4_TCP 0x00000001
229 #define E1000_RXDADV_RSSTYPE_IPV4 0x00000002
230 #define E1000_RXDADV_RSSTYPE_IPV6_TCP 0x00000003
231 #define E1000_RXDADV_RSSTYPE_IPV6_EX 0x00000004
232 #define E1000_RXDADV_RSSTYPE_IPV6 0x00000005
233 #define E1000_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
234 #define E1000_RXDADV_RSSTYPE_IPV4_UDP 0x00000007
235 #define E1000_RXDADV_RSSTYPE_IPV6_UDP 0x00000008
236 #define E1000_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
238 /* RSS Packet Types as indicated in the receive descriptor */
239 #define E1000_RXDADV_PKTTYPE_NONE 0x00000000
240 #define E1000_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPV4 hdr present */
241 #define E1000_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPV4 hdr + extensions */
242 #define E1000_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPV6 hdr present */
243 #define E1000_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPV6 hdr + extensions */
244 #define E1000_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
245 #define E1000_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */
246 #define E1000_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
247 #define E1000_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */
249 #define E1000_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */
250 #define E1000_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */
251 #define E1000_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */
252 #define E1000_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */
253 #define E1000_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */
254 #define E1000_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */
256 /* LinkSec results */
257 /* Security Processing bit Indication */
258 #define E1000_RXDADV_LNKSEC_STATUS_SECP 0x00020000
259 #define E1000_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000
260 #define E1000_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000
261 #define E1000_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000
262 #define E1000_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000
264 #define E1000_RXDADV_IPSEC_STATUS_SECP 0x00020000
265 #define E1000_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000
266 #define E1000_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000
267 #define E1000_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000
268 #define E1000_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED 0x18000000
270 /* Transmit Descriptor - Advanced */
271 union e1000_adv_tx_desc {
273 __le64 buffer_addr; /* Address of descriptor's data buf */
275 __le32 olinfo_status;
278 __le64 rsvd; /* Reserved */
284 /* Adv Transmit Descriptor Config Masks */
285 #define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
286 #define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
287 #define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */
288 #define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
289 #define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */
290 #define E1000_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */
291 #define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
292 #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
293 #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
294 #define E1000_ADVTXD_MAC_LINKSEC 0x00040000 /* Apply LinkSec on pkt */
295 #define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp pkt */
296 #define E1000_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED prsnt in WB */
297 #define E1000_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */
298 #define E1000_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */
299 #define E1000_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */
300 #define E1000_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
301 /* 1st & Last TSO-full iSCSI PDU*/
302 #define E1000_ADVTXD_POPTS_ISCO_FULL 0x00001800
303 #define E1000_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */
304 #define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
306 /* Context descriptors */
307 struct e1000_adv_tx_context_desc {
308 __le32 vlan_macip_lens;
310 __le32 type_tucmd_mlhl;
311 __le32 mss_l4len_idx;
314 #define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
315 #define E1000_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
316 #define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
317 #define E1000_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
318 #define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
319 #define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
320 #define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
321 #define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
322 /* IPSec Encrypt Enable for ESP */
323 #define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000
324 /* Req requires Markers and CRC */
325 #define E1000_ADVTXD_TUCMD_MKRREQ 0x00002000
326 #define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
327 #define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
328 /* Adv ctxt IPSec SA IDX mask */
329 #define E1000_ADVTXD_IPSEC_SA_INDEX_MASK 0x000000FF
330 /* Adv ctxt IPSec ESP len mask */
331 #define E1000_ADVTXD_IPSEC_ESP_LEN_MASK 0x000000FF
333 /* Additional Transmit Descriptor Control definitions */
334 #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */
335 #define E1000_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. wbk flushing */
336 /* Tx Queue Arbitration Priority 0=low, 1=high */
337 #define E1000_TXDCTL_PRIORITY 0x08000000
339 /* Additional Receive Descriptor Control definitions */
340 #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */
341 #define E1000_RXDCTL_SWFLSH 0x04000000 /* Rx Desc. wbk flushing */
343 /* Direct Cache Access (DCA) definitions */
344 #define E1000_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */
345 #define E1000_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
347 #define E1000_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
348 #define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
350 #define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
351 #define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
352 #define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header ena */
353 #define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload ena */
354 #define E1000_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx Desc Relax Order */
356 #define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
357 #define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
358 #define E1000_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */
359 #define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
360 #define E1000_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */
362 #define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
363 #define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
364 #define E1000_DCA_TXCTRL_CPUID_SHIFT_82576 24 /* Tx CPUID */
365 #define E1000_DCA_RXCTRL_CPUID_SHIFT_82576 24 /* Rx CPUID */
367 /* Additional interrupt register bit definitions */
368 #define E1000_ICR_LSECPNS 0x00000020 /* PN threshold - server */
369 #define E1000_IMS_LSECPNS E1000_ICR_LSECPNS /* PN threshold - server */
370 #define E1000_ICS_LSECPNS E1000_ICR_LSECPNS /* PN threshold - server */
372 /* ETQF register bit definitions */
373 #define E1000_ETQF_FILTER_ENABLE (1 << 26)
374 #define E1000_ETQF_IMM_INT (1 << 29)
375 #define E1000_ETQF_1588 (1 << 30)
376 #define E1000_ETQF_QUEUE_ENABLE (1 << 31)
378 * ETQF filter list: one static filter per filter consumer. This is
379 * to avoid filter collisions later. Add new filters
383 * EAPOL 802.1x (0x888e): Filter 0
385 #define E1000_ETQF_FILTER_EAPOL 0
387 #define E1000_FTQF_VF_BP 0x00008000
388 #define E1000_FTQF_1588_TIME_STAMP 0x08000000
389 #define E1000_FTQF_MASK 0xF0000000
390 #define E1000_FTQF_MASK_PROTO_BP 0x10000000
391 #define E1000_FTQF_MASK_SOURCE_ADDR_BP 0x20000000
392 #define E1000_FTQF_MASK_DEST_ADDR_BP 0x40000000
393 #define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000
395 #define E1000_NVM_APME_82575 0x0400
396 #define MAX_NUM_VFS 7
398 #define E1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF /* Per VF MAC spoof cntrl */
399 #define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof cntrl */
400 #define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */
401 #define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8
402 #define E1000_DTXSWC_LLE_SHIFT 16
403 #define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31) /* global VF LB enable */
405 /* Easy defines for setting default pool, would normally be left a zero */
406 #define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7
407 #define E1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)
409 /* Other useful VMD_CTL register defines */
410 #define E1000_VT_CTL_IGNORE_MAC (1 << 28)
411 #define E1000_VT_CTL_DISABLE_DEF_POOL (1 << 29)
412 #define E1000_VT_CTL_VM_REPL_EN (1 << 30)
414 /* Per VM Offload register setup */
415 #define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */
416 #define E1000_VMOLR_LPE 0x00010000 /* Accept Long packet */
417 #define E1000_VMOLR_RSSE 0x00020000 /* Enable RSS */
418 #define E1000_VMOLR_AUPE 0x01000000 /* Accept untagged packets */
419 #define E1000_VMOLR_ROMPE 0x02000000 /* Accept overflow multicast */
420 #define E1000_VMOLR_ROPE 0x04000000 /* Accept overflow unicast */
421 #define E1000_VMOLR_BAM 0x08000000 /* Accept Broadcast packets */
422 #define E1000_VMOLR_MPME 0x10000000 /* Multicast promiscuous mode */
423 #define E1000_VMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */
424 #define E1000_VMOLR_STRCRC 0x80000000 /* CRC stripping enable */
426 #define E1000_VMOLR_VPE 0x00800000 /* VLAN promiscuous enable */
427 #define E1000_VMOLR_UPE 0x20000000 /* Unicast promisuous enable */
428 #define E1000_DVMOLR_HIDVLAN 0x20000000 /* Vlan hiding enable */
429 #define E1000_DVMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */
430 #define E1000_DVMOLR_STRCRC 0x80000000 /* CRC stripping enable */
432 #define E1000_PBRWAC_WALPB 0x00000007 /* Wrap around event on LAN Rx PB */
433 #define E1000_PBRWAC_PBE 0x00000008 /* Rx packet buffer empty */
435 #define E1000_VLVF_ARRAY_SIZE 32
436 #define E1000_VLVF_VLANID_MASK 0x00000FFF
437 #define E1000_VLVF_POOLSEL_SHIFT 12
438 #define E1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT)
439 #define E1000_VLVF_LVLAN 0x00100000
440 #define E1000_VLVF_VLANID_ENABLE 0x80000000
442 #define E1000_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
443 #define E1000_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */
445 #define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
447 #define E1000_IOVCTL 0x05BBC
448 #define E1000_IOVCTL_REUSE_VFQ 0x00000001
450 #define E1000_RPLOLR_STRVLAN 0x40000000
451 #define E1000_RPLOLR_STRCRC 0x80000000
453 #define E1000_TCTL_EXT_COLD 0x000FFC00
454 #define E1000_TCTL_EXT_COLD_SHIFT 10
456 #define E1000_DTXCTL_8023LL 0x0004
457 #define E1000_DTXCTL_VLAN_ADDED 0x0008
458 #define E1000_DTXCTL_OOS_ENABLE 0x0010
459 #define E1000_DTXCTL_MDP_EN 0x0020
460 #define E1000_DTXCTL_SPOOF_INT 0x0040
462 #define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT (1 << 14)
464 #define ALL_QUEUES 0xFFFF
466 /* Rx packet buffer size defines */
467 #define E1000_RXPBS_SIZE_MASK_82576 0x0000007F
468 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable);
469 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf);
470 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable);
471 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw);
473 u16 e1000_rxpbs_adjust_82580(u32 data);
474 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data);
475 s32 e1000_set_eee_i350(struct e1000_hw *);
476 s32 e1000_set_eee_i354(struct e1000_hw *);
477 s32 e1000_get_eee_status_i354(struct e1000_hw *, bool *);
478 #define E1000_I2C_THERMAL_SENSOR_ADDR 0xF8
479 #define E1000_EMC_INTERNAL_DATA 0x00
480 #define E1000_EMC_INTERNAL_THERM_LIMIT 0x20
481 #define E1000_EMC_DIODE1_DATA 0x01
482 #define E1000_EMC_DIODE1_THERM_LIMIT 0x19
483 #define E1000_EMC_DIODE2_DATA 0x23
484 #define E1000_EMC_DIODE2_THERM_LIMIT 0x1A
485 #define E1000_EMC_DIODE3_DATA 0x2A
486 #define E1000_EMC_DIODE3_THERM_LIMIT 0x30
488 s32 e1000_get_thermal_sensor_data_generic(struct e1000_hw *hw);
489 s32 e1000_init_thermal_sensor_thresh_generic(struct e1000_hw *hw);
491 /* I2C SDA and SCL timing parameters for standard mode */
492 #define E1000_I2C_T_HD_STA 4
493 #define E1000_I2C_T_LOW 5
494 #define E1000_I2C_T_HIGH 4
495 #define E1000_I2C_T_SU_STA 5
496 #define E1000_I2C_T_HD_DATA 5
497 #define E1000_I2C_T_SU_DATA 1
498 #define E1000_I2C_T_RISE 1
499 #define E1000_I2C_T_FALL 1
500 #define E1000_I2C_T_SU_STO 4
501 #define E1000_I2C_T_BUF 5
503 s32 e1000_set_i2c_bb(struct e1000_hw *hw);
504 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
505 u8 dev_addr, u8 *data);
506 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
507 u8 dev_addr, u8 data);
508 void e1000_i2c_bus_clear(struct e1000_hw *hw);
509 #endif /* _E1000_82575_H_ */