1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #ifndef _E1000_DEFINES_H_
29 #define _E1000_DEFINES_H_
31 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
32 #define REQ_TX_DESCRIPTOR_MULTIPLE 8
33 #define REQ_RX_DESCRIPTOR_MULTIPLE 8
35 /* Definitions for power management and wakeup registers */
37 #define E1000_WUC_APME 0x00000001 /* APM Enable */
38 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
39 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
40 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
41 #define E1000_WUC_LSCWE 0x00000010 /* Link Status wake up enable */
42 #define E1000_WUC_PPROXYE 0x00000010 /* Protocol Proxy Enable */
43 #define E1000_WUC_LSCWO 0x00000020 /* Link Status wake up override */
44 #define E1000_WUC_SPM 0x80000000 /* Enable SPM */
45 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
47 /* Wake Up Filter Control */
48 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
49 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
50 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
51 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
52 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
53 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
54 #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
55 #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
56 #define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
57 #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
58 #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
59 #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
60 #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
61 #define E1000_WUFC_FW_RST 0x80000000 /* Wake on FW Reset Enable */
62 #define E1000_WUFC_ALL_FILTERS 0x000F00FF /* all wakeup filters mask */
63 #define E1000_WUFC_FLX_OFFSET 16 /* Flexible Filters bits offset */
64 #define E1000_WUFC_FLX_FILTERS 0x000F0000 /* 4 flexible filters mask */
66 * For 82576 to utilize Extended filter masks in addition to
67 * existing (filter) masks
69 #define E1000_WUFC_EXT_FLX_FILTERS 0x00300000 /* Ext. FLX filter mask */
72 #define E1000_WUS_LNKC E1000_WUFC_LNKC
73 #define E1000_WUS_MAG E1000_WUFC_MAG
74 #define E1000_WUS_EX E1000_WUFC_EX
75 #define E1000_WUS_MC E1000_WUFC_MC
76 #define E1000_WUS_BC E1000_WUFC_BC
77 #define E1000_WUS_ARP E1000_WUFC_ARP
78 #define E1000_WUS_IPV4 E1000_WUFC_IPV4
79 #define E1000_WUS_IPV6 E1000_WUFC_IPV6
80 #define E1000_WUS_FLX0 E1000_WUFC_FLX0
81 #define E1000_WUS_FLX1 E1000_WUFC_FLX1
82 #define E1000_WUS_FLX2 E1000_WUFC_FLX2
83 #define E1000_WUS_FLX3 E1000_WUFC_FLX3
84 #define E1000_WUS_FLX_FILTERS E1000_WUFC_FLX_FILTERS
86 /* Wake Up Packet Length */
87 #define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
89 /* Four Flexible Filters are supported */
90 #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
91 /* Two Extended Flexible Filters are supported (82576) */
92 #define E1000_EXT_FLEXIBLE_FILTER_COUNT_MAX 2
93 #define E1000_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */
94 #define E1000_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */
96 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
97 #define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
99 #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
100 #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
101 #define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
103 /* Extended Device Control */
104 #define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
105 #define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
106 #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
107 #define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
108 #define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
109 /* Reserved (bits 4,5) in >= 82575 */
110 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* SW Definable Pin 4 data */
111 #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* SW Definable Pin 5 data */
112 #define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
113 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* SW Definable Pin 6 data */
114 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* SW Definable Pin 3 data */
115 /* SDP 4/5 (bits 8,9) are reserved in >= 82575 */
116 #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
117 #define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
118 #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
119 #define E1000_CTRL_EXT_SDP3_DIR 0x00000800 /* Direction of SDP3 0=in 1=out */
120 #define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
121 #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
122 #define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
123 /* Physical Func Reset Done Indication */
124 #define E1000_CTRL_EXT_PFRSTD 0x00004000
125 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
126 #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
127 #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clk Gating */
128 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
129 /* Offset of the link mode field in Ctrl Ext register */
130 #define E1000_CTRL_EXT_LINK_MODE_OFFSET 22
131 #define E1000_CTRL_EXT_LINK_MODE_82580_MASK 0x01C00000 /*82580 bit 24:22*/
132 #define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000
133 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
134 #define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
135 #define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000
136 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
137 #define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES 0x00800000
138 #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
139 #define E1000_CTRL_EXT_EIAME 0x01000000
140 #define E1000_CTRL_EXT_IRCA 0x00000001
141 #define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
142 #define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
143 #define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
144 #define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
145 #define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
146 #define E1000_CTRL_EXT_CANC 0x04000000 /* Int delay cancellation */
147 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */
148 /* IAME enable bit (27) was removed in >= 82575 */
149 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
150 /* packet buffer parity error detection enabled */
151 #define E1000_CRTL_EXT_PB_PAREN 0x01000000
152 /* descriptor FIFO parity error detection enable */
153 #define E1000_CTRL_EXT_DF_PAREN 0x02000000
154 #define E1000_CTRL_EXT_GHOST_PAREN 0x40000000
155 #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */
156 #define E1000_I2CCMD_REG_ADDR_SHIFT 16
157 #define E1000_I2CCMD_REG_ADDR 0x00FF0000
158 #define E1000_I2CCMD_PHY_ADDR_SHIFT 24
159 #define E1000_I2CCMD_PHY_ADDR 0x07000000
160 #define E1000_I2CCMD_OPCODE_READ 0x08000000
161 #define E1000_I2CCMD_OPCODE_WRITE 0x00000000
162 #define E1000_I2CCMD_RESET 0x10000000
163 #define E1000_I2CCMD_READY 0x20000000
164 #define E1000_I2CCMD_INTERRUPT_ENA 0x40000000
165 #define E1000_I2CCMD_ERROR 0x80000000
166 #define E1000_I2CCMD_SFP_DATA_ADDR(a) (0x0000 + (a))
167 #define E1000_I2CCMD_SFP_DIAG_ADDR(a) (0x0100 + (a))
168 #define E1000_MAX_SGMII_PHY_REG_ADDR 255
169 #define E1000_I2CCMD_PHY_TIMEOUT 200
170 #define E1000_IVAR_VALID 0x80
171 #define E1000_GPIE_NSICR 0x00000001
172 #define E1000_GPIE_MSIX_MODE 0x00000010
173 #define E1000_GPIE_EIAME 0x40000000
174 #define E1000_GPIE_PBA 0x80000000
176 /* Receive Descriptor bit definitions */
177 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
178 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
179 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
180 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
181 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
182 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
183 #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
184 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
185 #define E1000_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
186 #define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */
187 #define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
188 #define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
189 #define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
190 #define E1000_RXD_ERR_CE 0x01 /* CRC Error */
191 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
192 #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
193 #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
194 #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
195 #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
196 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
197 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
198 #define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
199 #define E1000_RXD_SPC_PRI_SHIFT 13
200 #define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
201 #define E1000_RXD_SPC_CFI_SHIFT 12
203 #define E1000_RXDEXT_STATERR_LB 0x00040000
204 #define E1000_RXDEXT_STATERR_CE 0x01000000
205 #define E1000_RXDEXT_STATERR_SE 0x02000000
206 #define E1000_RXDEXT_STATERR_SEQ 0x04000000
207 #define E1000_RXDEXT_STATERR_CXE 0x10000000
208 #define E1000_RXDEXT_STATERR_TCPE 0x20000000
209 #define E1000_RXDEXT_STATERR_IPE 0x40000000
210 #define E1000_RXDEXT_STATERR_RXE 0x80000000
212 /* mask to determine if packets should be dropped due to frame errors */
213 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \
216 E1000_RXD_ERR_SEQ | \
217 E1000_RXD_ERR_CXE | \
220 /* Same mask, but for extended and packet split descriptors */
221 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
222 E1000_RXDEXT_STATERR_CE | \
223 E1000_RXDEXT_STATERR_SE | \
224 E1000_RXDEXT_STATERR_SEQ | \
225 E1000_RXDEXT_STATERR_CXE | \
226 E1000_RXDEXT_STATERR_RXE)
228 #define E1000_MRQC_ENABLE_MASK 0x00000007
229 #define E1000_MRQC_ENABLE_RSS_2Q 0x00000001
230 #define E1000_MRQC_ENABLE_RSS_INT 0x00000004
231 #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
232 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
233 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
234 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
235 #define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
236 #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
237 #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
239 #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
240 #define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
242 /* Management Control */
243 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
244 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
245 #define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
246 #define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
247 #define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
248 #define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
249 #define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
250 #define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
251 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
252 /* Enable Neighbor Discovery Filtering */
253 #define E1000_MANC_NEIGHBOR_EN 0x00004000
254 #define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */
255 #define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
256 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
257 #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
258 #define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */
259 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
260 /* Enable MAC address filtering */
261 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
262 /* Enable MNG packets to host memory */
263 #define E1000_MANC_EN_MNG2HOST 0x00200000
264 /* Enable IP address filtering */
265 #define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000
266 #define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Ena checksum filtering */
267 #define E1000_MANC_BR_EN 0x01000000 /* Ena broadcast filtering */
268 #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
269 #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
270 #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
271 #define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
272 #define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
273 #define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
274 #define E1000_MANC_MPROXYE 0x40000000 /* Mngment Proxy Enable */
275 #define E1000_MANC_EN_BMC2OS 0x10000000 /* OS2BMC is enabld or not */
277 #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
278 #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
280 #define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */
281 #define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */
282 #define E1000_MDEF_PORT_623 0x00000800 /* Port 0x26f */
283 #define E1000_MDEF_PORT_664 0x00000400 /* Port 0x298 */
285 /* Receive Control */
286 #define E1000_RCTL_RST 0x00000001 /* Software reset */
287 #define E1000_RCTL_EN 0x00000002 /* enable */
288 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */
289 #define E1000_RCTL_UPE 0x00000008 /* unicast promisc enable */
290 #define E1000_RCTL_MPE 0x00000010 /* multicast promisc enable */
291 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */
292 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
293 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
294 #define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
295 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
296 #define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */
297 #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
298 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */
299 #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* Rx desc min thresh size */
300 #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* Rx desc min thresh size */
301 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
302 #define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
303 #define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
304 #define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
305 #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
306 #define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
307 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
308 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
309 #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */
310 #define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */
311 #define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */
312 #define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */
313 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
314 #define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */
315 #define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */
316 #define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */
317 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
318 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
319 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
320 #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
321 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
322 #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
323 #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
324 #define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */
325 #define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */
328 * Use byte values for the following shift parameters
330 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
331 * E1000_PSRCTL_BSIZE0_MASK) |
332 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
333 * E1000_PSRCTL_BSIZE1_MASK) |
334 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
335 * E1000_PSRCTL_BSIZE2_MASK) |
336 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
337 * E1000_PSRCTL_BSIZE3_MASK))
338 * where value0 = [128..16256], default=256
339 * value1 = [1024..64512], default=4096
340 * value2 = [0..64512], default=4096
341 * value3 = [0..64512], default=0
344 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
345 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
346 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
347 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
349 #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
350 #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
351 #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
352 #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
354 /* SWFW_SYNC Definitions */
355 #define E1000_SWFW_EEP_SM 0x01
356 #define E1000_SWFW_PHY0_SM 0x02
357 #define E1000_SWFW_PHY1_SM 0x04
358 #define E1000_SWFW_CSR_SM 0x08
359 #define E1000_SWFW_PHY2_SM 0x20
360 #define E1000_SWFW_PHY3_SM 0x40
361 #define E1000_SWFW_SW_MNG_SM 0x400
363 /* FACTPS Definitions */
364 #define E1000_FACTPS_LFS 0x40000000 /* LAN Function Select */
366 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
367 #define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
368 #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
369 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */
370 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
371 #define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
372 #define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
373 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
374 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
375 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
376 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
377 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
378 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
379 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
380 #define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
381 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
382 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
383 #define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */
384 /* Defined polarity of Dock/Undock indication in SDP[0] */
385 #define E1000_CTRL_D_UD_POLARITY 0x00004000
386 /* Reset both PHY ports, through PHYRST_N pin */
387 #define E1000_CTRL_FORCE_PHY_RESET 0x00008000
388 /* enable link status from external LINK_0 and LINK_1 pins */
389 #define E1000_CTRL_EXT_LINK_EN 0x00010000
390 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
391 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
392 #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
393 #define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */
394 #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
395 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
396 #define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
397 #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
398 #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
399 #define E1000_CTRL_RST 0x04000000 /* Global reset */
400 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
401 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
402 #define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
403 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
404 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
405 #define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to ME */
406 #define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */
409 * Bit definitions for the Management Data IO (MDIO) and Management Data
410 * Clock (MDC) pins in the Device Control Register.
412 #define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
413 #define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
414 #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
415 #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
416 #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
417 #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
418 #define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
419 #define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
421 #define E1000_CONNSW_ENRGSRC 0x4
422 #define E1000_PCS_CFG_PCS_EN 8
423 #define E1000_PCS_LCTL_FLV_LINK_UP 1
424 #define E1000_PCS_LCTL_FSV_10 0
425 #define E1000_PCS_LCTL_FSV_100 2
426 #define E1000_PCS_LCTL_FSV_1000 4
427 #define E1000_PCS_LCTL_FDV_FULL 8
428 #define E1000_PCS_LCTL_FSD 0x10
429 #define E1000_PCS_LCTL_FORCE_LINK 0x20
430 #define E1000_PCS_LCTL_LOW_LINK_LATCH 0x40
431 #define E1000_PCS_LCTL_FORCE_FCTRL 0x80
432 #define E1000_PCS_LCTL_AN_ENABLE 0x10000
433 #define E1000_PCS_LCTL_AN_RESTART 0x20000
434 #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000
435 #define E1000_PCS_LCTL_AN_SGMII_BYPASS 0x80000
436 #define E1000_PCS_LCTL_AN_SGMII_TRIGGER 0x100000
437 #define E1000_PCS_LCTL_FAST_LINK_TIMER 0x1000000
438 #define E1000_PCS_LCTL_LINK_OK_FIX 0x2000000
439 #define E1000_PCS_LCTL_CRS_ON_NI 0x4000000
440 #define E1000_ENABLE_SERDES_LOOPBACK 0x0410
442 #define E1000_PCS_LSTS_LINK_OK 1
443 #define E1000_PCS_LSTS_SPEED_10 0
444 #define E1000_PCS_LSTS_SPEED_100 2
445 #define E1000_PCS_LSTS_SPEED_1000 4
446 #define E1000_PCS_LSTS_DUPLEX_FULL 8
447 #define E1000_PCS_LSTS_SYNK_OK 0x10
448 #define E1000_PCS_LSTS_AN_COMPLETE 0x10000
449 #define E1000_PCS_LSTS_AN_PAGE_RX 0x20000
450 #define E1000_PCS_LSTS_AN_TIMED_OUT 0x40000
451 #define E1000_PCS_LSTS_AN_REMOTE_FAULT 0x80000
452 #define E1000_PCS_LSTS_AN_ERROR_RWS 0x100000
455 #define E1000_STATUS_FD 0x00000001 /* Duplex 0=half 1=full */
456 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
457 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
458 #define E1000_STATUS_FUNC_SHIFT 2
459 #define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
460 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
461 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
462 #define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
463 #define E1000_STATUS_SPEED_MASK 0x000000C0
464 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
465 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
466 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
467 #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Compltn by NVM */
468 #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
469 #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */
470 /* Change in Dock/Undock state clear on write '0'. */
471 #define E1000_STATUS_DOCK_CI 0x00000800
472 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */
473 #define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
474 #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
475 #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
476 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
477 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
478 #define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disbld */
479 #define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */
480 #define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */
481 #define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */
482 /* BMC external code execution disabled */
483 #define E1000_STATUS_BMC_LITE 0x01000000
484 #define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */
485 #define E1000_STATUS_FUSE_8 0x04000000
486 #define E1000_STATUS_FUSE_9 0x08000000
487 #define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disbld on port 0 */
488 #define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disbld on port 1 */
490 /* Constants used to interpret the masked PCI-X bus speed. */
491 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */
492 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus spd 66-100MHz */
493 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus spd 100-133MHz*/
496 #define SPEED_100 100
497 #define SPEED_1000 1000
498 #define HALF_DUPLEX 1
499 #define FULL_DUPLEX 2
501 #define PHY_FORCE_TIME 20
503 #define ADVERTISE_10_HALF 0x0001
504 #define ADVERTISE_10_FULL 0x0002
505 #define ADVERTISE_100_HALF 0x0004
506 #define ADVERTISE_100_FULL 0x0008
507 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
508 #define ADVERTISE_1000_FULL 0x0020
510 /* 1000/H is not supported, nor spec-compliant. */
511 #define E1000_ALL_SPEED_DUPLEX ( \
512 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
513 ADVERTISE_100_FULL | ADVERTISE_1000_FULL)
514 #define E1000_ALL_NOT_GIG ( \
515 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
517 #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
518 #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
519 #define E1000_ALL_FULL_DUPLEX ( \
520 ADVERTISE_10_FULL | ADVERTISE_100_FULL | ADVERTISE_1000_FULL)
521 #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
523 #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
526 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
527 #define E1000_LEDCTL_LED0_MODE_SHIFT 0
528 #define E1000_LEDCTL_LED0_BLINK_RATE 0x00000020
529 #define E1000_LEDCTL_LED0_IVRT 0x00000040
530 #define E1000_LEDCTL_LED0_BLINK 0x00000080
531 #define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
532 #define E1000_LEDCTL_LED1_MODE_SHIFT 8
533 #define E1000_LEDCTL_LED1_BLINK_RATE 0x00002000
534 #define E1000_LEDCTL_LED1_IVRT 0x00004000
535 #define E1000_LEDCTL_LED1_BLINK 0x00008000
536 #define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
537 #define E1000_LEDCTL_LED2_MODE_SHIFT 16
538 #define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000
539 #define E1000_LEDCTL_LED2_IVRT 0x00400000
540 #define E1000_LEDCTL_LED2_BLINK 0x00800000
541 #define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
542 #define E1000_LEDCTL_LED3_MODE_SHIFT 24
543 #define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000
544 #define E1000_LEDCTL_LED3_IVRT 0x40000000
545 #define E1000_LEDCTL_LED3_BLINK 0x80000000
547 #define E1000_LEDCTL_MODE_LINK_10_1000 0x0
548 #define E1000_LEDCTL_MODE_LINK_100_1000 0x1
549 #define E1000_LEDCTL_MODE_LINK_UP 0x2
550 #define E1000_LEDCTL_MODE_ACTIVITY 0x3
551 #define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
552 #define E1000_LEDCTL_MODE_LINK_10 0x5
553 #define E1000_LEDCTL_MODE_LINK_100 0x6
554 #define E1000_LEDCTL_MODE_LINK_1000 0x7
555 #define E1000_LEDCTL_MODE_PCIX_MODE 0x8
556 #define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
557 #define E1000_LEDCTL_MODE_COLLISION 0xA
558 #define E1000_LEDCTL_MODE_BUS_SPEED 0xB
559 #define E1000_LEDCTL_MODE_BUS_SIZE 0xC
560 #define E1000_LEDCTL_MODE_PAUSED 0xD
561 #define E1000_LEDCTL_MODE_LED_ON 0xE
562 #define E1000_LEDCTL_MODE_LED_OFF 0xF
564 /* Transmit Descriptor bit definitions */
565 #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
566 #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
567 #define E1000_TXD_POPTS_SHIFT 8 /* POPTS shift */
568 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
569 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
570 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
571 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
572 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
573 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
574 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
575 #define E1000_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */
576 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
577 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
578 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
579 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
580 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
581 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
582 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
583 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
584 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
585 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
586 /* Extended desc bits for Linksec and timesync */
588 /* Transmit Control */
589 #define E1000_TCTL_RST 0x00000001 /* software reset */
590 #define E1000_TCTL_EN 0x00000002 /* enable Tx */
591 #define E1000_TCTL_BCE 0x00000004 /* busy check enable */
592 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */
593 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
594 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */
595 #define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
596 #define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
597 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
598 #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
599 #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
601 /* Transmit Arbitration Count */
602 #define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */
605 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
607 /* Receive Checksum Control */
608 #define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
609 #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
610 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
611 #define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
612 #define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */
613 #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
614 #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
616 /* Header split receive */
617 #define E1000_RFCTL_ISCSI_DIS 0x00000001
618 #define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E
619 #define E1000_RFCTL_ISCSI_DWC_SHIFT 1
620 #define E1000_RFCTL_NFSW_DIS 0x00000040
621 #define E1000_RFCTL_NFSR_DIS 0x00000080
622 #define E1000_RFCTL_NFS_VER_MASK 0x00000300
623 #define E1000_RFCTL_NFS_VER_SHIFT 8
624 #define E1000_RFCTL_IPV6_DIS 0x00000400
625 #define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800
626 #define E1000_RFCTL_ACK_DIS 0x00001000
627 #define E1000_RFCTL_ACKD_DIS 0x00002000
628 #define E1000_RFCTL_IPFRSP_DIS 0x00004000
629 #define E1000_RFCTL_EXTEN 0x00008000
630 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000
631 #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
632 #define E1000_RFCTL_LEF 0x00040000
634 /* Collision related configuration parameters */
635 #define E1000_COLLISION_THRESHOLD 15
636 #define E1000_CT_SHIFT 4
637 #define E1000_COLLISION_DISTANCE 63
638 #define E1000_COLD_SHIFT 12
640 /* Default values for the transmit IPG register */
641 #define DEFAULT_82543_TIPG_IPGT_FIBER 9
642 #define DEFAULT_82543_TIPG_IPGT_COPPER 8
644 #define E1000_TIPG_IPGT_MASK 0x000003FF
645 #define E1000_TIPG_IPGR1_MASK 0x000FFC00
646 #define E1000_TIPG_IPGR2_MASK 0x3FF00000
648 #define DEFAULT_82543_TIPG_IPGR1 8
649 #define E1000_TIPG_IPGR1_SHIFT 10
651 #define DEFAULT_82543_TIPG_IPGR2 6
652 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
653 #define E1000_TIPG_IPGR2_SHIFT 20
655 /* Ethertype field values */
656 #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
658 #define ETHERNET_FCS_SIZE 4
659 #define MAX_JUMBO_FRAME_SIZE 0x3F00
661 /* Extended Configuration Control and Size */
662 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
663 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
664 #define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008
665 #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
666 #define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080
667 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000
668 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16
669 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000
670 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16
672 #define E1000_PHY_CTRL_SPD_EN 0x00000001
673 #define E1000_PHY_CTRL_D0A_LPLU 0x00000002
674 #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
675 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
676 #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
678 #define E1000_KABGTXD_BGSQLBIAS 0x00050000
681 #define E1000_PBA_6K 0x0006 /* 6KB */
682 #define E1000_PBA_8K 0x0008 /* 8KB */
683 #define E1000_PBA_10K 0x000A /* 10KB */
684 #define E1000_PBA_12K 0x000C /* 12KB */
685 #define E1000_PBA_14K 0x000E /* 14KB */
686 #define E1000_PBA_16K 0x0010 /* 16KB */
687 #define E1000_PBA_18K 0x0012
688 #define E1000_PBA_20K 0x0014
689 #define E1000_PBA_22K 0x0016
690 #define E1000_PBA_24K 0x0018
691 #define E1000_PBA_26K 0x001A
692 #define E1000_PBA_30K 0x001E
693 #define E1000_PBA_32K 0x0020
694 #define E1000_PBA_34K 0x0022
695 #define E1000_PBA_35K 0x0023
696 #define E1000_PBA_38K 0x0026
697 #define E1000_PBA_40K 0x0028
698 #define E1000_PBA_48K 0x0030 /* 48KB */
699 #define E1000_PBA_64K 0x0040 /* 64KB */
701 #define E1000_PBA_RXA_MASK 0xFFFF;
703 #define E1000_PBS_16K E1000_PBA_16K
704 #define E1000_PBS_24K E1000_PBA_24K
710 #define MIN_NUM_XMITS 1000
712 /* SW Semaphore Register */
713 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
714 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
715 #define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
716 #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
718 #define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */
720 /* Interrupt Cause Read */
721 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
722 #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
723 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */
724 #define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */
725 #define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */
726 #define E1000_ICR_RXO 0x00000040 /* Rx overrun */
727 #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */
728 #define E1000_ICR_VMMB 0x00000100 /* VM MB event */
729 #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
730 #define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */
731 #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
732 #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
733 #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
734 #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
735 #define E1000_ICR_TXD_LOW 0x00008000
736 #define E1000_ICR_SRPD 0x00010000
737 #define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */
738 #define E1000_ICR_MNG 0x00040000 /* Manageability event */
739 #define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */
740 #define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */
741 /* If this bit asserted, the driver should claim the interrupt */
742 #define E1000_ICR_INT_ASSERTED 0x80000000
743 #define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* Q0 Rx desc FIFO parity error */
744 #define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* Q0 Tx desc FIFO parity error */
745 #define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity err */
746 #define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */
747 #define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* Q1 Rx desc FIFO parity error */
748 #define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* Q1 Tx desc FIFO parity error */
749 #define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */
750 /* FW changed the status of DISSW bit in the FWSM */
751 #define E1000_ICR_DSW 0x00000020
752 /* LAN connected device generates an interrupt */
753 #define E1000_ICR_PHYINT 0x00001000
754 #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
755 #define E1000_ICR_EPRST 0x00100000 /* ME hardware reset occurs */
756 #define E1000_ICR_FER 0x00400000 /* Fatal Error */
758 #define E1000_ICR_THS 0x00800000 /* ICR.THS: Thermal Sensor Event*/
759 #define E1000_ICR_MDDET 0x10000000 /* Malicious Driver Detect */
761 #define E1000_ITR_MASK 0x000FFFFF /* ITR value bitfield */
762 #define E1000_ITR_MULT 256 /* ITR mulitplier in nsec */
765 /* Extended Interrupt Cause Read */
766 #define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */
767 #define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */
768 #define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */
769 #define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */
770 #define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */
771 #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */
772 #define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */
773 #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */
774 #define E1000_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
775 #define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
777 #define E1000_TCPTIMER_KS 0x00000100 /* KickStart */
778 #define E1000_TCPTIMER_COUNT_ENABLE 0x00000200 /* Count Enable */
779 #define E1000_TCPTIMER_COUNT_FINISH 0x00000400 /* Count finish */
780 #define E1000_TCPTIMER_LOOP 0x00000800 /* Loop */
783 * This defines the bits that are set in the Interrupt Mask
784 * Set/Read Register. Each bit is documented below:
785 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
786 * o RXSEQ = Receive Sequence Error
788 #define POLL_IMS_ENABLE_MASK ( \
793 * This defines the bits that are set in the Interrupt Mask
794 * Set/Read Register. Each bit is documented below:
795 * o RXT0 = Receiver Timer Interrupt (ring 0)
796 * o TXDW = Transmit Descriptor Written Back
797 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
798 * o RXSEQ = Receive Sequence Error
799 * o LSC = Link Status Change
801 #define IMS_ENABLE_MASK ( \
808 /* Interrupt Mask Set */
809 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Tx desc written back */
810 #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
811 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
812 #define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */
813 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
814 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
815 #define E1000_IMS_RXO E1000_ICR_RXO /* Rx overrun */
816 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */
817 #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
818 #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */
819 #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
820 #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
821 #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
822 #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
823 #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
824 #define E1000_IMS_SRPD E1000_ICR_SRPD
825 #define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */
826 #define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */
827 #define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */
828 #define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */
829 /* Q0 Rx desc FIFO parity error */
830 #define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0
831 /* Q0 Tx desc FIFO parity error */
832 #define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0
833 /* host arb read buffer parity error */
834 #define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR
835 /* packet buffer parity error */
836 #define E1000_IMS_PB_PAR E1000_ICR_PB_PAR
837 /* Q1 Rx desc FIFO parity error */
838 #define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1
839 /* Q1 Tx desc FIFO parity error */
840 #define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1
841 #define E1000_IMS_DSW E1000_ICR_DSW
842 #define E1000_IMS_PHYINT E1000_ICR_PHYINT
843 #define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
844 #define E1000_IMS_EPRST E1000_ICR_EPRST
845 #define E1000_IMS_FER E1000_ICR_FER /* Fatal Error */
847 #define E1000_IMS_THS E1000_ICR_THS /* ICR.TS: Thermal Sensor Event*/
848 #define E1000_IMS_MDDET E1000_ICR_MDDET /* Malicious Driver Detect */
849 /* Extended Interrupt Mask Set */
850 #define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
851 #define E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
852 #define E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
853 #define E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
854 #define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
855 #define E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
856 #define E1000_EIMS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
857 #define E1000_EIMS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
858 #define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */
859 #define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */
861 /* Interrupt Cause Set */
862 #define E1000_ICS_TXDW E1000_ICR_TXDW /* Tx desc written back */
863 #define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
864 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
865 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
866 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
867 #define E1000_ICS_RXO E1000_ICR_RXO /* Rx overrun */
868 #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */
869 #define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
870 #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */
871 #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
872 #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
873 #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
874 #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
875 #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
876 #define E1000_ICS_SRPD E1000_ICR_SRPD
877 #define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */
878 #define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */
879 #define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */
880 #define E1000_ICS_DRSTA E1000_ICR_DRSTA /* Device Reset Aserted */
881 /* Q0 Rx desc FIFO parity error */
882 #define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0
883 /* Q0 Tx desc FIFO parity error */
884 #define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0
885 /* host arb read buffer parity error */
886 #define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR
887 /* packet buffer parity error */
888 #define E1000_ICS_PB_PAR E1000_ICR_PB_PAR
889 /* Q1 Rx desc FIFO parity error */
890 #define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1
891 /* Q1 Tx desc FIFO parity error */
892 #define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1
893 #define E1000_ICS_DSW E1000_ICR_DSW
894 #define E1000_ICS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
895 #define E1000_ICS_PHYINT E1000_ICR_PHYINT
896 #define E1000_ICS_EPRST E1000_ICR_EPRST
898 /* Extended Interrupt Cause Set */
899 #define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
900 #define E1000_EICS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
901 #define E1000_EICS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
902 #define E1000_EICS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
903 #define E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
904 #define E1000_EICS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
905 #define E1000_EICS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
906 #define E1000_EICS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
907 #define E1000_EICS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */
908 #define E1000_EICS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */
910 #define E1000_EITR_ITR_INT_MASK 0x0000FFFF
911 /* E1000_EITR_CNT_IGNR is only for 82576 and newer */
912 #define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */
914 /* Transmit Descriptor Control */
915 #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
916 #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
917 #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
918 #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
919 #define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
920 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
921 #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
922 /* Enable the counting of descriptors still to be processed. */
923 #define E1000_TXDCTL_COUNT_DESC 0x00400000
925 /* Flow Control Constants */
926 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
927 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
928 #define FLOW_CONTROL_TYPE 0x8808
930 /* 802.1q VLAN Packet Size */
931 #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */
932 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
934 /* Receive Address */
936 * Number of high/low register pairs in the RAR. The RAR (Receive Address
937 * Registers) holds the directed and multicast addresses that we monitor.
938 * Technically, we have 16 spots. However, we reserve one of these spots
939 * (RAR[15]) for our directed address used by controllers with
940 * manageability enabled, allowing us room for 15 multicast addresses.
942 #define E1000_RAR_ENTRIES 15
943 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
944 #define E1000_RAL_MAC_ADDR_LEN 4
945 #define E1000_RAH_MAC_ADDR_LEN 2
946 #define E1000_RAH_QUEUE_MASK_82575 0x000C0000
947 #define E1000_RAH_POOL_MASK 0x03FC0000
948 #define E1000_RAH_POOL_SHIFT 18
949 #define E1000_RAH_POOL_1 0x00040000
952 #define E1000_SUCCESS 0
953 #define E1000_ERR_NVM 1
954 #define E1000_ERR_PHY 2
955 #define E1000_ERR_CONFIG 3
956 #define E1000_ERR_PARAM 4
957 #define E1000_ERR_MAC_INIT 5
958 #define E1000_ERR_PHY_TYPE 6
959 #define E1000_ERR_RESET 9
960 #define E1000_ERR_MASTER_REQUESTS_PENDING 10
961 #define E1000_ERR_HOST_INTERFACE_COMMAND 11
962 #define E1000_BLK_PHY_RESET 12
963 #define E1000_ERR_SWFW_SYNC 13
964 #define E1000_NOT_IMPLEMENTED 14
965 #define E1000_ERR_MBX 15
966 #define E1000_ERR_INVALID_ARGUMENT 16
967 #define E1000_ERR_NO_SPACE 17
968 #define E1000_ERR_NVM_PBA_SECTION 18
969 #define E1000_ERR_I2C 19
970 #define E1000_ERR_INVM_VALUE_NOT_FOUND 20
972 /* Loop limit on how long we wait for auto-negotiation to complete */
973 #define FIBER_LINK_UP_LIMIT 50
974 #define COPPER_LINK_UP_LIMIT 10
975 #define PHY_AUTO_NEG_LIMIT 45
976 #define PHY_FORCE_LIMIT 20
977 /* Number of 100 microseconds we wait for PCI Express master disable */
978 #define MASTER_DISABLE_TIMEOUT 800
979 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
980 #define PHY_CFG_TIMEOUT 100
981 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
982 #define MDIO_OWNERSHIP_TIMEOUT 10
983 /* Number of milliseconds for NVM auto read done after MAC reset. */
984 #define AUTO_READ_DONE_TIMEOUT 10
987 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
988 #define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
989 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
990 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
992 /* Transmit Configuration Word */
993 #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
994 #define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
995 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
996 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
997 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
998 #define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
999 #define E1000_TXCW_NP 0x00008000 /* TXCW next page */
1000 #define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
1001 #define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
1002 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
1004 /* Receive Configuration Word */
1005 #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
1006 #define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
1007 #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
1008 #define E1000_RXCW_CC 0x10000000 /* Receive config change */
1009 #define E1000_RXCW_C 0x20000000 /* Receive config */
1010 #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
1011 #define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
1013 #define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */
1014 #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */
1016 #define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */
1017 #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
1018 #define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00
1019 #define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02
1020 #define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
1021 #define E1000_TSYNCRXCTL_TYPE_ALL 0x08
1022 #define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
1023 #define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */
1025 #define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF
1026 #define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00
1027 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01
1028 #define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02
1029 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03
1030 #define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04
1032 #define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00
1033 #define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000
1034 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100
1035 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200
1036 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300
1037 #define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800
1038 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900
1039 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00
1040 #define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00
1041 #define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00
1042 #define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00
1044 #define E1000_TIMINCA_16NS_SHIFT 24
1045 /* TUPLE Filtering Configuration */
1046 #define E1000_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */
1047 #define E1000_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */
1048 #define E1000_TTQF_PROTOCOL_MASK 0xFF /* TTQF Protocol Mask */
1049 /* TTQF TCP Bit, shift with E1000_TTQF_PROTOCOL SHIFT */
1050 #define E1000_TTQF_PROTOCOL_TCP 0x0
1051 /* TTQF UDP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
1052 #define E1000_TTQF_PROTOCOL_UDP 0x1
1053 /* TTQF SCTP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
1054 #define E1000_TTQF_PROTOCOL_SCTP 0x2
1055 #define E1000_TTQF_PROTOCOL_SHIFT 5 /* TTQF Protocol Shift */
1056 #define E1000_TTQF_QUEUE_SHIFT 16 /* TTQF Queue Shfit */
1057 #define E1000_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */
1058 #define E1000_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */
1059 #define E1000_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */
1060 #define E1000_IMIR_PORT_BYPASS 0x20000 /* IMIR Port Bypass Bit */
1061 #define E1000_IMIR_PRIORITY_SHIFT 29 /* IMIR Priority Shift */
1062 #define E1000_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */
1064 #define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */
1065 #define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */
1066 #define E1000_MDICNFG_PHY_MASK 0x03E00000
1067 #define E1000_MDICNFG_PHY_SHIFT 21
1069 #define E1000_THSTAT_LOW_EVENT 0x20000000 /* Low thermal threshold */
1070 #define E1000_THSTAT_MID_EVENT 0x00200000 /* Mid thermal threshold */
1071 #define E1000_THSTAT_HIGH_EVENT 0x00002000 /* High thermal threshold */
1072 #define E1000_THSTAT_PWR_DOWN 0x00000001 /* Power Down Event */
1073 #define E1000_THSTAT_LINK_THROTTLE 0x00000002 /* Link Spd Throttle Event */
1075 /* I350 EEE defines */
1076 #define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */
1077 #define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */
1078 #define E1000_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */
1079 #define E1000_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */
1080 #define E1000_EEER_LPI_FC 0x00040000 /* EEER Ena on Flow Cntrl */
1082 #define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */
1083 #define E1000_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */
1084 #define E1000_EEER_TX_LPI_STATUS 0x80000000 /* Tx in LPI state */
1086 /* PCI Express Control */
1087 #define E1000_GCR_RXD_NO_SNOOP 0x00000001
1088 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
1089 #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
1090 #define E1000_GCR_TXD_NO_SNOOP 0x00000008
1091 #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
1092 #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
1093 #define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000
1094 #define E1000_GCR_CMPL_TMOUT_10ms 0x00001000
1095 #define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000
1096 #define E1000_GCR_CAP_VER2 0x00040000
1098 #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
1099 E1000_GCR_RXDSCW_NO_SNOOP | \
1100 E1000_GCR_RXDSCR_NO_SNOOP | \
1101 E1000_GCR_TXD_NO_SNOOP | \
1102 E1000_GCR_TXDSCW_NO_SNOOP | \
1103 E1000_GCR_TXDSCR_NO_SNOOP)
1105 /* mPHY address control and data registers */
1106 #define E1000_MPHY_ADDR_CTL 0x0024 /* Address Control Reg */
1107 #define E1000_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000
1108 #define E1000_MPHY_DATA 0x0E10 /* Data Register */
1110 /* AFE CSR Offset for PCS CLK */
1111 #define E1000_MPHY_PCS_CLK_REG_OFFSET 0x0004
1112 /* Override for near end digital loopback. */
1113 #define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10
1115 /* PHY Control Register */
1116 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
1117 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
1118 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
1119 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
1120 #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
1121 #define MII_CR_POWER_DOWN 0x0800 /* Power down */
1122 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
1123 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
1124 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
1125 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
1126 #define MII_CR_SPEED_1000 0x0040
1127 #define MII_CR_SPEED_100 0x2000
1128 #define MII_CR_SPEED_10 0x0000
1130 /* PHY Status Register */
1131 #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
1132 #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
1133 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
1134 #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
1135 #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
1136 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
1137 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
1138 #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
1139 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
1140 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
1141 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
1142 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
1143 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
1144 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
1145 #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
1147 /* Autoneg Advertisement Register */
1148 #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
1149 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
1150 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
1151 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
1152 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
1153 #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
1154 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
1155 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
1156 #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
1157 #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
1159 /* Link Partner Ability Register (Base Page) */
1160 #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
1161 #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP 10T Half Dplx Capable */
1162 #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP 10T Full Dplx Capable */
1163 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP 100TX Half Dplx Capable */
1164 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP 100TX Full Dplx Capable */
1165 #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
1166 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
1167 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asym Pause Direction bit */
1168 #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP detected Remote Fault */
1169 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP rx'd link code word */
1170 #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
1172 /* Autoneg Expansion Register */
1173 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
1174 #define NWAY_ER_PAGE_RXD 0x0002 /* LP 10T Half Dplx Capable */
1175 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP 10T Full Dplx Capable */
1176 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP 100TX Half Dplx Capable */
1177 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP 100TX Full Dplx Capable */
1179 /* 1000BASE-T Control Register */
1180 #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
1181 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
1182 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
1183 /* 1=Repeater/switch device port 0=DTE device */
1184 #define CR_1000T_REPEATER_DTE 0x0400
1185 /* 1=Configure PHY as Master 0=Configure PHY as Slave */
1186 #define CR_1000T_MS_VALUE 0x0800
1187 /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */
1188 #define CR_1000T_MS_ENABLE 0x1000
1189 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
1190 #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
1191 #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
1192 #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
1193 #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
1195 /* 1000BASE-T Status Register */
1196 #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle err since last rd */
1197 #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asym pause direction bit */
1198 #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
1199 #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
1200 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
1201 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
1202 #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx Master, 0=Slave */
1203 #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
1205 #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
1207 /* PHY 1000 MII Register/Bit Definitions */
1208 /* PHY Registers defined by IEEE */
1209 #define PHY_CONTROL 0x00 /* Control Register */
1210 #define PHY_STATUS 0x01 /* Status Register */
1211 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
1212 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
1213 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
1214 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
1215 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
1216 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */
1217 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
1218 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1219 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1220 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
1222 #define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */
1225 #define E1000_EECD_SK 0x00000001 /* NVM Clock */
1226 #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */
1227 #define E1000_EECD_DI 0x00000004 /* NVM Data In */
1228 #define E1000_EECD_DO 0x00000008 /* NVM Data Out */
1229 #define E1000_EECD_FWE_MASK 0x00000030
1230 #define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
1231 #define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
1232 #define E1000_EECD_FWE_SHIFT 4
1233 #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */
1234 #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */
1235 #define E1000_EECD_PRES 0x00000100 /* NVM Present */
1236 #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */
1237 #define E1000_EECD_BLOCKED 0x00008000 /* Bit banging access blocked flag */
1238 #define E1000_EECD_ABORT 0x00010000 /* NVM operation aborted flag */
1239 #define E1000_EECD_TIMEOUT 0x00020000 /* NVM read operation timeout flag */
1240 #define E1000_EECD_ERROR_CLR 0x00040000 /* NVM error status clear bit */
1241 /* NVM Addressing bits based on type 0=small, 1=large */
1242 #define E1000_EECD_ADDR_BITS 0x00000400
1243 #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
1244 #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
1245 #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
1246 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
1247 #define E1000_EECD_SIZE_EX_SHIFT 11
1248 #define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
1249 #define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
1250 #define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
1251 #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
1252 #define E1000_EECD_AUPDEN 0x00100000 /* Ena Auto FLASH update */
1253 #define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
1254 #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
1255 #define E1000_EECD_SECVAL_SHIFT 22
1256 #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
1258 #define E1000_NVM_SWDPIN0 0x0001 /* SWDPIN 0 NVM Value */
1259 #define E1000_NVM_LED_LOGIC 0x0020 /* Led Logic Word */
1260 #define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write regs */
1261 #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
1262 #define E1000_NVM_RW_REG_START 1 /* Start operation */
1263 #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1264 #define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */
1265 #define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */
1266 #define E1000_FLASH_UPDATES 2000
1268 /* NVM Word Offsets */
1269 #define NVM_COMPAT 0x0003
1270 #define NVM_ID_LED_SETTINGS 0x0004
1271 #define NVM_VERSION 0x0005
1272 #define NVM_SERDES_AMPLITUDE 0x0006 /* SERDES output amplitude */
1273 #define NVM_PHY_CLASS_WORD 0x0007
1275 #define NVM_ETS_CFG 0x003E
1276 #define NVM_ETS_LTHRES_DELTA_MASK 0x07C0
1277 #define NVM_ETS_LTHRES_DELTA_SHIFT 6
1278 #define NVM_ETS_TYPE_MASK 0x0038
1279 #define NVM_ETS_TYPE_SHIFT 3
1280 #define NVM_ETS_TYPE_EMC 0x000
1281 #define NVM_ETS_NUM_SENSORS_MASK 0x0007
1282 #define NVM_ETS_DATA_LOC_MASK 0x3C00
1283 #define NVM_ETS_DATA_LOC_SHIFT 10
1284 #define NVM_ETS_DATA_INDEX_MASK 0x0300
1285 #define NVM_ETS_DATA_INDEX_SHIFT 8
1286 #define NVM_ETS_DATA_HTHRESH_MASK 0x00FF
1287 #define NVM_INIT_CONTROL1_REG 0x000A
1288 #define NVM_INIT_CONTROL2_REG 0x000F
1289 #define NVM_SWDEF_PINS_CTRL_PORT_1 0x0010
1290 #define NVM_INIT_CONTROL3_PORT_B 0x0014
1291 #define NVM_INIT_3GIO_3 0x001A
1292 #define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020
1293 #define NVM_INIT_CONTROL3_PORT_A 0x0024
1294 #define NVM_CFG 0x0012
1295 #define NVM_FLASH_VERSION 0x0032
1296 #define NVM_ALT_MAC_ADDR_PTR 0x0037
1297 #define NVM_CHECKSUM_REG 0x003F
1298 #define NVM_COMPATIBILITY_REG_3 0x0003
1299 #define NVM_COMPATIBILITY_BIT_MASK 0x8000
1301 #define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */
1302 #define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */
1303 #define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */
1304 #define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */
1306 #define NVM_82580_LAN_FUNC_OFFSET(a) ((a) ? (0x40 + (0x40 * (a))) : 0)
1308 /* Mask bits for fields in Word 0x24 of the NVM */
1309 #define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */
1310 #define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed extrnl */
1311 /* Offset of Link Mode bits for 82575/82576 */
1312 #define NVM_WORD24_LNK_MODE_OFFSET 8
1313 /* Offset of Link Mode bits for 82580 up */
1314 #define NVM_WORD24_82580_LNK_MODE_OFFSET 4
1317 /* Mask bits for fields in Word 0x0f of the NVM */
1318 #define NVM_WORD0F_PAUSE_MASK 0x3000
1319 #define NVM_WORD0F_PAUSE 0x1000
1320 #define NVM_WORD0F_ASM_DIR 0x2000
1321 #define NVM_WORD0F_ANE 0x0800
1322 #define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0
1323 #define NVM_WORD0F_LPLU 0x0001
1325 /* Mask bits for fields in Word 0x1a of the NVM */
1326 #define NVM_WORD1A_ASPM_MASK 0x000C
1328 /* Mask bits for fields in Word 0x03 of the EEPROM */
1329 #define NVM_COMPAT_LOM 0x0800
1331 /* length of string needed to store PBA number */
1332 #define E1000_PBANUM_LENGTH 11
1334 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
1335 #define NVM_SUM 0xBABA
1337 #define NVM_MAC_ADDR_OFFSET 0
1338 #define NVM_PBA_OFFSET_0 8
1339 #define NVM_PBA_OFFSET_1 9
1340 #define NVM_PBA_PTR_GUARD 0xFAFA
1341 #define NVM_RESERVED_WORD 0xFFFF
1342 #define NVM_PHY_CLASS_A 0x8000
1343 #define NVM_SERDES_AMPLITUDE_MASK 0x000F
1344 #define NVM_SIZE_MASK 0x1C00
1345 #define NVM_SIZE_SHIFT 10
1346 #define NVM_WORD_SIZE_BASE_SHIFT 6
1347 #define NVM_SWDPIO_EXT_SHIFT 4
1349 /* NVM Commands - SPI */
1350 #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
1351 #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */
1352 #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */
1353 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1354 #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */
1355 #define NVM_WRDI_OPCODE_SPI 0x04 /* NVM reset Write Enable latch */
1356 #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */
1357 #define NVM_WRSR_OPCODE_SPI 0x01 /* NVM write Status register */
1359 /* SPI NVM Status Register */
1360 #define NVM_STATUS_RDY_SPI 0x01
1361 #define NVM_STATUS_WEN_SPI 0x02
1362 #define NVM_STATUS_BP0_SPI 0x04
1363 #define NVM_STATUS_BP1_SPI 0x08
1364 #define NVM_STATUS_WPEN_SPI 0x80
1366 /* Word definitions for ID LED Settings */
1367 #define ID_LED_RESERVED_0000 0x0000
1368 #define ID_LED_RESERVED_FFFF 0xFFFF
1369 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
1370 (ID_LED_OFF1_OFF2 << 8) | \
1371 (ID_LED_DEF1_DEF2 << 4) | \
1373 #define ID_LED_DEF1_DEF2 0x1
1374 #define ID_LED_DEF1_ON2 0x2
1375 #define ID_LED_DEF1_OFF2 0x3
1376 #define ID_LED_ON1_DEF2 0x4
1377 #define ID_LED_ON1_ON2 0x5
1378 #define ID_LED_ON1_OFF2 0x6
1379 #define ID_LED_OFF1_DEF2 0x7
1380 #define ID_LED_OFF1_ON2 0x8
1381 #define ID_LED_OFF1_OFF2 0x9
1383 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
1384 #define IGP_ACTIVITY_LED_ENABLE 0x0300
1385 #define IGP_LED3_MODE 0x07000000
1387 /* PCI/PCI-X/PCI-EX Config space */
1388 #define PCI_HEADER_TYPE_REGISTER 0x0E
1389 #define PCIE_LINK_STATUS 0x12
1390 #define PCIE_DEVICE_CONTROL2 0x28
1392 #define PCI_HEADER_TYPE_MULTIFUNC 0x80
1393 #define PCIE_LINK_WIDTH_MASK 0x3F0
1394 #define PCIE_LINK_WIDTH_SHIFT 4
1395 #define PCIE_LINK_SPEED_MASK 0x0F
1396 #define PCIE_LINK_SPEED_2500 0x01
1397 #define PCIE_LINK_SPEED_5000 0x02
1398 #define PCIE_DEVICE_CONTROL2_16ms 0x0005
1400 #ifndef ETH_ADDR_LEN
1401 #define ETH_ADDR_LEN 6
1404 #define PHY_REVISION_MASK 0xFFFFFFF0
1405 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1406 #define MAX_PHY_MULTI_PAGE_REG 0xF
1408 /* Bit definitions for valid PHY IDs. */
1413 #define M88E1000_E_PHY_ID 0x01410C50
1414 #define M88E1000_I_PHY_ID 0x01410C30
1415 #define M88E1011_I_PHY_ID 0x01410C20
1416 #define IGP01E1000_I_PHY_ID 0x02A80380
1417 #define M88E1011_I_REV_4 0x04
1418 #define M88E1111_I_PHY_ID 0x01410CC0
1419 #define M88E1112_E_PHY_ID 0x01410C90
1420 #define I347AT4_E_PHY_ID 0x01410DC0
1421 #define M88E1340M_E_PHY_ID 0x01410DF0
1422 #define GG82563_E_PHY_ID 0x01410CA0
1423 #define IGP03E1000_E_PHY_ID 0x02A80390
1424 #define IFE_E_PHY_ID 0x02A80330
1425 #define IFE_PLUS_E_PHY_ID 0x02A80320
1426 #define IFE_C_E_PHY_ID 0x02A80310
1427 #define I82580_I_PHY_ID 0x015403A0
1428 #define I350_I_PHY_ID 0x015403B0
1429 #define IGP04E1000_E_PHY_ID 0x02A80391
1430 #define M88_VENDOR 0x0141
1432 /* M88E1000 Specific Registers */
1433 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Reg */
1434 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Reg */
1435 #define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Reg */
1436 #define M88E1000_INT_STATUS 0x13 /* Interrupt Status Reg */
1437 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Cntrl */
1438 #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
1440 #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
1441 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for pg number setting */
1442 #define M88E1000_PHY_GEN_CONTROL 0x1E /* meaning depends on reg 29 */
1443 #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
1444 #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
1446 /* M88E1000 PHY Specific Control Register */
1447 #define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
1448 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */
1449 #define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
1450 /* 1=CLK125 low, 0=CLK125 toggling */
1451 #define M88E1000_PSCR_CLK125_DISABLE 0x0010
1452 /* MDI Crossover Mode bits 6:5 Manual MDI configuration */
1453 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000
1454 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
1455 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1456 #define M88E1000_PSCR_AUTO_X_1000T 0x0040
1457 /* Auto crossover enabled all speeds */
1458 #define M88E1000_PSCR_AUTO_X_MODE 0x0060
1460 * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
1461 * 0=Normal 10BASE-T Rx Threshold
1463 #define M88E1000_PSCR_EN_10BT_EXT_DIST 0x0080
1464 /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
1465 #define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
1466 #define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
1467 #define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
1468 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */
1470 /* M88E1000 PHY Specific Status Register */
1471 #define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
1472 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
1473 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
1474 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
1482 #define M88E1000_PSSR_CABLE_LENGTH 0x0380
1483 #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
1484 #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
1485 #define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
1486 #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
1487 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
1488 #define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
1489 #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
1490 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
1492 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
1494 /* M88E1000 Extended PHY Specific Control Register */
1495 #define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
1497 * 1 = Lost lock detect enabled.
1498 * Will assert lost lock and bring
1499 * link down if idle not seen
1500 * within 1ms in 1000BASE-T
1502 #define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000
1504 * Number of times we will attempt to autonegotiate before downshifting if we
1507 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
1508 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
1509 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
1510 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
1511 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
1513 * Number of times we will attempt to autonegotiate before downshifting if we
1516 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
1517 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
1518 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
1519 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
1520 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
1521 #define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
1522 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
1523 #define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
1525 /* M88E1111 Specific Registers */
1526 #define M88E1111_PHY_PAGE_SELECT1 0x16 /* for registers 0-28 */
1527 #define M88E1111_PHY_PAGE_SELECT2 0x1D /* for registers 30-31 */
1529 /* M88E1111 page select register mask */
1530 #define M88E1111_PHY_PAGE_SELECT_MASK1 0xFF
1531 #define M88E1111_PHY_PAGE_SELECT_MASK2 0x3F
1533 /* Intel I347AT4 Registers */
1535 #define I347AT4_PCDL 0x10 /* PHY Cable Diagnostics Length */
1536 #define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */
1537 #define I347AT4_PAGE_SELECT 0x16
1539 /* I347AT4 Extended PHY Specific Control Register */
1542 * Number of times we will attempt to autonegotiate before downshifting if we
1545 #define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800
1546 #define I347AT4_PSCR_DOWNSHIFT_MASK 0x7000
1547 #define I347AT4_PSCR_DOWNSHIFT_1X 0x0000
1548 #define I347AT4_PSCR_DOWNSHIFT_2X 0x1000
1549 #define I347AT4_PSCR_DOWNSHIFT_3X 0x2000
1550 #define I347AT4_PSCR_DOWNSHIFT_4X 0x3000
1551 #define I347AT4_PSCR_DOWNSHIFT_5X 0x4000
1552 #define I347AT4_PSCR_DOWNSHIFT_6X 0x5000
1553 #define I347AT4_PSCR_DOWNSHIFT_7X 0x6000
1554 #define I347AT4_PSCR_DOWNSHIFT_8X 0x7000
1556 /* I347AT4 PHY Cable Diagnostics Control */
1557 #define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400 /* 0=cm 1=meters */
1559 /* M88E1112 only registers */
1560 #define M88E1112_VCT_DSP_DISTANCE 0x001A
1562 /* M88EC018 Rev 2 specific DownShift settings */
1563 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
1564 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000
1565 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
1566 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
1567 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
1568 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
1569 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
1570 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
1571 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
1576 * 4-0: register offset
1578 #define GG82563_PAGE_SHIFT 5
1579 #define GG82563_REG(page, reg) \
1580 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
1581 #define GG82563_MIN_ALT_REG 30
1583 /* GG82563 Specific Registers */
1584 #define GG82563_PHY_SPEC_CTRL GG82563_REG(0, 16) /* PHY Spec Cntrl */
1585 #define GG82563_PHY_SPEC_STATUS GG82563_REG(0, 17) /* PHY Spec Status */
1586 #define GG82563_PHY_INT_ENABLE GG82563_REG(0, 18) /* Interrupt Ena */
1587 #define GG82563_PHY_SPEC_STATUS_2 GG82563_REG(0, 19) /* PHY Spec Stat2 */
1588 #define GG82563_PHY_RX_ERR_CNTR GG82563_REG(0, 21) /* Rx Err Counter */
1589 #define GG82563_PHY_PAGE_SELECT GG82563_REG(0, 22) /* Page Select */
1590 #define GG82563_PHY_SPEC_CTRL_2 GG82563_REG(0, 26) /* PHY Spec Cntrl2 */
1591 #define GG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) /* Alt Page Select */
1592 /* Test Clock Control (use reg. 29 to select) */
1593 #define GG82563_PHY_TEST_CLK_CTRL GG82563_REG(0, 30)
1595 /* MAC Specific Control Register */
1596 #define GG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21)
1597 #define GG82563_PHY_MAC_SPEC_CTRL_2 GG82563_REG(2, 26) /* MAC Spec Ctrl 2 */
1599 #define GG82563_PHY_DSP_DISTANCE GG82563_REG(5, 26) /* DSP Distance */
1601 /* Page 193 - Port Control Registers */
1602 /* Kumeran Mode Control */
1603 #define GG82563_PHY_KMRN_MODE_CTRL GG82563_REG(193, 16)
1604 #define GG82563_PHY_PORT_RESET GG82563_REG(193, 17) /* Port Reset */
1605 #define GG82563_PHY_REVISION_ID GG82563_REG(193, 18) /* Revision ID */
1606 #define GG82563_PHY_DEVICE_ID GG82563_REG(193, 19) /* Device ID */
1607 #define GG82563_PHY_PWR_MGMT_CTRL GG82563_REG(193, 20) /* Pwr Mgt Ctrl */
1608 /* Rate Adaptation Control */
1609 #define GG82563_PHY_RATE_ADAPT_CTRL GG82563_REG(193, 25)
1611 /* Page 194 - KMRN Registers */
1612 /* FIFO's Control/Status */
1613 #define GG82563_PHY_KMRN_FIFO_CTRL_STAT GG82563_REG(194, 16)
1614 #define GG82563_PHY_KMRN_CTRL GG82563_REG(194, 17) /* Control */
1615 #define GG82563_PHY_INBAND_CTRL GG82563_REG(194, 18) /* Inband Ctrl */
1616 #define GG82563_PHY_KMRN_DIAGNOSTIC GG82563_REG(194, 19) /* Diagnostic */
1617 #define GG82563_PHY_ACK_TIMEOUTS GG82563_REG(194, 20) /* Ack Timeouts */
1618 #define GG82563_PHY_ADV_ABILITY GG82563_REG(194, 21) /* Adver Ability */
1619 /* Link Partner Advertised Ability */
1620 #define GG82563_PHY_LINK_PARTNER_ADV_ABILITY GG82563_REG(194, 23)
1621 #define GG82563_PHY_ADV_NEXT_PAGE GG82563_REG(194, 24) /* Adver Next Pg */
1622 /* Link Partner Advertised Next page */
1623 #define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE GG82563_REG(194, 25)
1624 #define GG82563_PHY_KMRN_MISC GG82563_REG(194, 26) /* Misc. */
1627 #define E1000_MDIC_DATA_MASK 0x0000FFFF
1628 #define E1000_MDIC_REG_MASK 0x001F0000
1629 #define E1000_MDIC_REG_SHIFT 16
1630 #define E1000_MDIC_PHY_MASK 0x03E00000
1631 #define E1000_MDIC_PHY_SHIFT 21
1632 #define E1000_MDIC_OP_WRITE 0x04000000
1633 #define E1000_MDIC_OP_READ 0x08000000
1634 #define E1000_MDIC_READY 0x10000000
1635 #define E1000_MDIC_INT_EN 0x20000000
1636 #define E1000_MDIC_ERROR 0x40000000
1637 #define E1000_MDIC_DEST 0x80000000
1639 /* SerDes Control */
1640 #define E1000_GEN_CTL_READY 0x80000000
1641 #define E1000_GEN_CTL_ADDRESS_SHIFT 8
1642 #define E1000_GEN_POLL_TIMEOUT 640
1644 /* LinkSec register fields */
1645 #define E1000_LSECTXCAP_SUM_MASK 0x00FF0000
1646 #define E1000_LSECTXCAP_SUM_SHIFT 16
1647 #define E1000_LSECRXCAP_SUM_MASK 0x00FF0000
1648 #define E1000_LSECRXCAP_SUM_SHIFT 16
1650 #define E1000_LSECTXCTRL_EN_MASK 0x00000003
1651 #define E1000_LSECTXCTRL_DISABLE 0x0
1652 #define E1000_LSECTXCTRL_AUTH 0x1
1653 #define E1000_LSECTXCTRL_AUTH_ENCRYPT 0x2
1654 #define E1000_LSECTXCTRL_AISCI 0x00000020
1655 #define E1000_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00
1656 #define E1000_LSECTXCTRL_RSV_MASK 0x000000D8
1658 #define E1000_LSECRXCTRL_EN_MASK 0x0000000C
1659 #define E1000_LSECRXCTRL_EN_SHIFT 2
1660 #define E1000_LSECRXCTRL_DISABLE 0x0
1661 #define E1000_LSECRXCTRL_CHECK 0x1
1662 #define E1000_LSECRXCTRL_STRICT 0x2
1663 #define E1000_LSECRXCTRL_DROP 0x3
1664 #define E1000_LSECRXCTRL_PLSH 0x00000040
1665 #define E1000_LSECRXCTRL_RP 0x00000080
1666 #define E1000_LSECRXCTRL_RSV_MASK 0xFFFFFF33
1668 /* Tx Rate-Scheduler Config fields */
1669 #define E1000_RTTBCNRC_RS_ENA 0x80000000
1670 #define E1000_RTTBCNRC_RF_DEC_MASK 0x00003FFF
1671 #define E1000_RTTBCNRC_RF_INT_SHIFT 14
1672 #define E1000_RTTBCNRC_RF_INT_MASK \
1673 (E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT)
1675 /* DMA Coalescing register fields */
1676 /* DMA Coalescing Watchdog Timer */
1677 #define E1000_DMACR_DMACWT_MASK 0x00003FFF
1678 /* DMA Coalescing Rx Threshold */
1679 #define E1000_DMACR_DMACTHR_MASK 0x00FF0000
1680 #define E1000_DMACR_DMACTHR_SHIFT 16
1681 /* Lx when no PCIe transactions */
1682 #define E1000_DMACR_DMAC_LX_MASK 0x30000000
1683 #define E1000_DMACR_DMAC_LX_SHIFT 28
1684 #define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */
1685 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1686 #define E1000_DMACR_DC_BMC2OSW_EN 0x00008000
1688 /* DMA Coalescing Transmit Threshold */
1689 #define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF
1691 #define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */
1693 /* Rx Traffic Rate Threshold */
1694 #define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF
1695 /* Rx packet rate in current window */
1696 #define E1000_DMCRTRH_LRPRCW 0x80000000
1698 /* DMA Coal Rx Traffic Current Count */
1699 #define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF
1701 /* Flow ctrl Rx Threshold High val */
1702 #define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0
1703 #define E1000_FCRTC_RTH_COAL_SHIFT 4
1704 /* Lx power decision based on DMA coal */
1705 #define E1000_PCIEMISC_LX_DECISION 0x00000080
1707 /* Proxy Filer Control */
1708 #define E1000_PROXYFC_D0 0x00000001 /* Enable offload in D0 */
1709 #define E1000_PROXYFC_EX 0x00000004 /* Directed exact proxy */
1710 #define E1000_PROXYFC_MC 0x00000008 /* Directed MC Proxy */
1711 #define E1000_PROXYFC_BC 0x00000010 /* Broadcast Proxy Enable */
1712 #define E1000_PROXYFC_ARP_DIRECTED 0x00000020 /* Directed ARP Proxy Ena */
1713 #define E1000_PROXYFC_IPV4 0x00000040 /* Directed IPv4 Enable */
1714 #define E1000_PROXYFC_IPV6 0x00000080 /* Directed IPv6 Enable */
1715 #define E1000_PROXYFC_NS 0x00000200 /* IPv4 NBRHD Solicitation */
1716 #define E1000_PROXYFC_ARP 0x00000800 /* ARP Request Proxy Ena */
1718 #define E1000_PROXYS_CLEAR 0xFFFFFFFF /* Clear */
1720 /* Firmware Status */
1721 #define E1000_FWSTS_FWRI 0x80000000 /* FW Reset Indication */
1723 #define E1000_VTCTRL_RST 0x04000000 /* Reset VF */
1725 #define E1000_STATUS_LAN_ID_MASK 0x00000000C /* Mask for Lan ID field */
1726 /* Lan ID bit field offset in status register */
1727 #define E1000_STATUS_LAN_ID_OFFSET 2
1728 #define E1000_VFTA_ENTRIES 128
1729 #endif /* _E1000_DEFINES_H_ */