lib/librte_eal/linuxapp/kni/ethtool/igb/e1000_hw.h

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2012 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #ifndef _E1000_HW_H_
  29 #define _E1000_HW_H_
  30
  31 #include "e1000_osdep.h"
  32 #include "e1000_regs.h"
  33 #include "e1000_defines.h"
  34
  35 struct e1000_hw;
  36
  37 #define E1000_DEV_ID_82576                      0x10C9
  38 #define E1000_DEV_ID_82576_FIBER                0x10E6
  39 #define E1000_DEV_ID_82576_SERDES               0x10E7
  40 #define E1000_DEV_ID_82576_QUAD_COPPER          0x10E8
  41 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2      0x1526
  42 #define E1000_DEV_ID_82576_NS                   0x150A
  43 #define E1000_DEV_ID_82576_NS_SERDES            0x1518
  44 #define E1000_DEV_ID_82576_SERDES_QUAD          0x150D
  45 #define E1000_DEV_ID_82575EB_COPPER             0x10A7
  46 #define E1000_DEV_ID_82575EB_FIBER_SERDES       0x10A9
  47 #define E1000_DEV_ID_82575GB_QUAD_COPPER        0x10D6
  48 #define E1000_DEV_ID_82580_COPPER               0x150E
  49 #define E1000_DEV_ID_82580_FIBER                0x150F
  50 #define E1000_DEV_ID_82580_SERDES               0x1510
  51 #define E1000_DEV_ID_82580_SGMII                0x1511
  52 #define E1000_DEV_ID_82580_COPPER_DUAL          0x1516
  53 #define E1000_DEV_ID_82580_QUAD_FIBER           0x1527
  54 #define E1000_DEV_ID_I350_COPPER                0x1521
  55 #define E1000_DEV_ID_I350_FIBER                 0x1522
  56 #define E1000_DEV_ID_I350_SERDES                0x1523
  57 #define E1000_DEV_ID_I350_SGMII                 0x1524
  58 #define E1000_DEV_ID_I350_DA4                   0x1546
  59 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS       0x1F40
  60 #define E1000_DEV_ID_I354_SGMII                 0x1F41
  61 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS     0x1F45
  62 #define E1000_DEV_ID_DH89XXCC_SGMII             0x0438
  63 #define E1000_DEV_ID_DH89XXCC_SERDES            0x043A
  64 #define E1000_DEV_ID_DH89XXCC_BACKPLANE         0x043C
  65 #define E1000_DEV_ID_DH89XXCC_SFP               0x0440
  66 #define E1000_REVISION_0        0
  67 #define E1000_REVISION_1        1
  68 #define E1000_REVISION_2        2
  69 #define E1000_REVISION_3        3
  70 #define E1000_REVISION_4        4
  71
  72 #define E1000_FUNC_0            0
  73 #define E1000_FUNC_1            1
  74 #define E1000_FUNC_2            2
  75 #define E1000_FUNC_3            3
  76
  77 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0       0
  78 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1       3
  79 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2       6
  80 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3       9
  81
  82 enum e1000_mac_type {
  83         e1000_undefined = 0,
  84         e1000_82575,
  85         e1000_82576,
  86         e1000_82580,
  87         e1000_i350,
  88         e1000_i354,
  89         e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
  90 };
  91
  92 enum e1000_media_type {
  93         e1000_media_type_unknown = 0,
  94         e1000_media_type_copper = 1,
  95         e1000_media_type_fiber = 2,
  96         e1000_media_type_internal_serdes = 3,
  97         e1000_num_media_types
  98 };
  99
 100 enum e1000_nvm_type {
 101         e1000_nvm_unknown = 0,
 102         e1000_nvm_none,
 103         e1000_nvm_eeprom_spi,
 104         e1000_nvm_flash_hw,
 105         e1000_nvm_flash_sw
 106 };
 107
 108 enum e1000_nvm_override {
 109         e1000_nvm_override_none = 0,
 110         e1000_nvm_override_spi_small,
 111         e1000_nvm_override_spi_large,
 112 };
 113
 114 enum e1000_phy_type {
 115         e1000_phy_unknown = 0,
 116         e1000_phy_none,
 117         e1000_phy_m88,
 118         e1000_phy_igp,
 119         e1000_phy_igp_2,
 120         e1000_phy_gg82563,
 121         e1000_phy_igp_3,
 122         e1000_phy_ife,
 123         e1000_phy_82580,
 124         e1000_phy_vf,
 125 };
 126
 127 enum e1000_bus_type {
 128         e1000_bus_type_unknown = 0,
 129         e1000_bus_type_pci,
 130         e1000_bus_type_pcix,
 131         e1000_bus_type_pci_express,
 132         e1000_bus_type_reserved
 133 };
 134
 135 enum e1000_bus_speed {
 136         e1000_bus_speed_unknown = 0,
 137         e1000_bus_speed_33,
 138         e1000_bus_speed_66,
 139         e1000_bus_speed_100,
 140         e1000_bus_speed_120,
 141         e1000_bus_speed_133,
 142         e1000_bus_speed_2500,
 143         e1000_bus_speed_5000,
 144         e1000_bus_speed_reserved
 145 };
 146
 147 enum e1000_bus_width {
 148         e1000_bus_width_unknown = 0,
 149         e1000_bus_width_pcie_x1,
 150         e1000_bus_width_pcie_x2,
 151         e1000_bus_width_pcie_x4 = 4,
 152         e1000_bus_width_pcie_x8 = 8,
 153         e1000_bus_width_32,
 154         e1000_bus_width_64,
 155         e1000_bus_width_reserved
 156 };
 157
 158 enum e1000_1000t_rx_status {
 159         e1000_1000t_rx_status_not_ok = 0,
 160         e1000_1000t_rx_status_ok,
 161         e1000_1000t_rx_status_undefined = 0xFF
 162 };
 163
 164 enum e1000_rev_polarity {
 165         e1000_rev_polarity_normal = 0,
 166         e1000_rev_polarity_reversed,
 167         e1000_rev_polarity_undefined = 0xFF
 168 };
 169
 170 enum e1000_fc_mode {
 171         e1000_fc_none = 0,
 172         e1000_fc_rx_pause,
 173         e1000_fc_tx_pause,
 174         e1000_fc_full,
 175         e1000_fc_default = 0xFF
 176 };
 177
 178 enum e1000_ms_type {
 179         e1000_ms_hw_default = 0,
 180         e1000_ms_force_master,
 181         e1000_ms_force_slave,
 182         e1000_ms_auto
 183 };
 184
 185 enum e1000_smart_speed {
 186         e1000_smart_speed_default = 0,
 187         e1000_smart_speed_on,
 188         e1000_smart_speed_off
 189 };
 190
 191 enum e1000_serdes_link_state {
 192         e1000_serdes_link_down = 0,
 193         e1000_serdes_link_autoneg_progress,
 194         e1000_serdes_link_autoneg_complete,
 195         e1000_serdes_link_forced_up
 196 };
 197
 198 #ifndef __le16
 199 #define __le16 u16
 200 #endif
 201 #ifndef __le32
 202 #define __le32 u32
 203 #endif
 204 #ifndef __le64
 205 #define __le64 u64
 206 #endif
 207 /* Receive Descriptor */
 208 struct e1000_rx_desc {
 209         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 210         __le16 length;      /* Length of data DMAed into data buffer */
 211         __le16 csum; /* Packet checksum */
 212         u8  status;  /* Descriptor status */
 213         u8  errors;  /* Descriptor Errors */
 214         __le16 special;
 215 };
 216
 217 /* Receive Descriptor - Extended */
 218 union e1000_rx_desc_extended {
 219         struct {
 220                 __le64 buffer_addr;
 221                 __le64 reserved;
 222         } read;
 223         struct {
 224                 struct {
 225                         __le32 mrq; /* Multiple Rx Queues */
 226                         union {
 227                                 __le32 rss; /* RSS Hash */
 228                                 struct {
 229                                         __le16 ip_id;  /* IP id */
 230                                         __le16 csum;   /* Packet Checksum */
 231                                 } csum_ip;
 232                         } hi_dword;
 233                 } lower;
 234                 struct {
 235                         __le32 status_error;  /* ext status/error */
 236                         __le16 length;
 237                         __le16 vlan; /* VLAN tag */
 238                 } upper;
 239         } wb;  /* writeback */
 240 };
 241
 242 #define MAX_PS_BUFFERS 4
 243 /* Receive Descriptor - Packet Split */
 244 union e1000_rx_desc_packet_split {
 245         struct {
 246                 /* one buffer for protocol header(s), three data buffers */
 247                 __le64 buffer_addr[MAX_PS_BUFFERS];
 248         } read;
 249         struct {
 250                 struct {
 251                         __le32 mrq;  /* Multiple Rx Queues */
 252                         union {
 253                                 __le32 rss; /* RSS Hash */
 254                                 struct {
 255                                         __le16 ip_id;    /* IP id */
 256                                         __le16 csum;     /* Packet Checksum */
 257                                 } csum_ip;
 258                         } hi_dword;
 259                 } lower;
 260                 struct {
 261                         __le32 status_error;  /* ext status/error */
 262                         __le16 length0;  /* length of buffer 0 */
 263                         __le16 vlan;  /* VLAN tag */
 264                 } middle;
 265                 struct {
 266                         __le16 header_status;
 267                         __le16 length[3];     /* length of buffers 1-3 */
 268                 } upper;
 269                 __le64 reserved;
 270         } wb; /* writeback */
 271 };
 272
 273 /* Transmit Descriptor */
 274 struct e1000_tx_desc {
 275         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
 276         union {
 277                 __le32 data;
 278                 struct {
 279                         __le16 length;  /* Data buffer length */
 280                         u8 cso;  /* Checksum offset */
 281                         u8 cmd;  /* Descriptor control */
 282                 } flags;
 283         } lower;
 284         union {
 285                 __le32 data;
 286                 struct {
 287                         u8 status; /* Descriptor status */
 288                         u8 css;  /* Checksum start */
 289                         __le16 special;
 290                 } fields;
 291         } upper;
 292 };
 293
 294 /* Offload Context Descriptor */
 295 struct e1000_context_desc {
 296         union {
 297                 __le32 ip_config;
 298                 struct {
 299                         u8 ipcss;  /* IP checksum start */
 300                         u8 ipcso;  /* IP checksum offset */
 301                         __le16 ipcse;  /* IP checksum end */
 302                 } ip_fields;
 303         } lower_setup;
 304         union {
 305                 __le32 tcp_config;
 306                 struct {
 307                         u8 tucss;  /* TCP checksum start */
 308                         u8 tucso;  /* TCP checksum offset */
 309                         __le16 tucse;  /* TCP checksum end */
 310                 } tcp_fields;
 311         } upper_setup;
 312         __le32 cmd_and_length;
 313         union {
 314                 __le32 data;
 315                 struct {
 316                         u8 status;  /* Descriptor status */
 317                         u8 hdr_len;  /* Header length */
 318                         __le16 mss;  /* Maximum segment size */
 319                 } fields;
 320         } tcp_seg_setup;
 321 };
 322
 323 /* Offload data descriptor */
 324 struct e1000_data_desc {
 325         __le64 buffer_addr;  /* Address of the descriptor's buffer address */
 326         union {
 327                 __le32 data;
 328                 struct {
 329                         __le16 length;  /* Data buffer length */
 330                         u8 typ_len_ext;
 331                         u8 cmd;
 332                 } flags;
 333         } lower;
 334         union {
 335                 __le32 data;
 336                 struct {
 337                         u8 status;  /* Descriptor status */
 338                         u8 popts;  /* Packet Options */
 339                         __le16 special;
 340                 } fields;
 341         } upper;
 342 };
 343
 344 /* Statistics counters collected by the MAC */
 345 struct e1000_hw_stats {
 346         u64 crcerrs;
 347         u64 algnerrc;
 348         u64 symerrs;
 349         u64 rxerrc;
 350         u64 mpc;
 351         u64 scc;
 352         u64 ecol;
 353         u64 mcc;
 354         u64 latecol;
 355         u64 colc;
 356         u64 dc;
 357         u64 tncrs;
 358         u64 sec;
 359         u64 cexterr;
 360         u64 rlec;
 361         u64 xonrxc;
 362         u64 xontxc;
 363         u64 xoffrxc;
 364         u64 xofftxc;
 365         u64 fcruc;
 366         u64 prc64;
 367         u64 prc127;
 368         u64 prc255;
 369         u64 prc511;
 370         u64 prc1023;
 371         u64 prc1522;
 372         u64 gprc;
 373         u64 bprc;
 374         u64 mprc;
 375         u64 gptc;
 376         u64 gorc;
 377         u64 gotc;
 378         u64 rnbc;
 379         u64 ruc;
 380         u64 rfc;
 381         u64 roc;
 382         u64 rjc;
 383         u64 mgprc;
 384         u64 mgpdc;
 385         u64 mgptc;
 386         u64 tor;
 387         u64 tot;
 388         u64 tpr;
 389         u64 tpt;
 390         u64 ptc64;
 391         u64 ptc127;
 392         u64 ptc255;
 393         u64 ptc511;
 394         u64 ptc1023;
 395         u64 ptc1522;
 396         u64 mptc;
 397         u64 bptc;
 398         u64 tsctc;
 399         u64 tsctfc;
 400         u64 iac;
 401         u64 icrxptc;
 402         u64 icrxatc;
 403         u64 ictxptc;
 404         u64 ictxatc;
 405         u64 ictxqec;
 406         u64 ictxqmtc;
 407         u64 icrxdmtc;
 408         u64 icrxoc;
 409         u64 cbtmpc;
 410         u64 htdpmc;
 411         u64 cbrdpc;
 412         u64 cbrmpc;
 413         u64 rpthc;
 414         u64 hgptc;
 415         u64 htcbdpc;
 416         u64 hgorc;
 417         u64 hgotc;
 418         u64 lenerrs;
 419         u64 scvpc;
 420         u64 hrmpc;
 421         u64 doosync;
 422         u64 o2bgptc;
 423         u64 o2bspc;
 424         u64 b2ospc;
 425         u64 b2ogprc;
 426 };
 427
 428
 429 struct e1000_phy_stats {
 430         u32 idle_errors;
 431         u32 receive_errors;
 432 };
 433
 434 struct e1000_host_mng_dhcp_cookie {
 435         u32 signature;
 436         u8  status;
 437         u8  reserved0;
 438         u16 vlan_id;
 439         u32 reserved1;
 440         u16 reserved2;
 441         u8  reserved3;
 442         u8  checksum;
 443 };
 444
 445 /* Host Interface "Rev 1" */
 446 struct e1000_host_command_header {
 447         u8 command_id;
 448         u8 command_length;
 449         u8 command_options;
 450         u8 checksum;
 451 };
 452
 453 #define E1000_HI_MAX_DATA_LENGTH        252
 454 struct e1000_host_command_info {
 455         struct e1000_host_command_header command_header;
 456         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 457 };
 458
 459 /* Host Interface "Rev 2" */
 460 struct e1000_host_mng_command_header {
 461         u8  command_id;
 462         u8  checksum;
 463         u16 reserved1;
 464         u16 reserved2;
 465         u16 command_length;
 466 };
 467
 468 #define E1000_HI_MAX_MNG_DATA_LENGTH    0x6F8
 469 struct e1000_host_mng_command_info {
 470         struct e1000_host_mng_command_header command_header;
 471         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 472 };
 473
 474 #include "e1000_mac.h"
 475 #include "e1000_phy.h"
 476 #include "e1000_nvm.h"
 477 #include "e1000_manage.h"
 478 #include "e1000_mbx.h"
 479
 480 struct e1000_mac_operations {
 481         /* Function pointers for the MAC. */
 482         s32  (*init_params)(struct e1000_hw *);
 483         s32  (*id_led_init)(struct e1000_hw *);
 484         s32  (*blink_led)(struct e1000_hw *);
 485         s32  (*check_for_link)(struct e1000_hw *);
 486         bool (*check_mng_mode)(struct e1000_hw *hw);
 487         s32  (*cleanup_led)(struct e1000_hw *);
 488         void (*clear_hw_cntrs)(struct e1000_hw *);
 489         void (*clear_vfta)(struct e1000_hw *);
 490         s32  (*get_bus_info)(struct e1000_hw *);
 491         void (*set_lan_id)(struct e1000_hw *);
 492         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 493         s32  (*led_on)(struct e1000_hw *);
 494         s32  (*led_off)(struct e1000_hw *);
 495         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
 496         s32  (*reset_hw)(struct e1000_hw *);
 497         s32  (*init_hw)(struct e1000_hw *);
 498         void (*shutdown_serdes)(struct e1000_hw *);
 499         void (*power_up_serdes)(struct e1000_hw *);
 500         s32  (*setup_link)(struct e1000_hw *);
 501         s32  (*setup_physical_interface)(struct e1000_hw *);
 502         s32  (*setup_led)(struct e1000_hw *);
 503         void (*write_vfta)(struct e1000_hw *, u32, u32);
 504         void (*config_collision_dist)(struct e1000_hw *);
 505         void (*rar_set)(struct e1000_hw *, u8*, u32);
 506         s32  (*read_mac_addr)(struct e1000_hw *);
 507         s32  (*validate_mdi_setting)(struct e1000_hw *);
 508         s32  (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
 509         s32  (*mng_write_cmd_header)(struct e1000_hw *hw,
 510                                      struct e1000_host_mng_command_header*);
 511         s32  (*mng_enable_host_if)(struct e1000_hw *);
 512         s32  (*wait_autoneg)(struct e1000_hw *);
 513         s32 (*get_thermal_sensor_data)(struct e1000_hw *);
 514         s32 (*init_thermal_sensor_thresh)(struct e1000_hw *);
 515         s32  (*acquire_swfw_sync)(struct e1000_hw *, u16);
 516         void (*release_swfw_sync)(struct e1000_hw *, u16);
 517 };
 518
 519 /*
 520  * When to use various PHY register access functions:
 521  *
 522  *                 Func   Caller
 523  *   Function      Does   Does    When to use
 524  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 525  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
 526  *   X_reg_locked  P,A    L       for multiple accesses of different regs
 527  *                                on different pages
 528  *   X_reg_page    A      L,P     for multiple accesses of different regs
 529  *                                on the same page
 530  *
 531  * Where X=[read|write], L=locking, P=sets page, A=register access
 532  *
 533  */
 534 struct e1000_phy_operations {
 535         s32  (*init_params)(struct e1000_hw *);
 536         s32  (*acquire)(struct e1000_hw *);
 537         s32  (*check_polarity)(struct e1000_hw *);
 538         s32  (*check_reset_block)(struct e1000_hw *);
 539         s32  (*commit)(struct e1000_hw *);
 540         s32  (*force_speed_duplex)(struct e1000_hw *);
 541         s32  (*get_cfg_done)(struct e1000_hw *hw);
 542         s32  (*get_cable_length)(struct e1000_hw *);
 543         s32  (*get_info)(struct e1000_hw *);
 544         s32  (*set_page)(struct e1000_hw *, u16);
 545         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 546         s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
 547         s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
 548         void (*release)(struct e1000_hw *);
 549         s32  (*reset)(struct e1000_hw *);
 550         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 551         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 552         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 553         s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
 554         s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
 555         void (*power_up)(struct e1000_hw *);
 556         void (*power_down)(struct e1000_hw *);
 557         s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
 558         s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
 559 };
 560
 561 struct e1000_nvm_operations {
 562         s32  (*init_params)(struct e1000_hw *);
 563         s32  (*acquire)(struct e1000_hw *);
 564         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 565         void (*release)(struct e1000_hw *);
 566         void (*reload)(struct e1000_hw *);
 567         s32  (*update)(struct e1000_hw *);
 568         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 569         s32  (*validate)(struct e1000_hw *);
 570         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 571 };
 572
 573 #define E1000_MAX_SENSORS               3
 574
 575 struct e1000_thermal_diode_data {
 576         u8 location;
 577         u8 temp;
 578         u8 caution_thresh;
 579         u8 max_op_thresh;
 580 };
 581
 582 struct e1000_thermal_sensor_data {
 583         struct e1000_thermal_diode_data sensor[E1000_MAX_SENSORS];
 584 };
 585
 586 struct e1000_mac_info {
 587         struct e1000_mac_operations ops;
 588         u8 addr[ETH_ADDR_LEN];
 589         u8 perm_addr[ETH_ADDR_LEN];
 590
 591         enum e1000_mac_type type;
 592
 593         u32 collision_delta;
 594         u32 ledctl_default;
 595         u32 ledctl_mode1;
 596         u32 ledctl_mode2;
 597         u32 mc_filter_type;
 598         u32 tx_packet_delta;
 599         u32 txcw;
 600
 601         u16 current_ifs_val;
 602         u16 ifs_max_val;
 603         u16 ifs_min_val;
 604         u16 ifs_ratio;
 605         u16 ifs_step_size;
 606         u16 mta_reg_count;
 607         u16 uta_reg_count;
 608
 609         /* Maximum size of the MTA register table in all supported adapters */
 610         #define MAX_MTA_REG 128
 611         u32 mta_shadow[MAX_MTA_REG];
 612         u16 rar_entry_count;
 613
 614         u8  forced_speed_duplex;
 615
 616         bool adaptive_ifs;
 617         bool has_fwsm;
 618         bool arc_subsystem_valid;
 619         bool asf_firmware_present;
 620         bool autoneg;
 621         bool autoneg_failed;
 622         bool get_link_status;
 623         bool in_ifs_mode;
 624         enum e1000_serdes_link_state serdes_link_state;
 625         bool serdes_has_link;
 626         bool tx_pkt_filtering;
 627         struct e1000_thermal_sensor_data thermal_sensor_data;
 628 };
 629
 630 struct e1000_phy_info {
 631         struct e1000_phy_operations ops;
 632         enum e1000_phy_type type;
 633
 634         enum e1000_1000t_rx_status local_rx;
 635         enum e1000_1000t_rx_status remote_rx;
 636         enum e1000_ms_type ms_type;
 637         enum e1000_ms_type original_ms_type;
 638         enum e1000_rev_polarity cable_polarity;
 639         enum e1000_smart_speed smart_speed;
 640
 641         u32 addr;
 642         u32 id;
 643         u32 reset_delay_us; /* in usec */
 644         u32 revision;
 645
 646         enum e1000_media_type media_type;
 647
 648         u16 autoneg_advertised;
 649         u16 autoneg_mask;
 650         u16 cable_length;
 651         u16 max_cable_length;
 652         u16 min_cable_length;
 653
 654         u8 mdix;
 655
 656         bool disable_polarity_correction;
 657         bool is_mdix;
 658         bool polarity_correction;
 659         bool reset_disable;
 660         bool speed_downgraded;
 661         bool autoneg_wait_to_complete;
 662 };
 663
 664 struct e1000_nvm_info {
 665         struct e1000_nvm_operations ops;
 666         enum e1000_nvm_type type;
 667         enum e1000_nvm_override override;
 668
 669         u32 flash_bank_size;
 670         u32 flash_base_addr;
 671
 672         u16 word_size;
 673         u16 delay_usec;
 674         u16 address_bits;
 675         u16 opcode_bits;
 676         u16 page_size;
 677 };
 678
 679 struct e1000_bus_info {
 680         enum e1000_bus_type type;
 681         enum e1000_bus_speed speed;
 682         enum e1000_bus_width width;
 683
 684         u16 func;
 685         u16 pci_cmd_word;
 686 };
 687
 688 struct e1000_fc_info {
 689         u32 high_water;  /* Flow control high-water mark */
 690         u32 low_water;  /* Flow control low-water mark */
 691         u16 pause_time;  /* Flow control pause timer */
 692         u16 refresh_time;  /* Flow control refresh timer */
 693         bool send_xon;  /* Flow control send XON */
 694         bool strict_ieee;  /* Strict IEEE mode */
 695         enum e1000_fc_mode current_mode;  /* FC mode in effect */
 696         enum e1000_fc_mode requested_mode;  /* FC mode requested by caller */
 697 };
 698
 699 struct e1000_mbx_operations {
 700         s32 (*init_params)(struct e1000_hw *hw);
 701         s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
 702         s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
 703         s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
 704         s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
 705         s32 (*check_for_msg)(struct e1000_hw *, u16);
 706         s32 (*check_for_ack)(struct e1000_hw *, u16);
 707         s32 (*check_for_rst)(struct e1000_hw *, u16);
 708 };
 709
 710 struct e1000_mbx_stats {
 711         u32 msgs_tx;
 712         u32 msgs_rx;
 713
 714         u32 acks;
 715         u32 reqs;
 716         u32 rsts;
 717 };
 718
 719 struct e1000_mbx_info {
 720         struct e1000_mbx_operations ops;
 721         struct e1000_mbx_stats stats;
 722         u32 timeout;
 723         u32 usec_delay;
 724         u16 size;
 725 };
 726
 727 struct e1000_dev_spec_82575 {
 728         bool sgmii_active;
 729         bool global_device_reset;
 730         bool eee_disable;
 731         bool module_plugged;
 732         u32 mtu;
 733 };
 734
 735 struct e1000_dev_spec_vf {
 736         u32 vf_number;
 737         u32 v2p_mailbox;
 738 };
 739
 740 struct e1000_hw {
 741         void *back;
 742
 743         u8 __iomem *hw_addr;
 744         u8 __iomem *flash_address;
 745         unsigned long io_base;
 746
 747         struct e1000_mac_info  mac;
 748         struct e1000_fc_info   fc;
 749         struct e1000_phy_info  phy;
 750         struct e1000_nvm_info  nvm;
 751         struct e1000_bus_info  bus;
 752         struct e1000_mbx_info mbx;
 753         struct e1000_host_mng_dhcp_cookie mng_cookie;
 754
 755         union {
 756                 struct e1000_dev_spec_82575 _82575;
 757                 struct e1000_dev_spec_vf vf;
 758         } dev_spec;
 759
 760         u16 device_id;
 761         u16 subsystem_vendor_id;
 762         u16 subsystem_device_id;
 763         u16 vendor_id;
 764
 765         u8  revision_id;
 766 };
 767
 768 #include "e1000_82575.h"
 769
 770 /* These functions must be implemented by drivers */
 771 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 772 s32  e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 773
 774 #endif