1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "LICENSE.GPL".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include "e1000_api.h"
31 static s32 e1000_acquire_nvm_i210(struct e1000_hw *hw);
32 static void e1000_release_nvm_i210(struct e1000_hw *hw);
33 static s32 e1000_get_hw_semaphore_i210(struct e1000_hw *hw);
34 static s32 e1000_write_nvm_srwr(struct e1000_hw *hw, u16 offset, u16 words,
36 static s32 e1000_pool_flash_update_done_i210(struct e1000_hw *hw);
37 static s32 e1000_valid_led_default_i210(struct e1000_hw *hw, u16 *data);
40 * e1000_acquire_nvm_i210 - Request for access to EEPROM
41 * @hw: pointer to the HW structure
43 * Acquire the necessary semaphores for exclusive access to the EEPROM.
44 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
45 * Return successful if access grant bit set, else clear the request for
46 * EEPROM access and return -E1000_ERR_NVM (-1).
48 static s32 e1000_acquire_nvm_i210(struct e1000_hw *hw)
52 DEBUGFUNC("e1000_acquire_nvm_i210");
54 ret_val = e1000_acquire_swfw_sync_i210(hw, E1000_SWFW_EEP_SM);
60 * e1000_release_nvm_i210 - Release exclusive access to EEPROM
61 * @hw: pointer to the HW structure
63 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
64 * then release the semaphores acquired.
66 static void e1000_release_nvm_i210(struct e1000_hw *hw)
68 DEBUGFUNC("e1000_release_nvm_i210");
70 e1000_release_swfw_sync_i210(hw, E1000_SWFW_EEP_SM);
74 * e1000_acquire_swfw_sync_i210 - Acquire SW/FW semaphore
75 * @hw: pointer to the HW structure
76 * @mask: specifies which semaphore to acquire
78 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
79 * will also specify which port we're acquiring the lock for.
81 s32 e1000_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask)
85 u32 fwmask = mask << 16;
86 s32 ret_val = E1000_SUCCESS;
87 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
89 DEBUGFUNC("e1000_acquire_swfw_sync_i210");
92 if (e1000_get_hw_semaphore_i210(hw)) {
93 ret_val = -E1000_ERR_SWFW_SYNC;
97 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
98 if (!(swfw_sync & (fwmask | swmask)))
102 * Firmware currently using resource (fwmask)
103 * or other software thread using resource (swmask)
105 e1000_put_hw_semaphore_generic(hw);
111 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
112 ret_val = -E1000_ERR_SWFW_SYNC;
117 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
119 e1000_put_hw_semaphore_generic(hw);
126 * e1000_release_swfw_sync_i210 - Release SW/FW semaphore
127 * @hw: pointer to the HW structure
128 * @mask: specifies which semaphore to acquire
130 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
131 * will also specify which port we're releasing the lock for.
133 void e1000_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask)
137 DEBUGFUNC("e1000_release_swfw_sync_i210");
139 while (e1000_get_hw_semaphore_i210(hw) != E1000_SUCCESS)
142 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
144 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
146 e1000_put_hw_semaphore_generic(hw);
150 * e1000_get_hw_semaphore_i210 - Acquire hardware semaphore
151 * @hw: pointer to the HW structure
153 * Acquire the HW semaphore to access the PHY or NVM
155 static s32 e1000_get_hw_semaphore_i210(struct e1000_hw *hw)
158 s32 timeout = hw->nvm.word_size + 1;
161 DEBUGFUNC("e1000_get_hw_semaphore_i210");
163 /* Get the SW semaphore */
164 while (i < timeout) {
165 swsm = E1000_READ_REG(hw, E1000_SWSM);
166 if (!(swsm & E1000_SWSM_SMBI))
174 /* In rare circumstances, the SW semaphore may already be held
175 * unintentionally. Clear the semaphore once before giving up.
177 if (hw->dev_spec._82575.clear_semaphore_once) {
178 hw->dev_spec._82575.clear_semaphore_once = false;
179 e1000_put_hw_semaphore_generic(hw);
180 for (i = 0; i < timeout; i++) {
181 swsm = E1000_READ_REG(hw, E1000_SWSM);
182 if (!(swsm & E1000_SWSM_SMBI))
189 /* If we do not have the semaphore here, we have to give up. */
191 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
192 return -E1000_ERR_NVM;
196 /* Get the FW semaphore. */
197 for (i = 0; i < timeout; i++) {
198 swsm = E1000_READ_REG(hw, E1000_SWSM);
199 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
201 /* Semaphore acquired if bit latched */
202 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
209 /* Release semaphores */
210 e1000_put_hw_semaphore_generic(hw);
211 DEBUGOUT("Driver can't access the NVM\n");
212 return -E1000_ERR_NVM;
215 return E1000_SUCCESS;
219 * e1000_read_nvm_srrd_i210 - Reads Shadow Ram using EERD register
220 * @hw: pointer to the HW structure
221 * @offset: offset of word in the Shadow Ram to read
222 * @words: number of words to read
223 * @data: word read from the Shadow Ram
225 * Reads a 16 bit word from the Shadow Ram using the EERD register.
226 * Uses necessary synchronization semaphores.
228 s32 e1000_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset, u16 words,
231 s32 status = E1000_SUCCESS;
234 DEBUGFUNC("e1000_read_nvm_srrd_i210");
236 /* We cannot hold synchronization semaphores for too long,
237 * because of forceful takeover procedure. However it is more efficient
238 * to read in bursts than synchronizing access for each word. */
239 for (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) {
240 count = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ?
241 E1000_EERD_EEWR_MAX_COUNT : (words - i);
242 if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {
243 status = e1000_read_nvm_eerd(hw, offset, count,
245 hw->nvm.ops.release(hw);
247 status = E1000_ERR_SWFW_SYNC;
250 if (status != E1000_SUCCESS)
258 * e1000_write_nvm_srwr_i210 - Write to Shadow RAM using EEWR
259 * @hw: pointer to the HW structure
260 * @offset: offset within the Shadow RAM to be written to
261 * @words: number of words to write
262 * @data: 16 bit word(s) to be written to the Shadow RAM
264 * Writes data to Shadow RAM at offset using EEWR register.
266 * If e1000_update_nvm_checksum is not called after this function , the
267 * data will not be committed to FLASH and also Shadow RAM will most likely
268 * contain an invalid checksum.
270 * If error code is returned, data and Shadow RAM may be inconsistent - buffer
273 s32 e1000_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset, u16 words,
276 s32 status = E1000_SUCCESS;
279 DEBUGFUNC("e1000_write_nvm_srwr_i210");
281 /* We cannot hold synchronization semaphores for too long,
282 * because of forceful takeover procedure. However it is more efficient
283 * to write in bursts than synchronizing access for each word. */
284 for (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) {
285 count = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ?
286 E1000_EERD_EEWR_MAX_COUNT : (words - i);
287 if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {
288 status = e1000_write_nvm_srwr(hw, offset, count,
290 hw->nvm.ops.release(hw);
292 status = E1000_ERR_SWFW_SYNC;
295 if (status != E1000_SUCCESS)
303 * e1000_write_nvm_srwr - Write to Shadow Ram using EEWR
304 * @hw: pointer to the HW structure
305 * @offset: offset within the Shadow Ram to be written to
306 * @words: number of words to write
307 * @data: 16 bit word(s) to be written to the Shadow Ram
309 * Writes data to Shadow Ram at offset using EEWR register.
311 * If e1000_update_nvm_checksum is not called after this function , the
312 * Shadow Ram will most likely contain an invalid checksum.
314 static s32 e1000_write_nvm_srwr(struct e1000_hw *hw, u16 offset, u16 words,
317 struct e1000_nvm_info *nvm = &hw->nvm;
319 u32 attempts = 100000;
320 s32 ret_val = E1000_SUCCESS;
322 DEBUGFUNC("e1000_write_nvm_srwr");
325 * A check for invalid values: offset too large, too many words,
326 * too many words for the offset, and not enough words.
328 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
330 DEBUGOUT("nvm parameter(s) out of bounds\n");
331 ret_val = -E1000_ERR_NVM;
335 for (i = 0; i < words; i++) {
336 eewr = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
337 (data[i] << E1000_NVM_RW_REG_DATA) |
338 E1000_NVM_RW_REG_START;
340 E1000_WRITE_REG(hw, E1000_SRWR, eewr);
342 for (k = 0; k < attempts; k++) {
343 if (E1000_NVM_RW_REG_DONE &
344 E1000_READ_REG(hw, E1000_SRWR)) {
345 ret_val = E1000_SUCCESS;
351 if (ret_val != E1000_SUCCESS) {
352 DEBUGOUT("Shadow RAM write EEWR timed out\n");
361 /** e1000_read_invm_word_i210 - Reads OTP
362 * @hw: pointer to the HW structure
363 * @address: the word address (aka eeprom offset) to read
364 * @data: pointer to the data read
366 * Reads 16-bit words from the OTP. Return error when the word is not
369 static s32 e1000_read_invm_word_i210(struct e1000_hw *hw, u8 address, u16 *data)
371 s32 status = -E1000_ERR_INVM_VALUE_NOT_FOUND;
374 u8 record_type, word_address;
376 DEBUGFUNC("e1000_read_invm_word_i210");
378 for (i = 0; i < E1000_INVM_SIZE; i++) {
379 invm_dword = E1000_READ_REG(hw, E1000_INVM_DATA_REG(i));
380 /* Get record type */
381 record_type = INVM_DWORD_TO_RECORD_TYPE(invm_dword);
382 if (record_type == E1000_INVM_UNINITIALIZED_STRUCTURE)
384 if (record_type == E1000_INVM_CSR_AUTOLOAD_STRUCTURE)
385 i += E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS;
386 if (record_type == E1000_INVM_RSA_KEY_SHA256_STRUCTURE)
387 i += E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS;
388 if (record_type == E1000_INVM_WORD_AUTOLOAD_STRUCTURE) {
389 word_address = INVM_DWORD_TO_WORD_ADDRESS(invm_dword);
390 if (word_address == address) {
391 *data = INVM_DWORD_TO_WORD_DATA(invm_dword);
392 DEBUGOUT2("Read INVM Word 0x%02x = %x",
394 status = E1000_SUCCESS;
399 if (status != E1000_SUCCESS)
400 DEBUGOUT1("Requested word 0x%02x not found in OTP\n", address);
404 /** e1000_read_invm_i210 - Read invm wrapper function for I210/I211
405 * @hw: pointer to the HW structure
406 * @address: the word address (aka eeprom offset) to read
407 * @data: pointer to the data read
409 * Wrapper function to return data formerly found in the NVM.
411 static s32 e1000_read_invm_i210(struct e1000_hw *hw, u16 offset,
412 u16 E1000_UNUSEDARG words, u16 *data)
414 s32 ret_val = E1000_SUCCESS;
416 DEBUGFUNC("e1000_read_invm_i210");
418 /* Only the MAC addr is required to be present in the iNVM */
421 ret_val = e1000_read_invm_word_i210(hw, (u8)offset, &data[0]);
422 ret_val |= e1000_read_invm_word_i210(hw, (u8)offset+1,
424 ret_val |= e1000_read_invm_word_i210(hw, (u8)offset+2,
426 if (ret_val != E1000_SUCCESS)
427 DEBUGOUT("MAC Addr not found in iNVM\n");
429 case NVM_INIT_CTRL_2:
430 ret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);
431 if (ret_val != E1000_SUCCESS) {
432 *data = NVM_INIT_CTRL_2_DEFAULT_I211;
433 ret_val = E1000_SUCCESS;
436 case NVM_INIT_CTRL_4:
437 ret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);
438 if (ret_val != E1000_SUCCESS) {
439 *data = NVM_INIT_CTRL_4_DEFAULT_I211;
440 ret_val = E1000_SUCCESS;
444 ret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);
445 if (ret_val != E1000_SUCCESS) {
446 *data = NVM_LED_1_CFG_DEFAULT_I211;
447 ret_val = E1000_SUCCESS;
450 case NVM_LED_0_2_CFG:
451 ret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);
452 if (ret_val != E1000_SUCCESS) {
453 *data = NVM_LED_0_2_CFG_DEFAULT_I211;
454 ret_val = E1000_SUCCESS;
457 case NVM_ID_LED_SETTINGS:
458 ret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);
459 if (ret_val != E1000_SUCCESS) {
460 *data = ID_LED_RESERVED_FFFF;
461 ret_val = E1000_SUCCESS;
465 *data = hw->subsystem_device_id;
468 *data = hw->subsystem_vendor_id;
471 *data = hw->device_id;
474 *data = hw->vendor_id;
477 DEBUGOUT1("NVM word 0x%02x is not mapped.\n", offset);
478 *data = NVM_RESERVED_WORD;
485 * e1000_read_invm_version - Reads iNVM version and image type
486 * @hw: pointer to the HW structure
487 * @invm_ver: version structure for the version read
489 * Reads iNVM version and image type.
491 s32 e1000_read_invm_version(struct e1000_hw *hw,
492 struct e1000_fw_version *invm_ver)
495 u32 *next_record = NULL;
498 u32 invm_blocks = E1000_INVM_SIZE - (E1000_INVM_ULT_BYTES_SIZE /
499 E1000_INVM_RECORD_SIZE_IN_BYTES);
500 u32 buffer[E1000_INVM_SIZE];
501 s32 status = -E1000_ERR_INVM_VALUE_NOT_FOUND;
504 DEBUGFUNC("e1000_read_invm_version");
506 /* Read iNVM memory */
507 for (i = 0; i < E1000_INVM_SIZE; i++) {
508 invm_dword = E1000_READ_REG(hw, E1000_INVM_DATA_REG(i));
509 buffer[i] = invm_dword;
512 /* Read version number */
513 for (i = 1; i < invm_blocks; i++) {
514 record = &buffer[invm_blocks - i];
515 next_record = &buffer[invm_blocks - i + 1];
517 /* Check if we have first version location used */
518 if ((i == 1) && ((*record & E1000_INVM_VER_FIELD_ONE) == 0)) {
520 status = E1000_SUCCESS;
523 /* Check if we have second version location used */
525 ((*record & E1000_INVM_VER_FIELD_TWO) == 0)) {
526 version = (*record & E1000_INVM_VER_FIELD_ONE) >> 3;
527 status = E1000_SUCCESS;
531 * Check if we have odd version location
532 * used and it is the last one used
534 else if ((((*record & E1000_INVM_VER_FIELD_ONE) == 0) &&
535 ((*record & 0x3) == 0)) || (((*record & 0x3) != 0) &&
537 version = (*next_record & E1000_INVM_VER_FIELD_TWO)
539 status = E1000_SUCCESS;
543 * Check if we have even version location
544 * used and it is the last one used
546 else if (((*record & E1000_INVM_VER_FIELD_TWO) == 0) &&
547 ((*record & 0x3) == 0)) {
548 version = (*record & E1000_INVM_VER_FIELD_ONE) >> 3;
549 status = E1000_SUCCESS;
554 if (status == E1000_SUCCESS) {
555 invm_ver->invm_major = (version & E1000_INVM_MAJOR_MASK)
556 >> E1000_INVM_MAJOR_SHIFT;
557 invm_ver->invm_minor = version & E1000_INVM_MINOR_MASK;
559 /* Read Image Type */
560 for (i = 1; i < invm_blocks; i++) {
561 record = &buffer[invm_blocks - i];
562 next_record = &buffer[invm_blocks - i + 1];
564 /* Check if we have image type in first location used */
565 if ((i == 1) && ((*record & E1000_INVM_IMGTYPE_FIELD) == 0)) {
566 invm_ver->invm_img_type = 0;
567 status = E1000_SUCCESS;
570 /* Check if we have image type in first location used */
571 else if ((((*record & 0x3) == 0) &&
572 ((*record & E1000_INVM_IMGTYPE_FIELD) == 0)) ||
573 ((((*record & 0x3) != 0) && (i != 1)))) {
574 invm_ver->invm_img_type =
575 (*next_record & E1000_INVM_IMGTYPE_FIELD) >> 23;
576 status = E1000_SUCCESS;
584 * e1000_validate_nvm_checksum_i210 - Validate EEPROM checksum
585 * @hw: pointer to the HW structure
587 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
588 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
590 s32 e1000_validate_nvm_checksum_i210(struct e1000_hw *hw)
592 s32 status = E1000_SUCCESS;
593 s32 (*read_op_ptr)(struct e1000_hw *, u16, u16, u16 *);
595 DEBUGFUNC("e1000_validate_nvm_checksum_i210");
597 if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {
600 * Replace the read function with semaphore grabbing with
601 * the one that skips this for a while.
602 * We have semaphore taken already here.
604 read_op_ptr = hw->nvm.ops.read;
605 hw->nvm.ops.read = e1000_read_nvm_eerd;
607 status = e1000_validate_nvm_checksum_generic(hw);
609 /* Revert original read operation. */
610 hw->nvm.ops.read = read_op_ptr;
612 hw->nvm.ops.release(hw);
614 status = E1000_ERR_SWFW_SYNC;
622 * e1000_update_nvm_checksum_i210 - Update EEPROM checksum
623 * @hw: pointer to the HW structure
625 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
626 * up to the checksum. Then calculates the EEPROM checksum and writes the
627 * value to the EEPROM. Next commit EEPROM data onto the Flash.
629 s32 e1000_update_nvm_checksum_i210(struct e1000_hw *hw)
631 s32 ret_val = E1000_SUCCESS;
635 DEBUGFUNC("e1000_update_nvm_checksum_i210");
638 * Read the first word from the EEPROM. If this times out or fails, do
639 * not continue or we could be in for a very long wait while every
642 ret_val = e1000_read_nvm_eerd(hw, 0, 1, &nvm_data);
643 if (ret_val != E1000_SUCCESS) {
644 DEBUGOUT("EEPROM read failed\n");
648 if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {
650 * Do not use hw->nvm.ops.write, hw->nvm.ops.read
651 * because we do not want to take the synchronization
652 * semaphores twice here.
655 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
656 ret_val = e1000_read_nvm_eerd(hw, i, 1, &nvm_data);
658 hw->nvm.ops.release(hw);
659 DEBUGOUT("NVM Read Error while updating checksum.\n");
662 checksum += nvm_data;
664 checksum = (u16) NVM_SUM - checksum;
665 ret_val = e1000_write_nvm_srwr(hw, NVM_CHECKSUM_REG, 1,
667 if (ret_val != E1000_SUCCESS) {
668 hw->nvm.ops.release(hw);
669 DEBUGOUT("NVM Write Error while updating checksum.\n");
673 hw->nvm.ops.release(hw);
675 ret_val = e1000_update_flash_i210(hw);
677 ret_val = E1000_ERR_SWFW_SYNC;
684 * e1000_get_flash_presence_i210 - Check if flash device is detected.
685 * @hw: pointer to the HW structure
688 bool e1000_get_flash_presence_i210(struct e1000_hw *hw)
691 bool ret_val = false;
693 DEBUGFUNC("e1000_get_flash_presence_i210");
695 eec = E1000_READ_REG(hw, E1000_EECD);
697 if (eec & E1000_EECD_FLASH_DETECTED_I210)
704 * e1000_update_flash_i210 - Commit EEPROM to the flash
705 * @hw: pointer to the HW structure
708 s32 e1000_update_flash_i210(struct e1000_hw *hw)
710 s32 ret_val = E1000_SUCCESS;
713 DEBUGFUNC("e1000_update_flash_i210");
715 ret_val = e1000_pool_flash_update_done_i210(hw);
716 if (ret_val == -E1000_ERR_NVM) {
717 DEBUGOUT("Flash update time out\n");
721 flup = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD_I210;
722 E1000_WRITE_REG(hw, E1000_EECD, flup);
724 ret_val = e1000_pool_flash_update_done_i210(hw);
725 if (ret_val == E1000_SUCCESS)
726 DEBUGOUT("Flash update complete\n");
728 DEBUGOUT("Flash update time out\n");
735 * e1000_pool_flash_update_done_i210 - Pool FLUDONE status.
736 * @hw: pointer to the HW structure
739 s32 e1000_pool_flash_update_done_i210(struct e1000_hw *hw)
741 s32 ret_val = -E1000_ERR_NVM;
744 DEBUGFUNC("e1000_pool_flash_update_done_i210");
746 for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) {
747 reg = E1000_READ_REG(hw, E1000_EECD);
748 if (reg & E1000_EECD_FLUDONE_I210) {
749 ret_val = E1000_SUCCESS;
759 * e1000_init_nvm_params_i210 - Initialize i210 NVM function pointers
760 * @hw: pointer to the HW structure
762 * Initialize the i210/i211 NVM parameters and function pointers.
764 static s32 e1000_init_nvm_params_i210(struct e1000_hw *hw)
766 s32 ret_val = E1000_SUCCESS;
767 struct e1000_nvm_info *nvm = &hw->nvm;
769 DEBUGFUNC("e1000_init_nvm_params_i210");
771 ret_val = e1000_init_nvm_params_82575(hw);
772 nvm->ops.acquire = e1000_acquire_nvm_i210;
773 nvm->ops.release = e1000_release_nvm_i210;
774 nvm->ops.valid_led_default = e1000_valid_led_default_i210;
775 if (e1000_get_flash_presence_i210(hw)) {
776 hw->nvm.type = e1000_nvm_flash_hw;
777 nvm->ops.read = e1000_read_nvm_srrd_i210;
778 nvm->ops.write = e1000_write_nvm_srwr_i210;
779 nvm->ops.validate = e1000_validate_nvm_checksum_i210;
780 nvm->ops.update = e1000_update_nvm_checksum_i210;
782 hw->nvm.type = e1000_nvm_invm;
783 nvm->ops.read = e1000_read_invm_i210;
784 nvm->ops.write = e1000_null_write_nvm;
785 nvm->ops.validate = e1000_null_ops_generic;
786 nvm->ops.update = e1000_null_ops_generic;
792 * e1000_init_function_pointers_i210 - Init func ptrs.
793 * @hw: pointer to the HW structure
795 * Called to initialize all function pointers and parameters.
797 void e1000_init_function_pointers_i210(struct e1000_hw *hw)
799 e1000_init_function_pointers_82575(hw);
800 hw->nvm.ops.init_params = e1000_init_nvm_params_i210;
806 * e1000_valid_led_default_i210 - Verify a valid default LED config
807 * @hw: pointer to the HW structure
808 * @data: pointer to the NVM (EEPROM)
810 * Read the EEPROM for the current default LED configuration. If the
811 * LED configuration is not valid, set to a valid LED configuration.
813 static s32 e1000_valid_led_default_i210(struct e1000_hw *hw, u16 *data)
817 DEBUGFUNC("e1000_valid_led_default_i210");
819 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
821 DEBUGOUT("NVM Read Error\n");
825 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
826 switch (hw->phy.media_type) {
827 case e1000_media_type_internal_serdes:
828 *data = ID_LED_DEFAULT_I210_SERDES;
830 case e1000_media_type_copper:
832 *data = ID_LED_DEFAULT_I210;
841 * __e1000_access_xmdio_reg - Read/write XMDIO register
842 * @hw: pointer to the HW structure
843 * @address: XMDIO address to program
844 * @dev_addr: device address to program
845 * @data: pointer to value to read/write from/to the XMDIO address
846 * @read: boolean flag to indicate read or write
848 static s32 __e1000_access_xmdio_reg(struct e1000_hw *hw, u16 address,
849 u8 dev_addr, u16 *data, bool read)
851 s32 ret_val = E1000_SUCCESS;
853 DEBUGFUNC("__e1000_access_xmdio_reg");
855 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr);
859 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, address);
863 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, E1000_MMDAC_FUNC_DATA |
869 ret_val = hw->phy.ops.read_reg(hw, E1000_MMDAAD, data);
871 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, *data);
875 /* Recalibrate the device back to 0 */
876 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, 0);
884 * e1000_read_xmdio_reg - Read XMDIO register
885 * @hw: pointer to the HW structure
886 * @addr: XMDIO address to program
887 * @dev_addr: device address to program
888 * @data: value to be read from the EMI address
890 s32 e1000_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 *data)
892 DEBUGFUNC("e1000_read_xmdio_reg");
894 return __e1000_access_xmdio_reg(hw, addr, dev_addr, data, true);
898 * e1000_write_xmdio_reg - Write XMDIO register
899 * @hw: pointer to the HW structure
900 * @addr: XMDIO address to program
901 * @dev_addr: device address to program
902 * @data: value to be written to the XMDIO address
904 s32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 data)
906 DEBUGFUNC("e1000_read_xmdio_reg");
908 return __e1000_access_xmdio_reg(hw, addr, dev_addr, &data, false);