1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include "e1000_api.h"
30 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
31 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
32 static void e1000_config_collision_dist_generic(struct e1000_hw *hw);
35 * e1000_init_mac_ops_generic - Initialize MAC function pointers
36 * @hw: pointer to the HW structure
38 * Setups up the function pointers to no-op functions
40 void e1000_init_mac_ops_generic(struct e1000_hw *hw)
42 struct e1000_mac_info *mac = &hw->mac;
43 DEBUGFUNC("e1000_init_mac_ops_generic");
46 mac->ops.init_params = e1000_null_ops_generic;
47 mac->ops.init_hw = e1000_null_ops_generic;
48 mac->ops.reset_hw = e1000_null_ops_generic;
49 mac->ops.setup_physical_interface = e1000_null_ops_generic;
50 mac->ops.get_bus_info = e1000_null_ops_generic;
51 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie;
52 mac->ops.read_mac_addr = e1000_read_mac_addr_generic;
53 mac->ops.config_collision_dist = e1000_config_collision_dist_generic;
54 mac->ops.clear_hw_cntrs = e1000_null_mac_generic;
56 mac->ops.cleanup_led = e1000_null_ops_generic;
57 mac->ops.setup_led = e1000_null_ops_generic;
58 mac->ops.blink_led = e1000_null_ops_generic;
59 mac->ops.led_on = e1000_null_ops_generic;
60 mac->ops.led_off = e1000_null_ops_generic;
62 mac->ops.setup_link = e1000_null_ops_generic;
63 mac->ops.get_link_up_info = e1000_null_link_info;
64 mac->ops.check_for_link = e1000_null_ops_generic;
65 mac->ops.wait_autoneg = e1000_wait_autoneg_generic;
67 mac->ops.check_mng_mode = e1000_null_mng_mode;
68 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic;
69 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic;
70 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic;
72 mac->ops.update_mc_addr_list = e1000_null_update_mc;
73 mac->ops.clear_vfta = e1000_null_mac_generic;
74 mac->ops.write_vfta = e1000_null_write_vfta;
75 mac->ops.rar_set = e1000_rar_set_generic;
76 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic;
80 * e1000_null_ops_generic - No-op function, returns 0
81 * @hw: pointer to the HW structure
83 s32 e1000_null_ops_generic(struct e1000_hw *hw)
85 DEBUGFUNC("e1000_null_ops_generic");
90 * e1000_null_mac_generic - No-op function, return void
91 * @hw: pointer to the HW structure
93 void e1000_null_mac_generic(struct e1000_hw *hw)
95 DEBUGFUNC("e1000_null_mac_generic");
100 * e1000_null_link_info - No-op function, return 0
101 * @hw: pointer to the HW structure
103 s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d)
105 DEBUGFUNC("e1000_null_link_info");
106 return E1000_SUCCESS;
110 * e1000_null_mng_mode - No-op function, return false
111 * @hw: pointer to the HW structure
113 bool e1000_null_mng_mode(struct e1000_hw *hw)
115 DEBUGFUNC("e1000_null_mng_mode");
120 * e1000_null_update_mc - No-op function, return void
121 * @hw: pointer to the HW structure
123 void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a)
125 DEBUGFUNC("e1000_null_update_mc");
130 * e1000_null_write_vfta - No-op function, return void
131 * @hw: pointer to the HW structure
133 void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b)
135 DEBUGFUNC("e1000_null_write_vfta");
140 * e1000_null_rar_set - No-op function, return void
141 * @hw: pointer to the HW structure
143 void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a)
145 DEBUGFUNC("e1000_null_rar_set");
150 * e1000_get_bus_info_pcie_generic - Get PCIe bus information
151 * @hw: pointer to the HW structure
153 * Determines and stores the system bus information for a particular
154 * network interface. The following bus information is determined and stored:
155 * bus speed, bus width, type (PCIe), and PCIe function.
157 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
159 struct e1000_mac_info *mac = &hw->mac;
160 struct e1000_bus_info *bus = &hw->bus;
162 u16 pcie_link_status;
164 DEBUGFUNC("e1000_get_bus_info_pcie_generic");
166 bus->type = e1000_bus_type_pci_express;
168 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS,
171 bus->width = e1000_bus_width_unknown;
172 bus->speed = e1000_bus_speed_unknown;
174 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) {
175 case PCIE_LINK_SPEED_2500:
176 bus->speed = e1000_bus_speed_2500;
178 case PCIE_LINK_SPEED_5000:
179 bus->speed = e1000_bus_speed_5000;
182 bus->speed = e1000_bus_speed_unknown;
186 bus->width = (enum e1000_bus_width)((pcie_link_status &
187 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT);
190 mac->ops.set_lan_id(hw);
192 return E1000_SUCCESS;
196 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
198 * @hw: pointer to the HW structure
200 * Determines the LAN function id by reading memory-mapped registers
201 * and swaps the port value if requested.
203 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
205 struct e1000_bus_info *bus = &hw->bus;
209 * The status register reports the correct function number
210 * for the device regardless of function swap state.
212 reg = E1000_READ_REG(hw, E1000_STATUS);
213 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
217 * e1000_set_lan_id_single_port - Set LAN id for a single port device
218 * @hw: pointer to the HW structure
220 * Sets the LAN function id to zero for a single port device.
222 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
224 struct e1000_bus_info *bus = &hw->bus;
230 * e1000_clear_vfta_generic - Clear VLAN filter table
231 * @hw: pointer to the HW structure
233 * Clears the register array which contains the VLAN filter table by
234 * setting all the values to 0.
236 void e1000_clear_vfta_generic(struct e1000_hw *hw)
240 DEBUGFUNC("e1000_clear_vfta_generic");
242 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
243 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
244 E1000_WRITE_FLUSH(hw);
249 * e1000_write_vfta_generic - Write value to VLAN filter table
250 * @hw: pointer to the HW structure
251 * @offset: register offset in VLAN filter table
252 * @value: register value written to VLAN filter table
254 * Writes value at the given offset in the register array which stores
255 * the VLAN filter table.
257 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
259 DEBUGFUNC("e1000_write_vfta_generic");
261 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
262 E1000_WRITE_FLUSH(hw);
266 * e1000_init_rx_addrs_generic - Initialize receive address's
267 * @hw: pointer to the HW structure
268 * @rar_count: receive address registers
270 * Setup the receive address registers by setting the base receive address
271 * register to the devices MAC address and clearing all the other receive
272 * address registers to 0.
274 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
277 u8 mac_addr[ETH_ADDR_LEN] = {0};
279 DEBUGFUNC("e1000_init_rx_addrs_generic");
281 /* Setup the receive address */
282 DEBUGOUT("Programming MAC Address into RAR[0]\n");
284 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
286 /* Zero out the other (rar_entry_count - 1) receive addresses */
287 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
288 for (i = 1; i < rar_count; i++)
289 hw->mac.ops.rar_set(hw, mac_addr, i);
293 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
294 * @hw: pointer to the HW structure
296 * Checks the nvm for an alternate MAC address. An alternate MAC address
297 * can be setup by pre-boot software and must be treated like a permanent
298 * address and must override the actual permanent MAC address. If an
299 * alternate MAC address is found it is programmed into RAR0, replacing
300 * the permanent address that was installed into RAR0 by the Si on reset.
301 * This function will return SUCCESS unless it encounters an error while
302 * reading the EEPROM.
304 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
307 s32 ret_val = E1000_SUCCESS;
308 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
309 u8 alt_mac_addr[ETH_ADDR_LEN];
311 DEBUGFUNC("e1000_check_alt_mac_addr_generic");
313 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
319 * Alternate MAC address is handled by the option ROM for 82580
320 * and newer. SW support not required.
322 if (hw->mac.type >= e1000_82580)
323 return E1000_SUCCESS;
325 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
326 &nvm_alt_mac_addr_offset);
328 DEBUGOUT("NVM Read Error\n");
332 if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
333 (nvm_alt_mac_addr_offset == 0x0000))
334 /* There is no Alternate MAC Address */
335 return E1000_SUCCESS;
337 if (hw->bus.func == E1000_FUNC_1)
338 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
339 if (hw->bus.func == E1000_FUNC_2)
340 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2;
342 if (hw->bus.func == E1000_FUNC_3)
343 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3;
344 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
345 offset = nvm_alt_mac_addr_offset + (i >> 1);
346 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
348 DEBUGOUT("NVM Read Error\n");
352 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
353 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
356 /* if multicast bit is set, the alternate address will not be used */
357 if (alt_mac_addr[0] & 0x01) {
358 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n");
359 return E1000_SUCCESS;
363 * We have a valid alternate MAC address, and we want to treat it the
364 * same as the normal permanent MAC address stored by the HW into the
365 * RAR. Do this by mapping this address into RAR0.
367 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
369 return E1000_SUCCESS;
373 * e1000_rar_set_generic - Set receive address register
374 * @hw: pointer to the HW structure
375 * @addr: pointer to the receive address
376 * @index: receive address array register
378 * Sets the receive address array register at index to the address passed
381 void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
383 u32 rar_low, rar_high;
385 DEBUGFUNC("e1000_rar_set_generic");
388 * HW expects these in little endian so we reverse the byte order
389 * from network order (big endian) to little endian
391 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
392 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
394 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
396 /* If MAC address zero, no need to set the AV bit */
397 if (rar_low || rar_high)
398 rar_high |= E1000_RAH_AV;
401 * Some bridges will combine consecutive 32-bit writes into
402 * a single burst write, which will malfunction on some parts.
403 * The flushes avoid this.
405 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
406 E1000_WRITE_FLUSH(hw);
407 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
408 E1000_WRITE_FLUSH(hw);
412 * e1000_hash_mc_addr_generic - Generate a multicast hash value
413 * @hw: pointer to the HW structure
414 * @mc_addr: pointer to a multicast address
416 * Generates a multicast address hash value which is used to determine
417 * the multicast filter table array address and new table value.
419 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
421 u32 hash_value, hash_mask;
424 DEBUGFUNC("e1000_hash_mc_addr_generic");
426 /* Register count multiplied by bits per register */
427 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
430 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
431 * where 0xFF would still fall within the hash mask.
433 while (hash_mask >> bit_shift != 0xFF)
437 * The portion of the address that is used for the hash table
438 * is determined by the mc_filter_type setting.
439 * The algorithm is such that there is a total of 8 bits of shifting.
440 * The bit_shift for a mc_filter_type of 0 represents the number of
441 * left-shifts where the MSB of mc_addr[5] would still fall within
442 * the hash_mask. Case 0 does this exactly. Since there are a total
443 * of 8 bits of shifting, then mc_addr[4] will shift right the
444 * remaining number of bits. Thus 8 - bit_shift. The rest of the
445 * cases are a variation of this algorithm...essentially raising the
446 * number of bits to shift mc_addr[5] left, while still keeping the
447 * 8-bit shifting total.
449 * For example, given the following Destination MAC Address and an
450 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
451 * we can see that the bit_shift for case 0 is 4. These are the hash
452 * values resulting from each mc_filter_type...
453 * [0] [1] [2] [3] [4] [5]
457 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
458 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
459 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
460 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
462 switch (hw->mac.mc_filter_type) {
477 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
478 (((u16) mc_addr[5]) << bit_shift)));
484 * e1000_update_mc_addr_list_generic - Update Multicast addresses
485 * @hw: pointer to the HW structure
486 * @mc_addr_list: array of multicast addresses to program
487 * @mc_addr_count: number of multicast addresses to program
489 * Updates entire Multicast Table Array.
490 * The caller must have a packed mc_addr_list of multicast addresses.
492 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
493 u8 *mc_addr_list, u32 mc_addr_count)
495 u32 hash_value, hash_bit, hash_reg;
498 DEBUGFUNC("e1000_update_mc_addr_list_generic");
500 /* clear mta_shadow */
501 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
503 /* update mta_shadow from mc_addr_list */
504 for (i = 0; (u32) i < mc_addr_count; i++) {
505 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);
507 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
508 hash_bit = hash_value & 0x1F;
510 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
511 mc_addr_list += (ETH_ADDR_LEN);
514 /* replace the entire MTA table */
515 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
516 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
517 E1000_WRITE_FLUSH(hw);
521 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters
522 * @hw: pointer to the HW structure
524 * Clears the base hardware counters by reading the counter registers.
526 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
528 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic");
530 E1000_READ_REG(hw, E1000_CRCERRS);
531 E1000_READ_REG(hw, E1000_SYMERRS);
532 E1000_READ_REG(hw, E1000_MPC);
533 E1000_READ_REG(hw, E1000_SCC);
534 E1000_READ_REG(hw, E1000_ECOL);
535 E1000_READ_REG(hw, E1000_MCC);
536 E1000_READ_REG(hw, E1000_LATECOL);
537 E1000_READ_REG(hw, E1000_COLC);
538 E1000_READ_REG(hw, E1000_DC);
539 E1000_READ_REG(hw, E1000_SEC);
540 E1000_READ_REG(hw, E1000_RLEC);
541 E1000_READ_REG(hw, E1000_XONRXC);
542 E1000_READ_REG(hw, E1000_XONTXC);
543 E1000_READ_REG(hw, E1000_XOFFRXC);
544 E1000_READ_REG(hw, E1000_XOFFTXC);
545 E1000_READ_REG(hw, E1000_FCRUC);
546 E1000_READ_REG(hw, E1000_GPRC);
547 E1000_READ_REG(hw, E1000_BPRC);
548 E1000_READ_REG(hw, E1000_MPRC);
549 E1000_READ_REG(hw, E1000_GPTC);
550 E1000_READ_REG(hw, E1000_GORCL);
551 E1000_READ_REG(hw, E1000_GORCH);
552 E1000_READ_REG(hw, E1000_GOTCL);
553 E1000_READ_REG(hw, E1000_GOTCH);
554 E1000_READ_REG(hw, E1000_RNBC);
555 E1000_READ_REG(hw, E1000_RUC);
556 E1000_READ_REG(hw, E1000_RFC);
557 E1000_READ_REG(hw, E1000_ROC);
558 E1000_READ_REG(hw, E1000_RJC);
559 E1000_READ_REG(hw, E1000_TORL);
560 E1000_READ_REG(hw, E1000_TORH);
561 E1000_READ_REG(hw, E1000_TOTL);
562 E1000_READ_REG(hw, E1000_TOTH);
563 E1000_READ_REG(hw, E1000_TPR);
564 E1000_READ_REG(hw, E1000_TPT);
565 E1000_READ_REG(hw, E1000_MPTC);
566 E1000_READ_REG(hw, E1000_BPTC);
570 * e1000_check_for_copper_link_generic - Check for link (Copper)
571 * @hw: pointer to the HW structure
573 * Checks to see of the link status of the hardware has changed. If a
574 * change in link status has been detected, then we read the PHY registers
575 * to get the current speed/duplex if link exists.
577 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)
579 struct e1000_mac_info *mac = &hw->mac;
583 DEBUGFUNC("e1000_check_for_copper_link");
586 * We only want to go out to the PHY registers to see if Auto-Neg
587 * has completed and/or if our link status has changed. The
588 * get_link_status flag is set upon receiving a Link Status
589 * Change or Rx Sequence Error interrupt.
591 if (!mac->get_link_status)
592 return E1000_SUCCESS;
595 * First we want to see if the MII Status Register reports
596 * link. If so, then we want to get the current speed/duplex
599 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
604 return E1000_SUCCESS; /* No link detected */
606 mac->get_link_status = false;
609 * Check if there was DownShift, must be checked
610 * immediately after link-up
612 e1000_check_downshift_generic(hw);
615 * If we are forcing speed/duplex, then we simply return since
616 * we have already determined whether we have link or not.
619 return -E1000_ERR_CONFIG;
622 * Auto-Neg is enabled. Auto Speed Detection takes care
623 * of MAC speed/duplex configuration. So we only need to
624 * configure Collision Distance in the MAC.
626 mac->ops.config_collision_dist(hw);
629 * Configure Flow Control now that Auto-Neg has completed.
630 * First, we need to restore the desired flow control
631 * settings because we may have had to re-autoneg with a
632 * different link partner.
634 ret_val = e1000_config_fc_after_link_up_generic(hw);
636 DEBUGOUT("Error configuring flow control\n");
642 * e1000_check_for_fiber_link_generic - Check for link (Fiber)
643 * @hw: pointer to the HW structure
645 * Checks for link up on the hardware. If link is not up and we have
646 * a signal, then we need to force link up.
648 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
650 struct e1000_mac_info *mac = &hw->mac;
656 DEBUGFUNC("e1000_check_for_fiber_link_generic");
658 ctrl = E1000_READ_REG(hw, E1000_CTRL);
659 status = E1000_READ_REG(hw, E1000_STATUS);
660 rxcw = E1000_READ_REG(hw, E1000_RXCW);
663 * If we don't have link (auto-negotiation failed or link partner
664 * cannot auto-negotiate), the cable is plugged in (we have signal),
665 * and our link partner is not trying to auto-negotiate with us (we
666 * are receiving idles or data), we need to force link up. We also
667 * need to give auto-negotiation time to complete, in case the cable
668 * was just plugged in. The autoneg_failed flag does this.
670 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
671 if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) &&
672 !(rxcw & E1000_RXCW_C)) {
673 if (!mac->autoneg_failed) {
674 mac->autoneg_failed = true;
675 return E1000_SUCCESS;
677 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
679 /* Disable auto-negotiation in the TXCW register */
680 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
682 /* Force link-up and also force full-duplex. */
683 ctrl = E1000_READ_REG(hw, E1000_CTRL);
684 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
685 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
687 /* Configure Flow Control after forcing link up. */
688 ret_val = e1000_config_fc_after_link_up_generic(hw);
690 DEBUGOUT("Error configuring flow control\n");
693 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
695 * If we are forcing link and we are receiving /C/ ordered
696 * sets, re-enable auto-negotiation in the TXCW register
697 * and disable forced link in the Device Control register
698 * in an attempt to auto-negotiate with our link partner.
700 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
701 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
702 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
704 mac->serdes_has_link = true;
707 return E1000_SUCCESS;
711 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
712 * @hw: pointer to the HW structure
714 * Checks for link up on the hardware. If link is not up and we have
715 * a signal, then we need to force link up.
717 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
719 struct e1000_mac_info *mac = &hw->mac;
725 DEBUGFUNC("e1000_check_for_serdes_link_generic");
727 ctrl = E1000_READ_REG(hw, E1000_CTRL);
728 status = E1000_READ_REG(hw, E1000_STATUS);
729 rxcw = E1000_READ_REG(hw, E1000_RXCW);
732 * If we don't have link (auto-negotiation failed or link partner
733 * cannot auto-negotiate), and our link partner is not trying to
734 * auto-negotiate with us (we are receiving idles or data),
735 * we need to force link up. We also need to give auto-negotiation
738 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
739 if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) {
740 if (!mac->autoneg_failed) {
741 mac->autoneg_failed = true;
742 return E1000_SUCCESS;
744 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
746 /* Disable auto-negotiation in the TXCW register */
747 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
749 /* Force link-up and also force full-duplex. */
750 ctrl = E1000_READ_REG(hw, E1000_CTRL);
751 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
752 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
754 /* Configure Flow Control after forcing link up. */
755 ret_val = e1000_config_fc_after_link_up_generic(hw);
757 DEBUGOUT("Error configuring flow control\n");
760 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
762 * If we are forcing link and we are receiving /C/ ordered
763 * sets, re-enable auto-negotiation in the TXCW register
764 * and disable forced link in the Device Control register
765 * in an attempt to auto-negotiate with our link partner.
767 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
768 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
769 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
771 mac->serdes_has_link = true;
772 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
774 * If we force link for non-auto-negotiation switch, check
775 * link status based on MAC synchronization for internal
778 /* SYNCH bit and IV bit are sticky. */
780 rxcw = E1000_READ_REG(hw, E1000_RXCW);
781 if (rxcw & E1000_RXCW_SYNCH) {
782 if (!(rxcw & E1000_RXCW_IV)) {
783 mac->serdes_has_link = true;
784 DEBUGOUT("SERDES: Link up - forced.\n");
787 mac->serdes_has_link = false;
788 DEBUGOUT("SERDES: Link down - force failed.\n");
792 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) {
793 status = E1000_READ_REG(hw, E1000_STATUS);
794 if (status & E1000_STATUS_LU) {
795 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
797 rxcw = E1000_READ_REG(hw, E1000_RXCW);
798 if (rxcw & E1000_RXCW_SYNCH) {
799 if (!(rxcw & E1000_RXCW_IV)) {
800 mac->serdes_has_link = true;
801 DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n");
803 mac->serdes_has_link = false;
804 DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n");
807 mac->serdes_has_link = false;
808 DEBUGOUT("SERDES: Link down - no sync.\n");
811 mac->serdes_has_link = false;
812 DEBUGOUT("SERDES: Link down - autoneg failed\n");
816 return E1000_SUCCESS;
820 * e1000_set_default_fc_generic - Set flow control default values
821 * @hw: pointer to the HW structure
823 * Read the EEPROM for the default values for flow control and store the
826 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
831 DEBUGFUNC("e1000_set_default_fc_generic");
834 * Read and store word 0x0F of the EEPROM. This word contains bits
835 * that determine the hardware's default PAUSE (flow control) mode,
836 * a bit that determines whether the HW defaults to enabling or
837 * disabling auto-negotiation, and the direction of the
838 * SW defined pins. If there is no SW over-ride of the flow
839 * control setting, then the variable hw->fc will
840 * be initialized based on a value in the EEPROM.
842 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
845 DEBUGOUT("NVM Read Error\n");
849 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
850 hw->fc.requested_mode = e1000_fc_none;
851 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
853 hw->fc.requested_mode = e1000_fc_tx_pause;
855 hw->fc.requested_mode = e1000_fc_full;
857 return E1000_SUCCESS;
861 * e1000_setup_link_generic - Setup flow control and link settings
862 * @hw: pointer to the HW structure
864 * Determines which flow control settings to use, then configures flow
865 * control. Calls the appropriate media-specific link configuration
866 * function. Assuming the adapter has a valid link partner, a valid link
867 * should be established. Assumes the hardware has previously been reset
868 * and the transmitter and receiver are not enabled.
870 s32 e1000_setup_link_generic(struct e1000_hw *hw)
874 DEBUGFUNC("e1000_setup_link_generic");
877 * In the case of the phy reset being blocked, we already have a link.
878 * We do not need to set it up again.
880 if (hw->phy.ops.check_reset_block(hw))
881 return E1000_SUCCESS;
884 * If requested flow control is set to default, set flow control
885 * based on the EEPROM flow control settings.
887 if (hw->fc.requested_mode == e1000_fc_default) {
888 ret_val = e1000_set_default_fc_generic(hw);
894 * Save off the requested flow control mode for use later. Depending
895 * on the link partner's capabilities, we may or may not use this mode.
897 hw->fc.current_mode = hw->fc.requested_mode;
899 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
900 hw->fc.current_mode);
902 /* Call the necessary media_type subroutine to configure the link. */
903 ret_val = hw->mac.ops.setup_physical_interface(hw);
908 * Initialize the flow control address, type, and PAUSE timer
909 * registers to their default values. This is done even if flow
910 * control is disabled, because it does not hurt anything to
911 * initialize these registers.
913 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
914 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
915 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
916 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
918 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
920 return e1000_set_fc_watermarks_generic(hw);
924 * e1000_commit_fc_settings_generic - Configure flow control
925 * @hw: pointer to the HW structure
927 * Write the flow control settings to the Transmit Config Word Register (TXCW)
928 * base on the flow control settings in e1000_mac_info.
930 static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
932 struct e1000_mac_info *mac = &hw->mac;
935 DEBUGFUNC("e1000_commit_fc_settings_generic");
938 * Check for a software override of the flow control settings, and
939 * setup the device accordingly. If auto-negotiation is enabled, then
940 * software will have to set the "PAUSE" bits to the correct value in
941 * the Transmit Config Word Register (TXCW) and re-start auto-
942 * negotiation. However, if auto-negotiation is disabled, then
943 * software will have to manually configure the two flow control enable
944 * bits in the CTRL register.
946 * The possible values of the "fc" parameter are:
947 * 0: Flow control is completely disabled
948 * 1: Rx flow control is enabled (we can receive pause frames,
949 * but not send pause frames).
950 * 2: Tx flow control is enabled (we can send pause frames but we
951 * do not support receiving pause frames).
952 * 3: Both Rx and Tx flow control (symmetric) are enabled.
954 switch (hw->fc.current_mode) {
956 /* Flow control completely disabled by a software over-ride. */
957 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
959 case e1000_fc_rx_pause:
961 * Rx Flow control is enabled and Tx Flow control is disabled
962 * by a software over-ride. Since there really isn't a way to
963 * advertise that we are capable of Rx Pause ONLY, we will
964 * advertise that we support both symmetric and asymmetric Rx
965 * PAUSE. Later, we will disable the adapter's ability to send
968 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
970 case e1000_fc_tx_pause:
972 * Tx Flow control is enabled, and Rx Flow control is disabled,
973 * by a software over-ride.
975 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
979 * Flow control (both Rx and Tx) is enabled by a software
982 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
985 DEBUGOUT("Flow control param set incorrectly\n");
986 return -E1000_ERR_CONFIG;
990 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
993 return E1000_SUCCESS;
997 * e1000_poll_fiber_serdes_link_generic - Poll for link up
998 * @hw: pointer to the HW structure
1000 * Polls for link up by reading the status register, if link fails to come
1001 * up with auto-negotiation, then the link is forced if a signal is detected.
1003 static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
1005 struct e1000_mac_info *mac = &hw->mac;
1009 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic");
1012 * If we have a signal (the cable is plugged in, or assumed true for
1013 * serdes media) then poll for a "Link-Up" indication in the Device
1014 * Status Register. Time-out if a link isn't seen in 500 milliseconds
1015 * seconds (Auto-negotiation should complete in less than 500
1016 * milliseconds even if the other end is doing it in SW).
1018 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
1020 status = E1000_READ_REG(hw, E1000_STATUS);
1021 if (status & E1000_STATUS_LU)
1024 if (i == FIBER_LINK_UP_LIMIT) {
1025 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1026 mac->autoneg_failed = true;
1028 * AutoNeg failed to achieve a link, so we'll call
1029 * mac->check_for_link. This routine will force the
1030 * link up if we detect a signal. This will allow us to
1031 * communicate with non-autonegotiating link partners.
1033 ret_val = mac->ops.check_for_link(hw);
1035 DEBUGOUT("Error while checking for link\n");
1038 mac->autoneg_failed = false;
1040 mac->autoneg_failed = false;
1041 DEBUGOUT("Valid Link Found\n");
1044 return E1000_SUCCESS;
1048 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
1049 * @hw: pointer to the HW structure
1051 * Configures collision distance and flow control for fiber and serdes
1052 * links. Upon successful setup, poll for link.
1054 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
1059 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic");
1061 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1063 /* Take the link out of reset */
1064 ctrl &= ~E1000_CTRL_LRST;
1066 hw->mac.ops.config_collision_dist(hw);
1068 ret_val = e1000_commit_fc_settings_generic(hw);
1073 * Since auto-negotiation is enabled, take the link out of reset (the
1074 * link will be in reset, because we previously reset the chip). This
1075 * will restart auto-negotiation. If auto-negotiation is successful
1076 * then the link-up status bit will be set and the flow control enable
1077 * bits (RFCE and TFCE) will be set according to their negotiated value.
1079 DEBUGOUT("Auto-negotiation enabled\n");
1081 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1082 E1000_WRITE_FLUSH(hw);
1086 * For these adapters, the SW definable pin 1 is set when the optics
1087 * detect a signal. If we have a signal, then poll for a "Link-Up"
1090 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1091 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1092 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1094 DEBUGOUT("No signal detected\n");
1101 * e1000_config_collision_dist_generic - Configure collision distance
1102 * @hw: pointer to the HW structure
1104 * Configures the collision distance to the default value and is used
1105 * during link setup.
1107 static void e1000_config_collision_dist_generic(struct e1000_hw *hw)
1111 DEBUGFUNC("e1000_config_collision_dist_generic");
1113 tctl = E1000_READ_REG(hw, E1000_TCTL);
1115 tctl &= ~E1000_TCTL_COLD;
1116 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1118 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1119 E1000_WRITE_FLUSH(hw);
1123 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks
1124 * @hw: pointer to the HW structure
1126 * Sets the flow control high/low threshold (watermark) registers. If
1127 * flow control XON frame transmission is enabled, then set XON frame
1128 * transmission as well.
1130 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
1132 u32 fcrtl = 0, fcrth = 0;
1134 DEBUGFUNC("e1000_set_fc_watermarks_generic");
1137 * Set the flow control receive threshold registers. Normally,
1138 * these registers will be set to a default threshold that may be
1139 * adjusted later by the driver's runtime code. However, if the
1140 * ability to transmit pause frames is not enabled, then these
1141 * registers will be set to 0.
1143 if (hw->fc.current_mode & e1000_fc_tx_pause) {
1145 * We need to set up the Receive Threshold high and low water
1146 * marks as well as (optionally) enabling the transmission of
1149 fcrtl = hw->fc.low_water;
1150 if (hw->fc.send_xon)
1151 fcrtl |= E1000_FCRTL_XONE;
1153 fcrth = hw->fc.high_water;
1155 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
1156 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
1158 return E1000_SUCCESS;
1162 * e1000_force_mac_fc_generic - Force the MAC's flow control settings
1163 * @hw: pointer to the HW structure
1165 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1166 * device control register to reflect the adapter settings. TFCE and RFCE
1167 * need to be explicitly set by software when a copper PHY is used because
1168 * autonegotiation is managed by the PHY rather than the MAC. Software must
1169 * also configure these bits when link is forced on a fiber connection.
1171 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
1175 DEBUGFUNC("e1000_force_mac_fc_generic");
1177 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1180 * Because we didn't get link via the internal auto-negotiation
1181 * mechanism (we either forced link or we got link via PHY
1182 * auto-neg), we have to manually enable/disable transmit an
1183 * receive flow control.
1185 * The "Case" statement below enables/disable flow control
1186 * according to the "hw->fc.current_mode" parameter.
1188 * The possible values of the "fc" parameter are:
1189 * 0: Flow control is completely disabled
1190 * 1: Rx flow control is enabled (we can receive pause
1191 * frames but not send pause frames).
1192 * 2: Tx flow control is enabled (we can send pause frames
1193 * frames but we do not receive pause frames).
1194 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1195 * other: No other values should be possible at this point.
1197 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1199 switch (hw->fc.current_mode) {
1201 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1203 case e1000_fc_rx_pause:
1204 ctrl &= (~E1000_CTRL_TFCE);
1205 ctrl |= E1000_CTRL_RFCE;
1207 case e1000_fc_tx_pause:
1208 ctrl &= (~E1000_CTRL_RFCE);
1209 ctrl |= E1000_CTRL_TFCE;
1212 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1215 DEBUGOUT("Flow control param set incorrectly\n");
1216 return -E1000_ERR_CONFIG;
1219 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1221 return E1000_SUCCESS;
1225 * e1000_config_fc_after_link_up_generic - Configures flow control after link
1226 * @hw: pointer to the HW structure
1228 * Checks the status of auto-negotiation after link up to ensure that the
1229 * speed and duplex were not forced. If the link needed to be forced, then
1230 * flow control needs to be forced also. If auto-negotiation is enabled
1231 * and did not fail, then we configure flow control based on our link
1234 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
1236 struct e1000_mac_info *mac = &hw->mac;
1237 s32 ret_val = E1000_SUCCESS;
1238 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1241 DEBUGFUNC("e1000_config_fc_after_link_up_generic");
1244 * Check for the case where we have fiber media and auto-neg failed
1245 * so we had to force link. In this case, we need to force the
1246 * configuration of the MAC to match the "fc" parameter.
1248 if (mac->autoneg_failed) {
1249 if (hw->phy.media_type == e1000_media_type_fiber ||
1250 hw->phy.media_type == e1000_media_type_internal_serdes)
1251 ret_val = e1000_force_mac_fc_generic(hw);
1253 if (hw->phy.media_type == e1000_media_type_copper)
1254 ret_val = e1000_force_mac_fc_generic(hw);
1258 DEBUGOUT("Error forcing flow control settings\n");
1263 * Check for the case where we have copper media and auto-neg is
1264 * enabled. In this case, we need to check and see if Auto-Neg
1265 * has completed, and if so, how the PHY and link partner has
1266 * flow control configured.
1268 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1270 * Read the MII Status Register and check to see if AutoNeg
1271 * has completed. We read this twice because this reg has
1272 * some "sticky" (latched) bits.
1274 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1277 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1281 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1282 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
1287 * The AutoNeg process has completed, so we now need to
1288 * read both the Auto Negotiation Advertisement
1289 * Register (Address 4) and the Auto_Negotiation Base
1290 * Page Ability Register (Address 5) to determine how
1291 * flow control was negotiated.
1293 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1297 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1298 &mii_nway_lp_ability_reg);
1303 * Two bits in the Auto Negotiation Advertisement Register
1304 * (Address 4) and two bits in the Auto Negotiation Base
1305 * Page Ability Register (Address 5) determine flow control
1306 * for both the PHY and the link partner. The following
1307 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1308 * 1999, describes these PAUSE resolution bits and how flow
1309 * control is determined based upon these settings.
1310 * NOTE: DC = Don't Care
1312 * LOCAL DEVICE | LINK PARTNER
1313 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1314 *-------|---------|-------|---------|--------------------
1315 * 0 | 0 | DC | DC | e1000_fc_none
1316 * 0 | 1 | 0 | DC | e1000_fc_none
1317 * 0 | 1 | 1 | 0 | e1000_fc_none
1318 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1319 * 1 | 0 | 0 | DC | e1000_fc_none
1320 * 1 | DC | 1 | DC | e1000_fc_full
1321 * 1 | 1 | 0 | 0 | e1000_fc_none
1322 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1324 * Are both PAUSE bits set to 1? If so, this implies
1325 * Symmetric Flow Control is enabled at both ends. The
1326 * ASM_DIR bits are irrelevant per the spec.
1328 * For Symmetric Flow Control:
1330 * LOCAL DEVICE | LINK PARTNER
1331 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1332 *-------|---------|-------|---------|--------------------
1333 * 1 | DC | 1 | DC | E1000_fc_full
1336 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1337 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1339 * Now we need to check if the user selected Rx ONLY
1340 * of pause frames. In this case, we had to advertise
1341 * FULL flow control because we could not advertise Rx
1342 * ONLY. Hence, we must now check to see if we need to
1343 * turn OFF the TRANSMISSION of PAUSE frames.
1345 if (hw->fc.requested_mode == e1000_fc_full) {
1346 hw->fc.current_mode = e1000_fc_full;
1347 DEBUGOUT("Flow Control = FULL.\n");
1349 hw->fc.current_mode = e1000_fc_rx_pause;
1350 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1354 * For receiving PAUSE frames ONLY.
1356 * LOCAL DEVICE | LINK PARTNER
1357 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1358 *-------|---------|-------|---------|--------------------
1359 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1361 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1362 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1363 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1364 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1365 hw->fc.current_mode = e1000_fc_tx_pause;
1366 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
1369 * For transmitting PAUSE frames ONLY.
1371 * LOCAL DEVICE | LINK PARTNER
1372 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1373 *-------|---------|-------|---------|--------------------
1374 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1376 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1377 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1378 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1379 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1380 hw->fc.current_mode = e1000_fc_rx_pause;
1381 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1384 * Per the IEEE spec, at this point flow control
1385 * should be disabled.
1387 hw->fc.current_mode = e1000_fc_none;
1388 DEBUGOUT("Flow Control = NONE.\n");
1392 * Now we need to do one last check... If we auto-
1393 * negotiated to HALF DUPLEX, flow control should not be
1394 * enabled per IEEE 802.3 spec.
1396 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1398 DEBUGOUT("Error getting link speed and duplex\n");
1402 if (duplex == HALF_DUPLEX)
1403 hw->fc.current_mode = e1000_fc_none;
1406 * Now we call a subroutine to actually force the MAC
1407 * controller to use the correct flow control settings.
1409 ret_val = e1000_force_mac_fc_generic(hw);
1411 DEBUGOUT("Error forcing flow control settings\n");
1416 return E1000_SUCCESS;
1420 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
1421 * @hw: pointer to the HW structure
1422 * @speed: stores the current speed
1423 * @duplex: stores the current duplex
1425 * Read the status register for the current speed/duplex and store the current
1426 * speed and duplex for copper connections.
1428 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
1433 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic");
1435 status = E1000_READ_REG(hw, E1000_STATUS);
1436 if (status & E1000_STATUS_SPEED_1000) {
1437 *speed = SPEED_1000;
1438 DEBUGOUT("1000 Mbs, ");
1439 } else if (status & E1000_STATUS_SPEED_100) {
1441 DEBUGOUT("100 Mbs, ");
1444 DEBUGOUT("10 Mbs, ");
1447 if (status & E1000_STATUS_FD) {
1448 *duplex = FULL_DUPLEX;
1449 DEBUGOUT("Full Duplex\n");
1451 *duplex = HALF_DUPLEX;
1452 DEBUGOUT("Half Duplex\n");
1455 return E1000_SUCCESS;
1459 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex
1460 * @hw: pointer to the HW structure
1461 * @speed: stores the current speed
1462 * @duplex: stores the current duplex
1464 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1465 * for fiber/serdes links.
1467 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw,
1468 u16 *speed, u16 *duplex)
1470 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
1472 *speed = SPEED_1000;
1473 *duplex = FULL_DUPLEX;
1475 return E1000_SUCCESS;
1479 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore
1480 * @hw: pointer to the HW structure
1482 * Acquire the HW semaphore to access the PHY or NVM
1484 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw)
1487 s32 timeout = hw->nvm.word_size + 1;
1490 DEBUGFUNC("e1000_get_hw_semaphore_generic");
1492 /* Get the SW semaphore */
1493 while (i < timeout) {
1494 swsm = E1000_READ_REG(hw, E1000_SWSM);
1495 if (!(swsm & E1000_SWSM_SMBI))
1503 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1504 return -E1000_ERR_NVM;
1507 /* Get the FW semaphore. */
1508 for (i = 0; i < timeout; i++) {
1509 swsm = E1000_READ_REG(hw, E1000_SWSM);
1510 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1512 /* Semaphore acquired if bit latched */
1513 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
1520 /* Release semaphores */
1521 e1000_put_hw_semaphore_generic(hw);
1522 DEBUGOUT("Driver can't access the NVM\n");
1523 return -E1000_ERR_NVM;
1526 return E1000_SUCCESS;
1530 * e1000_put_hw_semaphore_generic - Release hardware semaphore
1531 * @hw: pointer to the HW structure
1533 * Release hardware semaphore used to access the PHY or NVM
1535 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw)
1539 DEBUGFUNC("e1000_put_hw_semaphore_generic");
1541 swsm = E1000_READ_REG(hw, E1000_SWSM);
1543 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1545 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
1549 * e1000_get_auto_rd_done_generic - Check for auto read completion
1550 * @hw: pointer to the HW structure
1552 * Check EEPROM for Auto Read done bit.
1554 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
1558 DEBUGFUNC("e1000_get_auto_rd_done_generic");
1560 while (i < AUTO_READ_DONE_TIMEOUT) {
1561 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)
1567 if (i == AUTO_READ_DONE_TIMEOUT) {
1568 DEBUGOUT("Auto read by HW from NVM has not completed.\n");
1569 return -E1000_ERR_RESET;
1572 return E1000_SUCCESS;
1576 * e1000_valid_led_default_generic - Verify a valid default LED config
1577 * @hw: pointer to the HW structure
1578 * @data: pointer to the NVM (EEPROM)
1580 * Read the EEPROM for the current default LED configuration. If the
1581 * LED configuration is not valid, set to a valid LED configuration.
1583 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
1587 DEBUGFUNC("e1000_valid_led_default_generic");
1589 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1591 DEBUGOUT("NVM Read Error\n");
1595 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1596 *data = ID_LED_DEFAULT;
1598 return E1000_SUCCESS;
1602 * e1000_id_led_init_generic -
1603 * @hw: pointer to the HW structure
1606 s32 e1000_id_led_init_generic(struct e1000_hw *hw)
1608 struct e1000_mac_info *mac = &hw->mac;
1610 const u32 ledctl_mask = 0x000000FF;
1611 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1612 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1614 const u16 led_mask = 0x0F;
1616 DEBUGFUNC("e1000_id_led_init_generic");
1618 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1622 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
1623 mac->ledctl_mode1 = mac->ledctl_default;
1624 mac->ledctl_mode2 = mac->ledctl_default;
1626 for (i = 0; i < 4; i++) {
1627 temp = (data >> (i << 2)) & led_mask;
1629 case ID_LED_ON1_DEF2:
1630 case ID_LED_ON1_ON2:
1631 case ID_LED_ON1_OFF2:
1632 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1633 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1635 case ID_LED_OFF1_DEF2:
1636 case ID_LED_OFF1_ON2:
1637 case ID_LED_OFF1_OFF2:
1638 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1639 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1646 case ID_LED_DEF1_ON2:
1647 case ID_LED_ON1_ON2:
1648 case ID_LED_OFF1_ON2:
1649 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1650 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1652 case ID_LED_DEF1_OFF2:
1653 case ID_LED_ON1_OFF2:
1654 case ID_LED_OFF1_OFF2:
1655 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1656 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1664 return E1000_SUCCESS;
1668 * e1000_setup_led_generic - Configures SW controllable LED
1669 * @hw: pointer to the HW structure
1671 * This prepares the SW controllable LED for use and saves the current state
1672 * of the LED so it can be later restored.
1674 s32 e1000_setup_led_generic(struct e1000_hw *hw)
1678 DEBUGFUNC("e1000_setup_led_generic");
1680 if (hw->mac.ops.setup_led != e1000_setup_led_generic)
1681 return -E1000_ERR_CONFIG;
1683 if (hw->phy.media_type == e1000_media_type_fiber) {
1684 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1685 hw->mac.ledctl_default = ledctl;
1687 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK |
1688 E1000_LEDCTL_LED0_MODE_MASK);
1689 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1690 E1000_LEDCTL_LED0_MODE_SHIFT);
1691 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1692 } else if (hw->phy.media_type == e1000_media_type_copper) {
1693 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1696 return E1000_SUCCESS;
1700 * e1000_cleanup_led_generic - Set LED config to default operation
1701 * @hw: pointer to the HW structure
1703 * Remove the current LED configuration and set the LED configuration
1704 * to the default value, saved from the EEPROM.
1706 s32 e1000_cleanup_led_generic(struct e1000_hw *hw)
1708 DEBUGFUNC("e1000_cleanup_led_generic");
1710 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1711 return E1000_SUCCESS;
1715 * e1000_blink_led_generic - Blink LED
1716 * @hw: pointer to the HW structure
1718 * Blink the LEDs which are set to be on.
1720 s32 e1000_blink_led_generic(struct e1000_hw *hw)
1722 u32 ledctl_blink = 0;
1725 DEBUGFUNC("e1000_blink_led_generic");
1727 if (hw->phy.media_type == e1000_media_type_fiber) {
1728 /* always blink LED0 for PCI-E fiber */
1729 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1730 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1733 * set the blink bit for each LED that's "on" (0x0E)
1736 ledctl_blink = hw->mac.ledctl_mode2;
1737 for (i = 0; i < 4; i++)
1738 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1739 E1000_LEDCTL_MODE_LED_ON)
1740 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1744 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
1746 return E1000_SUCCESS;
1750 * e1000_led_on_generic - Turn LED on
1751 * @hw: pointer to the HW structure
1755 s32 e1000_led_on_generic(struct e1000_hw *hw)
1759 DEBUGFUNC("e1000_led_on_generic");
1761 switch (hw->phy.media_type) {
1762 case e1000_media_type_fiber:
1763 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1764 ctrl &= ~E1000_CTRL_SWDPIN0;
1765 ctrl |= E1000_CTRL_SWDPIO0;
1766 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1768 case e1000_media_type_copper:
1769 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
1775 return E1000_SUCCESS;
1779 * e1000_led_off_generic - Turn LED off
1780 * @hw: pointer to the HW structure
1784 s32 e1000_led_off_generic(struct e1000_hw *hw)
1788 DEBUGFUNC("e1000_led_off_generic");
1790 switch (hw->phy.media_type) {
1791 case e1000_media_type_fiber:
1792 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1793 ctrl |= E1000_CTRL_SWDPIN0;
1794 ctrl |= E1000_CTRL_SWDPIO0;
1795 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1797 case e1000_media_type_copper:
1798 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1804 return E1000_SUCCESS;
1808 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities
1809 * @hw: pointer to the HW structure
1810 * @no_snoop: bitmap of snoop events
1812 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1814 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
1818 DEBUGFUNC("e1000_set_pcie_no_snoop_generic");
1821 gcr = E1000_READ_REG(hw, E1000_GCR);
1822 gcr &= ~(PCIE_NO_SNOOP_ALL);
1824 E1000_WRITE_REG(hw, E1000_GCR, gcr);
1829 * e1000_disable_pcie_master_generic - Disables PCI-express master access
1830 * @hw: pointer to the HW structure
1832 * Returns E1000_SUCCESS if successful, else returns -10
1833 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1834 * the master requests to be disabled.
1836 * Disables PCI-Express master access and verifies there are no pending
1839 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
1842 s32 timeout = MASTER_DISABLE_TIMEOUT;
1844 DEBUGFUNC("e1000_disable_pcie_master_generic");
1846 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1847 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
1848 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1851 if (!(E1000_READ_REG(hw, E1000_STATUS) &
1852 E1000_STATUS_GIO_MASTER_ENABLE))
1859 DEBUGOUT("Master requests are pending.\n");
1860 return -E1000_ERR_MASTER_REQUESTS_PENDING;
1863 return E1000_SUCCESS;
1867 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing
1868 * @hw: pointer to the HW structure
1870 * Reset the Adaptive Interframe Spacing throttle to default values.
1872 void e1000_reset_adaptive_generic(struct e1000_hw *hw)
1874 struct e1000_mac_info *mac = &hw->mac;
1876 DEBUGFUNC("e1000_reset_adaptive_generic");
1878 if (!mac->adaptive_ifs) {
1879 DEBUGOUT("Not in Adaptive IFS mode!\n");
1883 mac->current_ifs_val = 0;
1884 mac->ifs_min_val = IFS_MIN;
1885 mac->ifs_max_val = IFS_MAX;
1886 mac->ifs_step_size = IFS_STEP;
1887 mac->ifs_ratio = IFS_RATIO;
1889 mac->in_ifs_mode = false;
1890 E1000_WRITE_REG(hw, E1000_AIT, 0);
1894 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing
1895 * @hw: pointer to the HW structure
1897 * Update the Adaptive Interframe Spacing Throttle value based on the
1898 * time between transmitted packets and time between collisions.
1900 void e1000_update_adaptive_generic(struct e1000_hw *hw)
1902 struct e1000_mac_info *mac = &hw->mac;
1904 DEBUGFUNC("e1000_update_adaptive_generic");
1906 if (!mac->adaptive_ifs) {
1907 DEBUGOUT("Not in Adaptive IFS mode!\n");
1911 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
1912 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
1913 mac->in_ifs_mode = true;
1914 if (mac->current_ifs_val < mac->ifs_max_val) {
1915 if (!mac->current_ifs_val)
1916 mac->current_ifs_val = mac->ifs_min_val;
1918 mac->current_ifs_val +=
1920 E1000_WRITE_REG(hw, E1000_AIT,
1921 mac->current_ifs_val);
1925 if (mac->in_ifs_mode &&
1926 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
1927 mac->current_ifs_val = 0;
1928 mac->in_ifs_mode = false;
1929 E1000_WRITE_REG(hw, E1000_AIT, 0);
1935 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings
1936 * @hw: pointer to the HW structure
1938 * Verify that when not using auto-negotiation that MDI/MDIx is correctly
1939 * set, which is forced to MDI mode only.
1941 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
1943 DEBUGFUNC("e1000_validate_mdi_setting_generic");
1945 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
1946 DEBUGOUT("Invalid MDI setting detected\n");
1948 return -E1000_ERR_CONFIG;
1951 return E1000_SUCCESS;
1955 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register
1956 * @hw: pointer to the HW structure
1957 * @reg: 32bit register offset such as E1000_SCTL
1958 * @offset: register offset to write to
1959 * @data: data to write at register offset
1961 * Writes an address/data control type register. There are several of these
1962 * and they all have the format address << 8 | data and bit 31 is polled for
1965 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
1966 u32 offset, u8 data)
1968 u32 i, regvalue = 0;
1970 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic");
1972 /* Set up the address and data */
1973 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
1974 E1000_WRITE_REG(hw, reg, regvalue);
1976 /* Poll the ready bit to see if the MDI read completed */
1977 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
1979 regvalue = E1000_READ_REG(hw, reg);
1980 if (regvalue & E1000_GEN_CTL_READY)
1983 if (!(regvalue & E1000_GEN_CTL_READY)) {
1984 DEBUGOUT1("Reg %08x did not indicate ready\n", reg);
1985 return -E1000_ERR_PHY;
1988 return E1000_SUCCESS;