1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "LICENSE.GPL".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include "e1000_api.h"
30 static void e1000_reload_nvm_generic(struct e1000_hw *hw);
33 * e1000_init_nvm_ops_generic - Initialize NVM function pointers
34 * @hw: pointer to the HW structure
36 * Setups up the function pointers to no-op functions
38 void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
40 struct e1000_nvm_info *nvm = &hw->nvm;
41 DEBUGFUNC("e1000_init_nvm_ops_generic");
43 /* Initialize function pointers */
44 nvm->ops.init_params = e1000_null_ops_generic;
45 nvm->ops.acquire = e1000_null_ops_generic;
46 nvm->ops.read = e1000_null_read_nvm;
47 nvm->ops.release = e1000_null_nvm_generic;
48 nvm->ops.reload = e1000_reload_nvm_generic;
49 nvm->ops.update = e1000_null_ops_generic;
50 nvm->ops.valid_led_default = e1000_null_led_default;
51 nvm->ops.validate = e1000_null_ops_generic;
52 nvm->ops.write = e1000_null_write_nvm;
56 * e1000_null_nvm_read - No-op function, return 0
57 * @hw: pointer to the HW structure
59 s32 e1000_null_read_nvm(struct e1000_hw E1000_UNUSEDARG *hw,
60 u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,
61 u16 E1000_UNUSEDARG *c)
63 DEBUGFUNC("e1000_null_read_nvm");
68 * e1000_null_nvm_generic - No-op function, return void
69 * @hw: pointer to the HW structure
71 void e1000_null_nvm_generic(struct e1000_hw E1000_UNUSEDARG *hw)
73 DEBUGFUNC("e1000_null_nvm_generic");
78 * e1000_null_led_default - No-op function, return 0
79 * @hw: pointer to the HW structure
81 s32 e1000_null_led_default(struct e1000_hw E1000_UNUSEDARG *hw,
82 u16 E1000_UNUSEDARG *data)
84 DEBUGFUNC("e1000_null_led_default");
89 * e1000_null_write_nvm - No-op function, return 0
90 * @hw: pointer to the HW structure
92 s32 e1000_null_write_nvm(struct e1000_hw E1000_UNUSEDARG *hw,
93 u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,
94 u16 E1000_UNUSEDARG *c)
96 DEBUGFUNC("e1000_null_write_nvm");
101 * e1000_raise_eec_clk - Raise EEPROM clock
102 * @hw: pointer to the HW structure
103 * @eecd: pointer to the EEPROM
105 * Enable/Raise the EEPROM clock bit.
107 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
109 *eecd = *eecd | E1000_EECD_SK;
110 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
111 E1000_WRITE_FLUSH(hw);
112 usec_delay(hw->nvm.delay_usec);
116 * e1000_lower_eec_clk - Lower EEPROM clock
117 * @hw: pointer to the HW structure
118 * @eecd: pointer to the EEPROM
120 * Clear/Lower the EEPROM clock bit.
122 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
124 *eecd = *eecd & ~E1000_EECD_SK;
125 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
126 E1000_WRITE_FLUSH(hw);
127 usec_delay(hw->nvm.delay_usec);
131 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
132 * @hw: pointer to the HW structure
133 * @data: data to send to the EEPROM
134 * @count: number of bits to shift out
136 * We need to shift 'count' bits out to the EEPROM. So, the value in the
137 * "data" parameter will be shifted out to the EEPROM one bit at a time.
138 * In order to do this, "data" must be broken down into bits.
140 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
142 struct e1000_nvm_info *nvm = &hw->nvm;
143 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
146 DEBUGFUNC("e1000_shift_out_eec_bits");
148 mask = 0x01 << (count - 1);
149 if (nvm->type == e1000_nvm_eeprom_spi)
150 eecd |= E1000_EECD_DO;
153 eecd &= ~E1000_EECD_DI;
156 eecd |= E1000_EECD_DI;
158 E1000_WRITE_REG(hw, E1000_EECD, eecd);
159 E1000_WRITE_FLUSH(hw);
161 usec_delay(nvm->delay_usec);
163 e1000_raise_eec_clk(hw, &eecd);
164 e1000_lower_eec_clk(hw, &eecd);
169 eecd &= ~E1000_EECD_DI;
170 E1000_WRITE_REG(hw, E1000_EECD, eecd);
174 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
175 * @hw: pointer to the HW structure
176 * @count: number of bits to shift in
178 * In order to read a register from the EEPROM, we need to shift 'count' bits
179 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
180 * the EEPROM (setting the SK bit), and then reading the value of the data out
181 * "DO" bit. During this "shifting in" process the data in "DI" bit should
184 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
190 DEBUGFUNC("e1000_shift_in_eec_bits");
192 eecd = E1000_READ_REG(hw, E1000_EECD);
194 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
197 for (i = 0; i < count; i++) {
199 e1000_raise_eec_clk(hw, &eecd);
201 eecd = E1000_READ_REG(hw, E1000_EECD);
203 eecd &= ~E1000_EECD_DI;
204 if (eecd & E1000_EECD_DO)
207 e1000_lower_eec_clk(hw, &eecd);
214 * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
215 * @hw: pointer to the HW structure
216 * @ee_reg: EEPROM flag for polling
218 * Polls the EEPROM status bit for either read or write completion based
219 * upon the value of 'ee_reg'.
221 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
223 u32 attempts = 100000;
226 DEBUGFUNC("e1000_poll_eerd_eewr_done");
228 for (i = 0; i < attempts; i++) {
229 if (ee_reg == E1000_NVM_POLL_READ)
230 reg = E1000_READ_REG(hw, E1000_EERD);
232 reg = E1000_READ_REG(hw, E1000_EEWR);
234 if (reg & E1000_NVM_RW_REG_DONE)
235 return E1000_SUCCESS;
240 return -E1000_ERR_NVM;
244 * e1000_acquire_nvm_generic - Generic request for access to EEPROM
245 * @hw: pointer to the HW structure
247 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
248 * Return successful if access grant bit set, else clear the request for
249 * EEPROM access and return -E1000_ERR_NVM (-1).
251 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
253 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
254 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
256 DEBUGFUNC("e1000_acquire_nvm_generic");
258 E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
259 eecd = E1000_READ_REG(hw, E1000_EECD);
262 if (eecd & E1000_EECD_GNT)
265 eecd = E1000_READ_REG(hw, E1000_EECD);
270 eecd &= ~E1000_EECD_REQ;
271 E1000_WRITE_REG(hw, E1000_EECD, eecd);
272 DEBUGOUT("Could not acquire NVM grant\n");
273 return -E1000_ERR_NVM;
276 return E1000_SUCCESS;
280 * e1000_standby_nvm - Return EEPROM to standby state
281 * @hw: pointer to the HW structure
283 * Return the EEPROM to a standby state.
285 static void e1000_standby_nvm(struct e1000_hw *hw)
287 struct e1000_nvm_info *nvm = &hw->nvm;
288 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
290 DEBUGFUNC("e1000_standby_nvm");
292 if (nvm->type == e1000_nvm_eeprom_spi) {
293 /* Toggle CS to flush commands */
294 eecd |= E1000_EECD_CS;
295 E1000_WRITE_REG(hw, E1000_EECD, eecd);
296 E1000_WRITE_FLUSH(hw);
297 usec_delay(nvm->delay_usec);
298 eecd &= ~E1000_EECD_CS;
299 E1000_WRITE_REG(hw, E1000_EECD, eecd);
300 E1000_WRITE_FLUSH(hw);
301 usec_delay(nvm->delay_usec);
306 * e1000_stop_nvm - Terminate EEPROM command
307 * @hw: pointer to the HW structure
309 * Terminates the current command by inverting the EEPROM's chip select pin.
311 static void e1000_stop_nvm(struct e1000_hw *hw)
315 DEBUGFUNC("e1000_stop_nvm");
317 eecd = E1000_READ_REG(hw, E1000_EECD);
318 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
320 eecd |= E1000_EECD_CS;
321 e1000_lower_eec_clk(hw, &eecd);
326 * e1000_release_nvm_generic - Release exclusive access to EEPROM
327 * @hw: pointer to the HW structure
329 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
331 void e1000_release_nvm_generic(struct e1000_hw *hw)
335 DEBUGFUNC("e1000_release_nvm_generic");
339 eecd = E1000_READ_REG(hw, E1000_EECD);
340 eecd &= ~E1000_EECD_REQ;
341 E1000_WRITE_REG(hw, E1000_EECD, eecd);
345 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
346 * @hw: pointer to the HW structure
348 * Setups the EEPROM for reading and writing.
350 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
352 struct e1000_nvm_info *nvm = &hw->nvm;
353 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
356 DEBUGFUNC("e1000_ready_nvm_eeprom");
358 if (nvm->type == e1000_nvm_eeprom_spi) {
359 u16 timeout = NVM_MAX_RETRY_SPI;
361 /* Clear SK and CS */
362 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
363 E1000_WRITE_REG(hw, E1000_EECD, eecd);
364 E1000_WRITE_FLUSH(hw);
367 /* Read "Status Register" repeatedly until the LSB is cleared.
368 * The EEPROM will signal that the command has been completed
369 * by clearing bit 0 of the internal status register. If it's
370 * not cleared within 'timeout', then error out.
373 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
374 hw->nvm.opcode_bits);
375 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
376 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
380 e1000_standby_nvm(hw);
385 DEBUGOUT("SPI NVM Status error\n");
386 return -E1000_ERR_NVM;
390 return E1000_SUCCESS;
394 * e1000_read_nvm_spi - Read EEPROM's using SPI
395 * @hw: pointer to the HW structure
396 * @offset: offset of word in the EEPROM to read
397 * @words: number of words to read
398 * @data: word read from the EEPROM
400 * Reads a 16 bit word from the EEPROM.
402 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
404 struct e1000_nvm_info *nvm = &hw->nvm;
408 u8 read_opcode = NVM_READ_OPCODE_SPI;
410 DEBUGFUNC("e1000_read_nvm_spi");
412 /* A check for invalid values: offset too large, too many words,
413 * and not enough words.
415 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
417 DEBUGOUT("nvm parameter(s) out of bounds\n");
418 return -E1000_ERR_NVM;
421 ret_val = nvm->ops.acquire(hw);
425 ret_val = e1000_ready_nvm_eeprom(hw);
429 e1000_standby_nvm(hw);
431 if ((nvm->address_bits == 8) && (offset >= 128))
432 read_opcode |= NVM_A8_OPCODE_SPI;
434 /* Send the READ command (opcode + addr) */
435 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
436 e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
438 /* Read the data. SPI NVMs increment the address with each byte
439 * read and will roll over if reading beyond the end. This allows
440 * us to read the whole NVM from any offset
442 for (i = 0; i < words; i++) {
443 word_in = e1000_shift_in_eec_bits(hw, 16);
444 data[i] = (word_in >> 8) | (word_in << 8);
448 nvm->ops.release(hw);
454 * e1000_read_nvm_eerd - Reads EEPROM using EERD register
455 * @hw: pointer to the HW structure
456 * @offset: offset of word in the EEPROM to read
457 * @words: number of words to read
458 * @data: word read from the EEPROM
460 * Reads a 16 bit word from the EEPROM using the EERD register.
462 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
464 struct e1000_nvm_info *nvm = &hw->nvm;
466 s32 ret_val = E1000_SUCCESS;
468 DEBUGFUNC("e1000_read_nvm_eerd");
470 /* A check for invalid values: offset too large, too many words,
471 * too many words for the offset, and not enough words.
473 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
475 DEBUGOUT("nvm parameter(s) out of bounds\n");
476 return -E1000_ERR_NVM;
479 for (i = 0; i < words; i++) {
480 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
481 E1000_NVM_RW_REG_START;
483 E1000_WRITE_REG(hw, E1000_EERD, eerd);
484 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
488 data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
489 E1000_NVM_RW_REG_DATA);
496 * e1000_write_nvm_spi - Write to EEPROM using SPI
497 * @hw: pointer to the HW structure
498 * @offset: offset within the EEPROM to be written to
499 * @words: number of words to write
500 * @data: 16 bit word(s) to be written to the EEPROM
502 * Writes data to EEPROM at offset using SPI interface.
504 * If e1000_update_nvm_checksum is not called after this function , the
505 * EEPROM will most likely contain an invalid checksum.
507 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
509 struct e1000_nvm_info *nvm = &hw->nvm;
510 s32 ret_val = -E1000_ERR_NVM;
513 DEBUGFUNC("e1000_write_nvm_spi");
515 /* A check for invalid values: offset too large, too many words,
516 * and not enough words.
518 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
520 DEBUGOUT("nvm parameter(s) out of bounds\n");
521 return -E1000_ERR_NVM;
524 while (widx < words) {
525 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
527 ret_val = nvm->ops.acquire(hw);
531 ret_val = e1000_ready_nvm_eeprom(hw);
533 nvm->ops.release(hw);
537 e1000_standby_nvm(hw);
539 /* Send the WRITE ENABLE command (8 bit opcode) */
540 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
543 e1000_standby_nvm(hw);
545 /* Some SPI eeproms use the 8th address bit embedded in the
548 if ((nvm->address_bits == 8) && (offset >= 128))
549 write_opcode |= NVM_A8_OPCODE_SPI;
551 /* Send the Write command (8-bit opcode + addr) */
552 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
553 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
556 /* Loop to allow for up to whole page write of eeprom */
557 while (widx < words) {
558 u16 word_out = data[widx];
559 word_out = (word_out >> 8) | (word_out << 8);
560 e1000_shift_out_eec_bits(hw, word_out, 16);
563 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
564 e1000_standby_nvm(hw);
569 nvm->ops.release(hw);
576 * e1000_read_pba_string_generic - Read device part number
577 * @hw: pointer to the HW structure
578 * @pba_num: pointer to device part number
579 * @pba_num_size: size of part number buffer
581 * Reads the product board assembly (PBA) number from the EEPROM and stores
582 * the value in pba_num.
584 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
593 DEBUGFUNC("e1000_read_pba_string_generic");
595 if (pba_num == NULL) {
596 DEBUGOUT("PBA string buffer was null\n");
597 return -E1000_ERR_INVALID_ARGUMENT;
600 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
602 DEBUGOUT("NVM Read Error\n");
606 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
608 DEBUGOUT("NVM Read Error\n");
612 /* if nvm_data is not ptr guard the PBA must be in legacy format which
613 * means pba_ptr is actually our second data word for the PBA number
614 * and we can decode it into an ascii string
616 if (nvm_data != NVM_PBA_PTR_GUARD) {
617 DEBUGOUT("NVM PBA number is not stored as string\n");
619 /* make sure callers buffer is big enough to store the PBA */
620 if (pba_num_size < E1000_PBANUM_LENGTH) {
621 DEBUGOUT("PBA string buffer too small\n");
622 return E1000_ERR_NO_SPACE;
625 /* extract hex string from data and pba_ptr */
626 pba_num[0] = (nvm_data >> 12) & 0xF;
627 pba_num[1] = (nvm_data >> 8) & 0xF;
628 pba_num[2] = (nvm_data >> 4) & 0xF;
629 pba_num[3] = nvm_data & 0xF;
630 pba_num[4] = (pba_ptr >> 12) & 0xF;
631 pba_num[5] = (pba_ptr >> 8) & 0xF;
634 pba_num[8] = (pba_ptr >> 4) & 0xF;
635 pba_num[9] = pba_ptr & 0xF;
637 /* put a null character on the end of our string */
640 /* switch all the data but the '-' to hex char */
641 for (offset = 0; offset < 10; offset++) {
642 if (pba_num[offset] < 0xA)
643 pba_num[offset] += '0';
644 else if (pba_num[offset] < 0x10)
645 pba_num[offset] += 'A' - 0xA;
648 return E1000_SUCCESS;
651 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
653 DEBUGOUT("NVM Read Error\n");
657 if (length == 0xFFFF || length == 0) {
658 DEBUGOUT("NVM PBA number section invalid length\n");
659 return -E1000_ERR_NVM_PBA_SECTION;
661 /* check if pba_num buffer is big enough */
662 if (pba_num_size < (((u32)length * 2) - 1)) {
663 DEBUGOUT("PBA string buffer too small\n");
664 return -E1000_ERR_NO_SPACE;
667 /* trim pba length from start of string */
671 for (offset = 0; offset < length; offset++) {
672 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
674 DEBUGOUT("NVM Read Error\n");
677 pba_num[offset * 2] = (u8)(nvm_data >> 8);
678 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
680 pba_num[offset * 2] = '\0';
682 return E1000_SUCCESS;
686 * e1000_read_pba_length_generic - Read device part number length
687 * @hw: pointer to the HW structure
688 * @pba_num_size: size of part number buffer
690 * Reads the product board assembly (PBA) number length from the EEPROM and
691 * stores the value in pba_num_size.
693 s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size)
700 DEBUGFUNC("e1000_read_pba_length_generic");
702 if (pba_num_size == NULL) {
703 DEBUGOUT("PBA buffer size was null\n");
704 return -E1000_ERR_INVALID_ARGUMENT;
707 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
709 DEBUGOUT("NVM Read Error\n");
713 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
715 DEBUGOUT("NVM Read Error\n");
719 /* if data is not ptr guard the PBA must be in legacy format */
720 if (nvm_data != NVM_PBA_PTR_GUARD) {
721 *pba_num_size = E1000_PBANUM_LENGTH;
722 return E1000_SUCCESS;
725 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
727 DEBUGOUT("NVM Read Error\n");
731 if (length == 0xFFFF || length == 0) {
732 DEBUGOUT("NVM PBA number section invalid length\n");
733 return -E1000_ERR_NVM_PBA_SECTION;
736 /* Convert from length in u16 values to u8 chars, add 1 for NULL,
737 * and subtract 2 because length field is included in length.
739 *pba_num_size = ((u32)length * 2) - 1;
741 return E1000_SUCCESS;
749 * e1000_read_mac_addr_generic - Read device MAC address
750 * @hw: pointer to the HW structure
752 * Reads the device MAC address from the EEPROM and stores the value.
753 * Since devices with two ports use the same EEPROM, we increment the
754 * last bit in the MAC address for the second port.
756 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
762 rar_high = E1000_READ_REG(hw, E1000_RAH(0));
763 rar_low = E1000_READ_REG(hw, E1000_RAL(0));
765 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
766 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
768 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
769 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
771 for (i = 0; i < ETH_ADDR_LEN; i++)
772 hw->mac.addr[i] = hw->mac.perm_addr[i];
774 return E1000_SUCCESS;
778 * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
779 * @hw: pointer to the HW structure
781 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
782 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
784 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
790 DEBUGFUNC("e1000_validate_nvm_checksum_generic");
792 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
793 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
795 DEBUGOUT("NVM Read Error\n");
798 checksum += nvm_data;
801 if (checksum != (u16) NVM_SUM) {
802 DEBUGOUT("NVM Checksum Invalid\n");
803 return -E1000_ERR_NVM;
806 return E1000_SUCCESS;
810 * e1000_update_nvm_checksum_generic - Update EEPROM checksum
811 * @hw: pointer to the HW structure
813 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
814 * up to the checksum. Then calculates the EEPROM checksum and writes the
815 * value to the EEPROM.
817 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
823 DEBUGFUNC("e1000_update_nvm_checksum");
825 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
826 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
828 DEBUGOUT("NVM Read Error while updating checksum.\n");
831 checksum += nvm_data;
833 checksum = (u16) NVM_SUM - checksum;
834 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
836 DEBUGOUT("NVM Write Error while updating checksum.\n");
842 * e1000_reload_nvm_generic - Reloads EEPROM
843 * @hw: pointer to the HW structure
845 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
846 * extended control register.
848 static void e1000_reload_nvm_generic(struct e1000_hw *hw)
852 DEBUGFUNC("e1000_reload_nvm_generic");
855 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
856 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
857 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
858 E1000_WRITE_FLUSH(hw);
862 * e1000_get_fw_version - Get firmware version information
863 * @hw: pointer to the HW structure
864 * @fw_vers: pointer to output version structure
866 * unsupported/not present features return 0 in version structure
868 void e1000_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers)
870 u16 eeprom_verh, eeprom_verl, etrack_test, fw_version;
871 u8 q, hval, rem, result;
872 u16 comb_verh, comb_verl, comb_offset;
874 memset(fw_vers, 0, sizeof(struct e1000_fw_version));
876 /* basic eeprom version numbers, bits used vary by part and by tool
877 * used to create the nvm images */
878 /* Check which data format we have */
879 hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
880 switch (hw->mac.type) {
882 e1000_read_invm_version(hw, fw_vers);
887 /* Use this format, unless EETRACK ID exists,
888 * then use alternate format
890 if ((etrack_test & NVM_MAJOR_MASK) != NVM_ETRACK_VALID) {
891 hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
892 fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
894 fw_vers->eep_minor = (fw_version & NVM_MINOR_MASK)
896 fw_vers->eep_build = (fw_version & NVM_IMAGE_ID_MASK);
901 if (!(e1000_get_flash_presence_i210(hw))) {
902 e1000_read_invm_version(hw, fw_vers);
908 /* find combo image version */
909 hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset);
910 if ((comb_offset != 0x0) &&
911 (comb_offset != NVM_VER_INVALID)) {
913 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset
914 + 1), 1, &comb_verh);
915 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset),
918 /* get Option Rom version if it exists and is valid */
919 if ((comb_verh && comb_verl) &&
920 ((comb_verh != NVM_VER_INVALID) &&
921 (comb_verl != NVM_VER_INVALID))) {
923 fw_vers->or_valid = true;
925 comb_verl >> NVM_COMB_VER_SHFT;
927 (comb_verl << NVM_COMB_VER_SHFT)
928 | (comb_verh >> NVM_COMB_VER_SHFT);
930 comb_verh & NVM_COMB_VER_MASK;
937 hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
938 fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
941 /* check for old style version format in newer images*/
942 if ((fw_version & NVM_NEW_DEC_MASK) == 0x0) {
943 eeprom_verl = (fw_version & NVM_COMB_VER_MASK);
945 eeprom_verl = (fw_version & NVM_MINOR_MASK)
948 /* Convert minor value to hex before assigning to output struct
949 * Val to be converted will not be higher than 99, per tool output
951 q = eeprom_verl / NVM_HEX_CONV;
952 hval = q * NVM_HEX_TENS;
953 rem = eeprom_verl % NVM_HEX_CONV;
955 fw_vers->eep_minor = result;
958 if ((etrack_test & NVM_MAJOR_MASK) == NVM_ETRACK_VALID) {
959 hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl);
960 hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh);
961 fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT)