1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
29 /* glue for the OS independent part of e1000
30 * includes register access macros
33 #ifndef _E1000_OSDEP_H_
34 #define _E1000_OSDEP_H_
36 #include <linux/pci.h>
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/if_ether.h>
40 #include <linux/sched.h>
43 #ifndef __INTEL_COMPILER
44 #pragma GCC diagnostic ignored "-Wunused-function"
47 #define usec_delay(x) udelay(x)
49 #define msec_delay(x) do { \
50 /* Don't mdelay in interrupt context! */ \
57 /* Some workarounds require millisecond delays and are run during interrupt
58 * context. Most notably, when establishing link, the phy may need tweaking
59 * but cannot process phy register reads/writes faster than millisecond
60 * intervals...and we establish link due to a "link status change" interrupt.
62 #define msec_delay_irq(x) mdelay(x)
65 #define PCI_COMMAND_REGISTER PCI_COMMAND
66 #define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE
67 #define ETH_ADDR_LEN ETH_ALEN
70 #define E1000_BIG_ENDIAN __BIG_ENDIAN
75 #define DEBUGOUT1(S, A...)
78 #define DEBUGOUT2 DEBUGOUT1
79 #define DEBUGOUT3 DEBUGOUT2
80 #define DEBUGOUT7 DEBUGOUT3
82 #define E1000_REGISTER(a, reg) reg
84 #define E1000_WRITE_REG(a, reg, value) ( \
85 writel((value), ((a)->hw_addr + E1000_REGISTER(a, reg))))
87 #define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_REGISTER(a, reg)))
89 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
90 writel((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 2))))
92 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \
93 readl((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 2)))
95 #define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
96 #define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
98 #define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \
99 writew((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 1))))
101 #define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \
102 readw((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 1)))
104 #define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \
105 writeb((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + (offset))))
107 #define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \
108 readb((a)->hw_addr + E1000_REGISTER(a, reg) + (offset)))
110 #define E1000_WRITE_REG_IO(a, reg, offset) do { \
111 outl(reg, ((a)->io_base)); \
112 outl(offset, ((a)->io_base + 4)); } while (0)
114 #define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS)
116 #define E1000_WRITE_FLASH_REG(a, reg, value) ( \
117 writel((value), ((a)->flash_address + reg)))
119 #define E1000_WRITE_FLASH_REG16(a, reg, value) ( \
120 writew((value), ((a)->flash_address + reg)))
122 #define E1000_READ_FLASH_REG(a, reg) (readl((a)->flash_address + reg))
124 #define E1000_READ_FLASH_REG16(a, reg) (readw((a)->flash_address + reg))
126 #endif /* _E1000_OSDEP_H_ */