1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include "e1000_api.h"
30 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
31 /* Cable length tables */
32 static const u16 e1000_m88_cable_length_table[] = {
33 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
34 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
35 (sizeof(e1000_m88_cable_length_table) / \
36 sizeof(e1000_m88_cable_length_table[0]))
38 static const u16 e1000_igp_2_cable_length_table[] = {
39 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
40 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
41 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
42 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
43 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
44 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
45 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
47 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
48 (sizeof(e1000_igp_2_cable_length_table) / \
49 sizeof(e1000_igp_2_cable_length_table[0]))
52 * e1000_init_phy_ops_generic - Initialize PHY function pointers
53 * @hw: pointer to the HW structure
55 * Setups up the function pointers to no-op functions
57 void e1000_init_phy_ops_generic(struct e1000_hw *hw)
59 struct e1000_phy_info *phy = &hw->phy;
60 DEBUGFUNC("e1000_init_phy_ops_generic");
62 /* Initialize function pointers */
63 phy->ops.init_params = e1000_null_ops_generic;
64 phy->ops.acquire = e1000_null_ops_generic;
65 phy->ops.check_polarity = e1000_null_ops_generic;
66 phy->ops.check_reset_block = e1000_null_ops_generic;
67 phy->ops.commit = e1000_null_ops_generic;
68 phy->ops.force_speed_duplex = e1000_null_ops_generic;
69 phy->ops.get_cfg_done = e1000_null_ops_generic;
70 phy->ops.get_cable_length = e1000_null_ops_generic;
71 phy->ops.get_info = e1000_null_ops_generic;
72 phy->ops.set_page = e1000_null_set_page;
73 phy->ops.read_reg = e1000_null_read_reg;
74 phy->ops.read_reg_locked = e1000_null_read_reg;
75 phy->ops.read_reg_page = e1000_null_read_reg;
76 phy->ops.release = e1000_null_phy_generic;
77 phy->ops.reset = e1000_null_ops_generic;
78 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
79 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
80 phy->ops.write_reg = e1000_null_write_reg;
81 phy->ops.write_reg_locked = e1000_null_write_reg;
82 phy->ops.write_reg_page = e1000_null_write_reg;
83 phy->ops.power_up = e1000_null_phy_generic;
84 phy->ops.power_down = e1000_null_phy_generic;
85 phy->ops.read_i2c_byte = e1000_read_i2c_byte_null;
86 phy->ops.write_i2c_byte = e1000_write_i2c_byte_null;
90 * e1000_null_set_page - No-op function, return 0
91 * @hw: pointer to the HW structure
93 s32 e1000_null_set_page(struct e1000_hw E1000_UNUSEDARG *hw,
94 u16 E1000_UNUSEDARG data)
96 DEBUGFUNC("e1000_null_set_page");
101 * e1000_null_read_reg - No-op function, return 0
102 * @hw: pointer to the HW structure
104 s32 e1000_null_read_reg(struct e1000_hw E1000_UNUSEDARG *hw,
105 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG *data)
107 DEBUGFUNC("e1000_null_read_reg");
108 return E1000_SUCCESS;
112 * e1000_null_phy_generic - No-op function, return void
113 * @hw: pointer to the HW structure
115 void e1000_null_phy_generic(struct e1000_hw E1000_UNUSEDARG *hw)
117 DEBUGFUNC("e1000_null_phy_generic");
122 * e1000_null_lplu_state - No-op function, return 0
123 * @hw: pointer to the HW structure
125 s32 e1000_null_lplu_state(struct e1000_hw E1000_UNUSEDARG *hw,
126 bool E1000_UNUSEDARG active)
128 DEBUGFUNC("e1000_null_lplu_state");
129 return E1000_SUCCESS;
133 * e1000_null_write_reg - No-op function, return 0
134 * @hw: pointer to the HW structure
136 s32 e1000_null_write_reg(struct e1000_hw E1000_UNUSEDARG *hw,
137 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG data)
139 DEBUGFUNC("e1000_null_write_reg");
140 return E1000_SUCCESS;
144 * e1000_read_i2c_byte_null - No-op function, return 0
145 * @hw: pointer to hardware structure
146 * @byte_offset: byte offset to write
147 * @dev_addr: device address
148 * @data: data value read
151 s32 e1000_read_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
152 u8 E1000_UNUSEDARG byte_offset,
153 u8 E1000_UNUSEDARG dev_addr,
154 u8 E1000_UNUSEDARG *data)
156 DEBUGFUNC("e1000_read_i2c_byte_null");
157 return E1000_SUCCESS;
161 * e1000_write_i2c_byte_null - No-op function, return 0
162 * @hw: pointer to hardware structure
163 * @byte_offset: byte offset to write
164 * @dev_addr: device address
165 * @data: data value to write
168 s32 e1000_write_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
169 u8 E1000_UNUSEDARG byte_offset,
170 u8 E1000_UNUSEDARG dev_addr,
171 u8 E1000_UNUSEDARG data)
173 DEBUGFUNC("e1000_write_i2c_byte_null");
174 return E1000_SUCCESS;
178 * e1000_check_reset_block_generic - Check if PHY reset is blocked
179 * @hw: pointer to the HW structure
181 * Read the PHY management control register and check whether a PHY reset
182 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
183 * return E1000_BLK_PHY_RESET (12).
185 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
189 DEBUGFUNC("e1000_check_reset_block");
191 manc = E1000_READ_REG(hw, E1000_MANC);
193 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
194 E1000_BLK_PHY_RESET : E1000_SUCCESS;
198 * e1000_get_phy_id - Retrieve the PHY ID and revision
199 * @hw: pointer to the HW structure
201 * Reads the PHY registers and stores the PHY ID and possibly the PHY
202 * revision in the hardware structure.
204 s32 e1000_get_phy_id(struct e1000_hw *hw)
206 struct e1000_phy_info *phy = &hw->phy;
207 s32 ret_val = E1000_SUCCESS;
210 DEBUGFUNC("e1000_get_phy_id");
212 if (!phy->ops.read_reg)
213 return E1000_SUCCESS;
215 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
219 phy->id = (u32)(phy_id << 16);
221 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
225 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
226 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
229 return E1000_SUCCESS;
233 * e1000_phy_reset_dsp_generic - Reset PHY DSP
234 * @hw: pointer to the HW structure
236 * Reset the digital signal processor.
238 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
242 DEBUGFUNC("e1000_phy_reset_dsp_generic");
244 if (!hw->phy.ops.write_reg)
245 return E1000_SUCCESS;
247 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
251 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
255 * e1000_read_phy_reg_mdic - Read MDI control register
256 * @hw: pointer to the HW structure
257 * @offset: register offset to be read
258 * @data: pointer to the read data
260 * Reads the MDI control register in the PHY at offset and stores the
261 * information read to data.
263 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
265 struct e1000_phy_info *phy = &hw->phy;
268 DEBUGFUNC("e1000_read_phy_reg_mdic");
270 if (offset > MAX_PHY_REG_ADDRESS) {
271 DEBUGOUT1("PHY Address %d is out of range\n", offset);
272 return -E1000_ERR_PARAM;
275 /* Set up Op-code, Phy Address, and register offset in the MDI
276 * Control register. The MAC will take care of interfacing with the
277 * PHY to retrieve the desired data.
279 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
280 (phy->addr << E1000_MDIC_PHY_SHIFT) |
281 (E1000_MDIC_OP_READ));
283 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
285 /* Poll the ready bit to see if the MDI read completed
286 * Increasing the time out as testing showed failures with
289 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
291 mdic = E1000_READ_REG(hw, E1000_MDIC);
292 if (mdic & E1000_MDIC_READY)
295 if (!(mdic & E1000_MDIC_READY)) {
296 DEBUGOUT("MDI Read did not complete\n");
297 return -E1000_ERR_PHY;
299 if (mdic & E1000_MDIC_ERROR) {
300 DEBUGOUT("MDI Error\n");
301 return -E1000_ERR_PHY;
303 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
304 DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n",
306 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
307 return -E1000_ERR_PHY;
311 return E1000_SUCCESS;
315 * e1000_write_phy_reg_mdic - Write MDI control register
316 * @hw: pointer to the HW structure
317 * @offset: register offset to write to
318 * @data: data to write to register at offset
320 * Writes data to MDI control register in the PHY at offset.
322 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
324 struct e1000_phy_info *phy = &hw->phy;
327 DEBUGFUNC("e1000_write_phy_reg_mdic");
329 if (offset > MAX_PHY_REG_ADDRESS) {
330 DEBUGOUT1("PHY Address %d is out of range\n", offset);
331 return -E1000_ERR_PARAM;
334 /* Set up Op-code, Phy Address, and register offset in the MDI
335 * Control register. The MAC will take care of interfacing with the
336 * PHY to retrieve the desired data.
338 mdic = (((u32)data) |
339 (offset << E1000_MDIC_REG_SHIFT) |
340 (phy->addr << E1000_MDIC_PHY_SHIFT) |
341 (E1000_MDIC_OP_WRITE));
343 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
345 /* Poll the ready bit to see if the MDI read completed
346 * Increasing the time out as testing showed failures with
349 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
351 mdic = E1000_READ_REG(hw, E1000_MDIC);
352 if (mdic & E1000_MDIC_READY)
355 if (!(mdic & E1000_MDIC_READY)) {
356 DEBUGOUT("MDI Write did not complete\n");
357 return -E1000_ERR_PHY;
359 if (mdic & E1000_MDIC_ERROR) {
360 DEBUGOUT("MDI Error\n");
361 return -E1000_ERR_PHY;
363 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
364 DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n",
366 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
367 return -E1000_ERR_PHY;
370 return E1000_SUCCESS;
374 * e1000_read_phy_reg_i2c - Read PHY register using i2c
375 * @hw: pointer to the HW structure
376 * @offset: register offset to be read
377 * @data: pointer to the read data
379 * Reads the PHY register at offset using the i2c interface and stores the
380 * retrieved information in data.
382 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
384 struct e1000_phy_info *phy = &hw->phy;
387 DEBUGFUNC("e1000_read_phy_reg_i2c");
389 /* Set up Op-code, Phy Address, and register address in the I2CCMD
390 * register. The MAC will take care of interfacing with the
391 * PHY to retrieve the desired data.
393 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
394 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
395 (E1000_I2CCMD_OPCODE_READ));
397 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
399 /* Poll the ready bit to see if the I2C read completed */
400 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
402 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
403 if (i2ccmd & E1000_I2CCMD_READY)
406 if (!(i2ccmd & E1000_I2CCMD_READY)) {
407 DEBUGOUT("I2CCMD Read did not complete\n");
408 return -E1000_ERR_PHY;
410 if (i2ccmd & E1000_I2CCMD_ERROR) {
411 DEBUGOUT("I2CCMD Error bit set\n");
412 return -E1000_ERR_PHY;
415 /* Need to byte-swap the 16-bit value. */
416 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
418 return E1000_SUCCESS;
422 * e1000_write_phy_reg_i2c - Write PHY register using i2c
423 * @hw: pointer to the HW structure
424 * @offset: register offset to write to
425 * @data: data to write at register offset
427 * Writes the data to PHY register at the offset using the i2c interface.
429 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
431 struct e1000_phy_info *phy = &hw->phy;
433 u16 phy_data_swapped;
435 DEBUGFUNC("e1000_write_phy_reg_i2c");
437 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/
438 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
439 DEBUGOUT1("PHY I2C Address %d is out of range.\n",
441 return -E1000_ERR_CONFIG;
444 /* Swap the data bytes for the I2C interface */
445 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
447 /* Set up Op-code, Phy Address, and register address in the I2CCMD
448 * register. The MAC will take care of interfacing with the
449 * PHY to retrieve the desired data.
451 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
452 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
453 E1000_I2CCMD_OPCODE_WRITE |
456 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
458 /* Poll the ready bit to see if the I2C read completed */
459 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
461 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
462 if (i2ccmd & E1000_I2CCMD_READY)
465 if (!(i2ccmd & E1000_I2CCMD_READY)) {
466 DEBUGOUT("I2CCMD Write did not complete\n");
467 return -E1000_ERR_PHY;
469 if (i2ccmd & E1000_I2CCMD_ERROR) {
470 DEBUGOUT("I2CCMD Error bit set\n");
471 return -E1000_ERR_PHY;
474 return E1000_SUCCESS;
478 * e1000_read_sfp_data_byte - Reads SFP module data.
479 * @hw: pointer to the HW structure
480 * @offset: byte location offset to be read
481 * @data: read data buffer pointer
483 * Reads one byte from SFP module data stored
484 * in SFP resided EEPROM memory or SFP diagnostic area.
485 * Function should be called with
486 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
487 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
490 s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
496 DEBUGFUNC("e1000_read_sfp_data_byte");
498 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
499 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
500 return -E1000_ERR_PHY;
503 /* Set up Op-code, EEPROM Address,in the I2CCMD
504 * register. The MAC will take care of interfacing with the
505 * EEPROM to retrieve the desired data.
507 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
508 E1000_I2CCMD_OPCODE_READ);
510 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
512 /* Poll the ready bit to see if the I2C read completed */
513 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
515 data_local = E1000_READ_REG(hw, E1000_I2CCMD);
516 if (data_local & E1000_I2CCMD_READY)
519 if (!(data_local & E1000_I2CCMD_READY)) {
520 DEBUGOUT("I2CCMD Read did not complete\n");
521 return -E1000_ERR_PHY;
523 if (data_local & E1000_I2CCMD_ERROR) {
524 DEBUGOUT("I2CCMD Error bit set\n");
525 return -E1000_ERR_PHY;
527 *data = (u8) data_local & 0xFF;
529 return E1000_SUCCESS;
533 * e1000_write_sfp_data_byte - Writes SFP module data.
534 * @hw: pointer to the HW structure
535 * @offset: byte location offset to write to
536 * @data: data to write
538 * Writes one byte to SFP module data stored
539 * in SFP resided EEPROM memory or SFP diagnostic area.
540 * Function should be called with
541 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
542 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
545 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data)
551 DEBUGFUNC("e1000_write_sfp_data_byte");
553 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
554 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
555 return -E1000_ERR_PHY;
557 /* The programming interface is 16 bits wide
558 * so we need to read the whole word first
559 * then update appropriate byte lane and write
560 * the updated word back.
562 /* Set up Op-code, EEPROM Address,in the I2CCMD
563 * register. The MAC will take care of interfacing
564 * with an EEPROM to write the data given.
566 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
567 E1000_I2CCMD_OPCODE_READ);
568 /* Set a command to read single word */
569 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
570 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
572 /* Poll the ready bit to see if lastly
573 * launched I2C operation completed
575 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
576 if (i2ccmd & E1000_I2CCMD_READY) {
577 /* Check if this is READ or WRITE phase */
578 if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) ==
579 E1000_I2CCMD_OPCODE_READ) {
580 /* Write the selected byte
581 * lane and update whole word
583 data_local = i2ccmd & 0xFF00;
586 E1000_I2CCMD_REG_ADDR_SHIFT) |
587 E1000_I2CCMD_OPCODE_WRITE | data_local);
588 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
594 if (!(i2ccmd & E1000_I2CCMD_READY)) {
595 DEBUGOUT("I2CCMD Write did not complete\n");
596 return -E1000_ERR_PHY;
598 if (i2ccmd & E1000_I2CCMD_ERROR) {
599 DEBUGOUT("I2CCMD Error bit set\n");
600 return -E1000_ERR_PHY;
602 return E1000_SUCCESS;
606 * e1000_read_phy_reg_m88 - Read m88 PHY register
607 * @hw: pointer to the HW structure
608 * @offset: register offset to be read
609 * @data: pointer to the read data
611 * Acquires semaphore, if necessary, then reads the PHY register at offset
612 * and storing the retrieved information in data. Release any acquired
613 * semaphores before exiting.
615 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
619 DEBUGFUNC("e1000_read_phy_reg_m88");
621 if (!hw->phy.ops.acquire)
622 return E1000_SUCCESS;
624 ret_val = hw->phy.ops.acquire(hw);
628 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
631 hw->phy.ops.release(hw);
637 * e1000_write_phy_reg_m88 - Write m88 PHY register
638 * @hw: pointer to the HW structure
639 * @offset: register offset to write to
640 * @data: data to write at register offset
642 * Acquires semaphore, if necessary, then writes the data to PHY register
643 * at the offset. Release any acquired semaphores before exiting.
645 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
649 DEBUGFUNC("e1000_write_phy_reg_m88");
651 if (!hw->phy.ops.acquire)
652 return E1000_SUCCESS;
654 ret_val = hw->phy.ops.acquire(hw);
658 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
661 hw->phy.ops.release(hw);
667 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
668 * @hw: pointer to the HW structure
669 * @page: page to set (shifted left when necessary)
671 * Sets PHY page required for PHY register access. Assumes semaphore is
672 * already acquired. Note, this function sets phy.addr to 1 so the caller
673 * must set it appropriately (if necessary) after this function returns.
675 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
677 DEBUGFUNC("e1000_set_page_igp");
679 DEBUGOUT1("Setting page 0x%x\n", page);
683 return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
687 * __e1000_read_phy_reg_igp - Read igp PHY register
688 * @hw: pointer to the HW structure
689 * @offset: register offset to be read
690 * @data: pointer to the read data
691 * @locked: semaphore has already been acquired or not
693 * Acquires semaphore, if necessary, then reads the PHY register at offset
694 * and stores the retrieved information in data. Release any acquired
695 * semaphores before exiting.
697 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
700 s32 ret_val = E1000_SUCCESS;
702 DEBUGFUNC("__e1000_read_phy_reg_igp");
705 if (!hw->phy.ops.acquire)
706 return E1000_SUCCESS;
708 ret_val = hw->phy.ops.acquire(hw);
713 if (offset > MAX_PHY_MULTI_PAGE_REG)
714 ret_val = e1000_write_phy_reg_mdic(hw,
715 IGP01E1000_PHY_PAGE_SELECT,
718 ret_val = e1000_read_phy_reg_mdic(hw,
719 MAX_PHY_REG_ADDRESS & offset,
722 hw->phy.ops.release(hw);
728 * e1000_read_phy_reg_igp - Read igp PHY register
729 * @hw: pointer to the HW structure
730 * @offset: register offset to be read
731 * @data: pointer to the read data
733 * Acquires semaphore then reads the PHY register at offset and stores the
734 * retrieved information in data.
735 * Release the acquired semaphore before exiting.
737 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
739 return __e1000_read_phy_reg_igp(hw, offset, data, false);
743 * e1000_read_phy_reg_igp_locked - Read igp PHY register
744 * @hw: pointer to the HW structure
745 * @offset: register offset to be read
746 * @data: pointer to the read data
748 * Reads the PHY register at offset and stores the retrieved information
749 * in data. Assumes semaphore already acquired.
751 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
753 return __e1000_read_phy_reg_igp(hw, offset, data, true);
757 * e1000_write_phy_reg_igp - Write igp PHY register
758 * @hw: pointer to the HW structure
759 * @offset: register offset to write to
760 * @data: data to write at register offset
761 * @locked: semaphore has already been acquired or not
763 * Acquires semaphore, if necessary, then writes the data to PHY register
764 * at the offset. Release any acquired semaphores before exiting.
766 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
769 s32 ret_val = E1000_SUCCESS;
771 DEBUGFUNC("e1000_write_phy_reg_igp");
774 if (!hw->phy.ops.acquire)
775 return E1000_SUCCESS;
777 ret_val = hw->phy.ops.acquire(hw);
782 if (offset > MAX_PHY_MULTI_PAGE_REG)
783 ret_val = e1000_write_phy_reg_mdic(hw,
784 IGP01E1000_PHY_PAGE_SELECT,
787 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
791 hw->phy.ops.release(hw);
797 * e1000_write_phy_reg_igp - Write igp PHY register
798 * @hw: pointer to the HW structure
799 * @offset: register offset to write to
800 * @data: data to write at register offset
802 * Acquires semaphore then writes the data to PHY register
803 * at the offset. Release any acquired semaphores before exiting.
805 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
807 return __e1000_write_phy_reg_igp(hw, offset, data, false);
811 * e1000_write_phy_reg_igp_locked - Write igp PHY register
812 * @hw: pointer to the HW structure
813 * @offset: register offset to write to
814 * @data: data to write at register offset
816 * Writes the data to PHY register at the offset.
817 * Assumes semaphore already acquired.
819 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
821 return __e1000_write_phy_reg_igp(hw, offset, data, true);
825 * __e1000_read_kmrn_reg - Read kumeran register
826 * @hw: pointer to the HW structure
827 * @offset: register offset to be read
828 * @data: pointer to the read data
829 * @locked: semaphore has already been acquired or not
831 * Acquires semaphore, if necessary. Then reads the PHY register at offset
832 * using the kumeran interface. The information retrieved is stored in data.
833 * Release any acquired semaphores before exiting.
835 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
840 DEBUGFUNC("__e1000_read_kmrn_reg");
843 s32 ret_val = E1000_SUCCESS;
845 if (!hw->phy.ops.acquire)
846 return E1000_SUCCESS;
848 ret_val = hw->phy.ops.acquire(hw);
853 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
854 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
855 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
856 E1000_WRITE_FLUSH(hw);
860 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
861 *data = (u16)kmrnctrlsta;
864 hw->phy.ops.release(hw);
866 return E1000_SUCCESS;
870 * e1000_read_kmrn_reg_generic - Read kumeran register
871 * @hw: pointer to the HW structure
872 * @offset: register offset to be read
873 * @data: pointer to the read data
875 * Acquires semaphore then reads the PHY register at offset using the
876 * kumeran interface. The information retrieved is stored in data.
877 * Release the acquired semaphore before exiting.
879 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
881 return __e1000_read_kmrn_reg(hw, offset, data, false);
885 * e1000_read_kmrn_reg_locked - Read kumeran register
886 * @hw: pointer to the HW structure
887 * @offset: register offset to be read
888 * @data: pointer to the read data
890 * Reads the PHY register at offset using the kumeran interface. The
891 * information retrieved is stored in data.
892 * Assumes semaphore already acquired.
894 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
896 return __e1000_read_kmrn_reg(hw, offset, data, true);
900 * __e1000_write_kmrn_reg - Write kumeran register
901 * @hw: pointer to the HW structure
902 * @offset: register offset to write to
903 * @data: data to write at register offset
904 * @locked: semaphore has already been acquired or not
906 * Acquires semaphore, if necessary. Then write the data to PHY register
907 * at the offset using the kumeran interface. Release any acquired semaphores
910 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
915 DEBUGFUNC("e1000_write_kmrn_reg_generic");
918 s32 ret_val = E1000_SUCCESS;
920 if (!hw->phy.ops.acquire)
921 return E1000_SUCCESS;
923 ret_val = hw->phy.ops.acquire(hw);
928 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
929 E1000_KMRNCTRLSTA_OFFSET) | data;
930 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
931 E1000_WRITE_FLUSH(hw);
936 hw->phy.ops.release(hw);
938 return E1000_SUCCESS;
942 * e1000_write_kmrn_reg_generic - Write kumeran register
943 * @hw: pointer to the HW structure
944 * @offset: register offset to write to
945 * @data: data to write at register offset
947 * Acquires semaphore then writes the data to the PHY register at the offset
948 * using the kumeran interface. Release the acquired semaphore before exiting.
950 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
952 return __e1000_write_kmrn_reg(hw, offset, data, false);
956 * e1000_write_kmrn_reg_locked - Write kumeran register
957 * @hw: pointer to the HW structure
958 * @offset: register offset to write to
959 * @data: data to write at register offset
961 * Write the data to PHY register at the offset using the kumeran interface.
962 * Assumes semaphore already acquired.
964 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
966 return __e1000_write_kmrn_reg(hw, offset, data, true);
970 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
971 * @hw: pointer to the HW structure
973 * Sets up Master/slave mode
975 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
980 /* Resolve Master/Slave mode */
981 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
985 /* load defaults for future use */
986 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
987 ((phy_data & CR_1000T_MS_VALUE) ?
988 e1000_ms_force_master :
989 e1000_ms_force_slave) : e1000_ms_auto;
991 switch (hw->phy.ms_type) {
992 case e1000_ms_force_master:
993 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
995 case e1000_ms_force_slave:
996 phy_data |= CR_1000T_MS_ENABLE;
997 phy_data &= ~(CR_1000T_MS_VALUE);
1000 phy_data &= ~CR_1000T_MS_ENABLE;
1006 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
1010 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
1011 * @hw: pointer to the HW structure
1013 * Sets up Carrier-sense on Transmit and downshift values.
1015 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
1020 DEBUGFUNC("e1000_copper_link_setup_82577");
1022 if (hw->phy.reset_disable)
1023 return E1000_SUCCESS;
1025 if (hw->phy.type == e1000_phy_82580) {
1026 ret_val = hw->phy.ops.reset(hw);
1028 DEBUGOUT("Error resetting the PHY.\n");
1033 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1034 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
1038 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
1040 /* Enable downshift */
1041 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
1043 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
1047 /* Set MDI/MDIX mode */
1048 ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
1051 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
1053 * 0 - Auto (default)
1057 switch (hw->phy.mdix) {
1061 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
1065 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
1068 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
1072 return e1000_set_master_slave_mode(hw);
1076 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
1077 * @hw: pointer to the HW structure
1079 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
1080 * and downshift values are set also.
1082 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
1084 struct e1000_phy_info *phy = &hw->phy;
1088 DEBUGFUNC("e1000_copper_link_setup_m88");
1090 if (phy->reset_disable)
1091 return E1000_SUCCESS;
1093 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1094 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1098 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1101 * MDI/MDI-X = 0 (default)
1102 * 0 - Auto for all speeds
1105 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1107 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1109 switch (phy->mdix) {
1111 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1114 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1117 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1121 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1126 * disable_polarity_correction = 0 (default)
1127 * Automatic Correction for Reversed Cable Polarity
1131 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1132 if (phy->disable_polarity_correction)
1133 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1135 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1139 if (phy->revision < E1000_REVISION_4) {
1140 /* Force TX_CLK in the Extended PHY Specific Control Register
1143 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1148 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1150 if ((phy->revision == E1000_REVISION_2) &&
1151 (phy->id == M88E1111_I_PHY_ID)) {
1152 /* 82573L PHY - set the downshift counter to 5x. */
1153 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
1154 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1156 /* Configure Master and Slave downshift values */
1157 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1158 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1159 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1160 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1162 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1168 /* Commit the changes. */
1169 ret_val = phy->ops.commit(hw);
1171 DEBUGOUT("Error committing the PHY changes\n");
1175 return E1000_SUCCESS;
1179 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
1180 * @hw: pointer to the HW structure
1182 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
1183 * Also enables and sets the downshift parameters.
1185 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)
1187 struct e1000_phy_info *phy = &hw->phy;
1191 DEBUGFUNC("e1000_copper_link_setup_m88_gen2");
1193 if (phy->reset_disable)
1194 return E1000_SUCCESS;
1196 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1197 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1202 * MDI/MDI-X = 0 (default)
1203 * 0 - Auto for all speeds
1206 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1208 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1210 switch (phy->mdix) {
1212 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1215 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1218 /* M88E1112 does not support this mode) */
1219 if (phy->id != M88E1112_E_PHY_ID) {
1220 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1225 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1230 * disable_polarity_correction = 0 (default)
1231 * Automatic Correction for Reversed Cable Polarity
1235 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1236 if (phy->disable_polarity_correction)
1237 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1239 /* Enable downshift and setting it to X6 */
1240 if (phy->id == M88E1543_E_PHY_ID) {
1241 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;
1243 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1247 ret_val = phy->ops.commit(hw);
1249 DEBUGOUT("Error committing the PHY changes\n");
1254 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
1255 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
1256 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
1258 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1262 /* Commit the changes. */
1263 ret_val = phy->ops.commit(hw);
1265 DEBUGOUT("Error committing the PHY changes\n");
1269 ret_val = e1000_set_master_slave_mode(hw);
1273 return E1000_SUCCESS;
1277 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
1278 * @hw: pointer to the HW structure
1280 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
1283 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
1285 struct e1000_phy_info *phy = &hw->phy;
1289 DEBUGFUNC("e1000_copper_link_setup_igp");
1291 if (phy->reset_disable)
1292 return E1000_SUCCESS;
1294 ret_val = hw->phy.ops.reset(hw);
1296 DEBUGOUT("Error resetting the PHY.\n");
1300 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1301 * timeout issues when LFS is enabled.
1305 /* disable lplu d0 during driver init */
1306 if (hw->phy.ops.set_d0_lplu_state) {
1307 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
1309 DEBUGOUT("Error Disabling LPLU D0\n");
1313 /* Configure mdi-mdix settings */
1314 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1318 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1320 switch (phy->mdix) {
1322 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1325 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1329 data |= IGP01E1000_PSCR_AUTO_MDIX;
1332 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1336 /* set auto-master slave resolution settings */
1337 if (hw->mac.autoneg) {
1338 /* when autonegotiation advertisement is only 1000Mbps then we
1339 * should disable SmartSpeed and enable Auto MasterSlave
1340 * resolution as hardware default.
1342 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1343 /* Disable SmartSpeed */
1344 ret_val = phy->ops.read_reg(hw,
1345 IGP01E1000_PHY_PORT_CONFIG,
1350 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1351 ret_val = phy->ops.write_reg(hw,
1352 IGP01E1000_PHY_PORT_CONFIG,
1357 /* Set auto Master/Slave resolution process */
1358 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1362 data &= ~CR_1000T_MS_ENABLE;
1363 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1368 ret_val = e1000_set_master_slave_mode(hw);
1375 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1376 * @hw: pointer to the HW structure
1378 * Reads the MII auto-neg advertisement register and/or the 1000T control
1379 * register and if the PHY is already setup for auto-negotiation, then
1380 * return successful. Otherwise, setup advertisement and flow control to
1381 * the appropriate values for the wanted auto-negotiation.
1383 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1385 struct e1000_phy_info *phy = &hw->phy;
1387 u16 mii_autoneg_adv_reg;
1388 u16 mii_1000t_ctrl_reg = 0;
1390 DEBUGFUNC("e1000_phy_setup_autoneg");
1392 phy->autoneg_advertised &= phy->autoneg_mask;
1394 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1395 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1399 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1400 /* Read the MII 1000Base-T Control Register (Address 9). */
1401 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1402 &mii_1000t_ctrl_reg);
1407 /* Need to parse both autoneg_advertised and fc and set up
1408 * the appropriate PHY registers. First we will parse for
1409 * autoneg_advertised software override. Since we can advertise
1410 * a plethora of combinations, we need to check each bit
1414 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1415 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1416 * the 1000Base-T Control Register (Address 9).
1418 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1419 NWAY_AR_100TX_HD_CAPS |
1420 NWAY_AR_10T_FD_CAPS |
1421 NWAY_AR_10T_HD_CAPS);
1422 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1424 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1426 /* Do we want to advertise 10 Mb Half Duplex? */
1427 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1428 DEBUGOUT("Advertise 10mb Half duplex\n");
1429 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1432 /* Do we want to advertise 10 Mb Full Duplex? */
1433 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1434 DEBUGOUT("Advertise 10mb Full duplex\n");
1435 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1438 /* Do we want to advertise 100 Mb Half Duplex? */
1439 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1440 DEBUGOUT("Advertise 100mb Half duplex\n");
1441 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1444 /* Do we want to advertise 100 Mb Full Duplex? */
1445 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1446 DEBUGOUT("Advertise 100mb Full duplex\n");
1447 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1450 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1451 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1452 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1454 /* Do we want to advertise 1000 Mb Full Duplex? */
1455 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1456 DEBUGOUT("Advertise 1000mb Full duplex\n");
1457 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1460 /* Check for a software override of the flow control settings, and
1461 * setup the PHY advertisement registers accordingly. If
1462 * auto-negotiation is enabled, then software will have to set the
1463 * "PAUSE" bits to the correct value in the Auto-Negotiation
1464 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1467 * The possible values of the "fc" parameter are:
1468 * 0: Flow control is completely disabled
1469 * 1: Rx flow control is enabled (we can receive pause frames
1470 * but not send pause frames).
1471 * 2: Tx flow control is enabled (we can send pause frames
1472 * but we do not support receiving pause frames).
1473 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1474 * other: No software override. The flow control configuration
1475 * in the EEPROM is used.
1477 switch (hw->fc.current_mode) {
1479 /* Flow control (Rx & Tx) is completely disabled by a
1480 * software over-ride.
1482 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1484 case e1000_fc_rx_pause:
1485 /* Rx Flow control is enabled, and Tx Flow control is
1486 * disabled, by a software over-ride.
1488 * Since there really isn't a way to advertise that we are
1489 * capable of Rx Pause ONLY, we will advertise that we
1490 * support both symmetric and asymmetric Rx PAUSE. Later
1491 * (in e1000_config_fc_after_link_up) we will disable the
1492 * hw's ability to send PAUSE frames.
1494 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1496 case e1000_fc_tx_pause:
1497 /* Tx Flow control is enabled, and Rx Flow control is
1498 * disabled, by a software over-ride.
1500 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1501 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1504 /* Flow control (both Rx and Tx) is enabled by a software
1507 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1510 DEBUGOUT("Flow control param set incorrectly\n");
1511 return -E1000_ERR_CONFIG;
1514 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1518 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1520 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1521 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
1522 mii_1000t_ctrl_reg);
1528 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1529 * @hw: pointer to the HW structure
1531 * Performs initial bounds checking on autoneg advertisement parameter, then
1532 * configure to advertise the full capability. Setup the PHY to autoneg
1533 * and restart the negotiation process between the link partner. If
1534 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1536 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1538 struct e1000_phy_info *phy = &hw->phy;
1542 DEBUGFUNC("e1000_copper_link_autoneg");
1544 /* Perform some bounds checking on the autoneg advertisement
1547 phy->autoneg_advertised &= phy->autoneg_mask;
1549 /* If autoneg_advertised is zero, we assume it was not defaulted
1550 * by the calling code so we set to advertise full capability.
1552 if (!phy->autoneg_advertised)
1553 phy->autoneg_advertised = phy->autoneg_mask;
1555 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1556 ret_val = e1000_phy_setup_autoneg(hw);
1558 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1561 DEBUGOUT("Restarting Auto-Neg\n");
1563 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1564 * the Auto Neg Restart bit in the PHY control register.
1566 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1570 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1571 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1575 /* Does the user want to wait for Auto-Neg to complete here, or
1576 * check at a later time (for example, callback routine).
1578 if (phy->autoneg_wait_to_complete) {
1579 ret_val = e1000_wait_autoneg(hw);
1581 DEBUGOUT("Error while waiting for autoneg to complete\n");
1586 hw->mac.get_link_status = true;
1592 * e1000_setup_copper_link_generic - Configure copper link settings
1593 * @hw: pointer to the HW structure
1595 * Calls the appropriate function to configure the link for auto-neg or forced
1596 * speed and duplex. Then we check for link, once link is established calls
1597 * to configure collision distance and flow control are called. If link is
1598 * not established, we return -E1000_ERR_PHY (-2).
1600 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1605 DEBUGFUNC("e1000_setup_copper_link_generic");
1607 if (hw->mac.autoneg) {
1608 /* Setup autoneg and flow control advertisement and perform
1611 ret_val = e1000_copper_link_autoneg(hw);
1615 /* PHY will be set to 10H, 10F, 100H or 100F
1616 * depending on user settings.
1618 DEBUGOUT("Forcing Speed and Duplex\n");
1619 ret_val = hw->phy.ops.force_speed_duplex(hw);
1621 DEBUGOUT("Error Forcing Speed and Duplex\n");
1626 /* Check link status. Wait up to 100 microseconds for link to become
1629 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1635 DEBUGOUT("Valid link established!!!\n");
1636 hw->mac.ops.config_collision_dist(hw);
1637 ret_val = e1000_config_fc_after_link_up_generic(hw);
1639 DEBUGOUT("Unable to establish link!!!\n");
1646 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1647 * @hw: pointer to the HW structure
1649 * Calls the PHY setup function to force speed and duplex. Clears the
1650 * auto-crossover to force MDI manually. Waits for link and returns
1651 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1653 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1655 struct e1000_phy_info *phy = &hw->phy;
1660 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1662 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1666 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1668 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1672 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1673 * forced whenever speed and duplex are forced.
1675 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1679 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1680 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1682 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1686 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1690 if (phy->autoneg_wait_to_complete) {
1691 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1693 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1699 DEBUGOUT("Link taking longer than expected.\n");
1702 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1710 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1711 * @hw: pointer to the HW structure
1713 * Calls the PHY setup function to force speed and duplex. Clears the
1714 * auto-crossover to force MDI manually. Resets the PHY to commit the
1715 * changes. If time expires while waiting for link up, we reset the DSP.
1716 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1717 * successful completion, else return corresponding error code.
1719 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1721 struct e1000_phy_info *phy = &hw->phy;
1726 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1728 /* I210 and I211 devices support Auto-Crossover in forced operation. */
1729 if (phy->type != e1000_phy_i210) {
1730 /* Clear Auto-Crossover to force MDI manually. M88E1000
1731 * requires MDI forced whenever speed and duplex are forced.
1733 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1738 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1739 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1745 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1747 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1751 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1753 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1757 /* Reset the phy to commit changes. */
1758 ret_val = hw->phy.ops.commit(hw);
1762 if (phy->autoneg_wait_to_complete) {
1763 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1765 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1771 bool reset_dsp = true;
1773 switch (hw->phy.id) {
1774 case I347AT4_E_PHY_ID:
1775 case M88E1340M_E_PHY_ID:
1776 case M88E1112_E_PHY_ID:
1777 case M88E1543_E_PHY_ID:
1782 if (hw->phy.type != e1000_phy_m88)
1788 DEBUGOUT("Link taking longer than expected.\n");
1790 /* We didn't get link.
1791 * Reset the DSP and cross our fingers.
1793 ret_val = phy->ops.write_reg(hw,
1794 M88E1000_PHY_PAGE_SELECT,
1798 ret_val = e1000_phy_reset_dsp_generic(hw);
1805 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1811 if (hw->phy.type != e1000_phy_m88)
1812 return E1000_SUCCESS;
1814 if (hw->phy.id == I347AT4_E_PHY_ID ||
1815 hw->phy.id == M88E1340M_E_PHY_ID ||
1816 hw->phy.id == M88E1112_E_PHY_ID)
1817 return E1000_SUCCESS;
1818 if (hw->phy.id == I210_I_PHY_ID)
1819 return E1000_SUCCESS;
1820 if ((hw->phy.id == M88E1543_E_PHY_ID))
1821 return E1000_SUCCESS;
1822 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1826 /* Resetting the phy means we need to re-force TX_CLK in the
1827 * Extended PHY Specific Control Register to 25MHz clock from
1828 * the reset value of 2.5MHz.
1830 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1831 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1835 /* In addition, we must re-enable CRS on Tx for both half and full
1838 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1842 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1843 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1849 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1850 * @hw: pointer to the HW structure
1852 * Forces the speed and duplex settings of the PHY.
1853 * This is a function pointer entry point only called by
1854 * PHY setup routines.
1856 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1858 struct e1000_phy_info *phy = &hw->phy;
1863 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1865 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1869 e1000_phy_force_speed_duplex_setup(hw, &data);
1871 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1875 /* Disable MDI-X support for 10/100 */
1876 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1880 data &= ~IFE_PMC_AUTO_MDIX;
1881 data &= ~IFE_PMC_FORCE_MDIX;
1883 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1887 DEBUGOUT1("IFE PMC: %X\n", data);
1891 if (phy->autoneg_wait_to_complete) {
1892 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1894 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1900 DEBUGOUT("Link taking longer than expected.\n");
1903 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1909 return E1000_SUCCESS;
1913 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1914 * @hw: pointer to the HW structure
1915 * @phy_ctrl: pointer to current value of PHY_CONTROL
1917 * Forces speed and duplex on the PHY by doing the following: disable flow
1918 * control, force speed/duplex on the MAC, disable auto speed detection,
1919 * disable auto-negotiation, configure duplex, configure speed, configure
1920 * the collision distance, write configuration to CTRL register. The
1921 * caller must write to the PHY_CONTROL register for these settings to
1924 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1926 struct e1000_mac_info *mac = &hw->mac;
1929 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
1931 /* Turn off flow control when forcing speed/duplex */
1932 hw->fc.current_mode = e1000_fc_none;
1934 /* Force speed/duplex on the mac */
1935 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1936 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1937 ctrl &= ~E1000_CTRL_SPD_SEL;
1939 /* Disable Auto Speed Detection */
1940 ctrl &= ~E1000_CTRL_ASDE;
1942 /* Disable autoneg on the phy */
1943 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1945 /* Forcing Full or Half Duplex? */
1946 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1947 ctrl &= ~E1000_CTRL_FD;
1948 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1949 DEBUGOUT("Half Duplex\n");
1951 ctrl |= E1000_CTRL_FD;
1952 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1953 DEBUGOUT("Full Duplex\n");
1956 /* Forcing 10mb or 100mb? */
1957 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1958 ctrl |= E1000_CTRL_SPD_100;
1959 *phy_ctrl |= MII_CR_SPEED_100;
1960 *phy_ctrl &= ~MII_CR_SPEED_1000;
1961 DEBUGOUT("Forcing 100mb\n");
1963 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1964 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1965 DEBUGOUT("Forcing 10mb\n");
1968 hw->mac.ops.config_collision_dist(hw);
1970 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1974 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
1975 * @hw: pointer to the HW structure
1976 * @active: boolean used to enable/disable lplu
1978 * Success returns 0, Failure returns 1
1980 * The low power link up (lplu) state is set to the power management level D3
1981 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1982 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1983 * is used during Dx states where the power conservation is most important.
1984 * During driver activity, SmartSpeed should be enabled so performance is
1987 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
1989 struct e1000_phy_info *phy = &hw->phy;
1993 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
1995 if (!hw->phy.ops.read_reg)
1996 return E1000_SUCCESS;
1998 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
2003 data &= ~IGP02E1000_PM_D3_LPLU;
2004 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2008 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
2009 * during Dx states where the power conservation is most
2010 * important. During driver activity we should enable
2011 * SmartSpeed, so performance is maintained.
2013 if (phy->smart_speed == e1000_smart_speed_on) {
2014 ret_val = phy->ops.read_reg(hw,
2015 IGP01E1000_PHY_PORT_CONFIG,
2020 data |= IGP01E1000_PSCFR_SMART_SPEED;
2021 ret_val = phy->ops.write_reg(hw,
2022 IGP01E1000_PHY_PORT_CONFIG,
2026 } else if (phy->smart_speed == e1000_smart_speed_off) {
2027 ret_val = phy->ops.read_reg(hw,
2028 IGP01E1000_PHY_PORT_CONFIG,
2033 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2034 ret_val = phy->ops.write_reg(hw,
2035 IGP01E1000_PHY_PORT_CONFIG,
2040 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2041 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2042 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2043 data |= IGP02E1000_PM_D3_LPLU;
2044 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2049 /* When LPLU is enabled, we should disable SmartSpeed */
2050 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2055 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2056 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2064 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
2065 * @hw: pointer to the HW structure
2067 * Success returns 0, Failure returns 1
2069 * A downshift is detected by querying the PHY link health.
2071 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
2073 struct e1000_phy_info *phy = &hw->phy;
2075 u16 phy_data, offset, mask;
2077 DEBUGFUNC("e1000_check_downshift_generic");
2079 switch (phy->type) {
2080 case e1000_phy_i210:
2082 case e1000_phy_gg82563:
2083 offset = M88E1000_PHY_SPEC_STATUS;
2084 mask = M88E1000_PSSR_DOWNSHIFT;
2086 case e1000_phy_igp_2:
2087 case e1000_phy_igp_3:
2088 offset = IGP01E1000_PHY_LINK_HEALTH;
2089 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
2092 /* speed downshift not supported */
2093 phy->speed_downgraded = false;
2094 return E1000_SUCCESS;
2097 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2100 phy->speed_downgraded = !!(phy_data & mask);
2106 * e1000_check_polarity_m88 - Checks the polarity.
2107 * @hw: pointer to the HW structure
2109 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2111 * Polarity is determined based on the PHY specific status register.
2113 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
2115 struct e1000_phy_info *phy = &hw->phy;
2119 DEBUGFUNC("e1000_check_polarity_m88");
2121 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
2124 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
2125 ? e1000_rev_polarity_reversed
2126 : e1000_rev_polarity_normal);
2132 * e1000_check_polarity_igp - Checks the polarity.
2133 * @hw: pointer to the HW structure
2135 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2137 * Polarity is determined based on the PHY port status register, and the
2138 * current speed (since there is no polarity at 100Mbps).
2140 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
2142 struct e1000_phy_info *phy = &hw->phy;
2144 u16 data, offset, mask;
2146 DEBUGFUNC("e1000_check_polarity_igp");
2148 /* Polarity is determined based on the speed of
2151 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2155 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2156 IGP01E1000_PSSR_SPEED_1000MBPS) {
2157 offset = IGP01E1000_PHY_PCS_INIT_REG;
2158 mask = IGP01E1000_PHY_POLARITY_MASK;
2160 /* This really only applies to 10Mbps since
2161 * there is no polarity for 100Mbps (always 0).
2163 offset = IGP01E1000_PHY_PORT_STATUS;
2164 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
2167 ret_val = phy->ops.read_reg(hw, offset, &data);
2170 phy->cable_polarity = ((data & mask)
2171 ? e1000_rev_polarity_reversed
2172 : e1000_rev_polarity_normal);
2178 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
2179 * @hw: pointer to the HW structure
2181 * Polarity is determined on the polarity reversal feature being enabled.
2183 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
2185 struct e1000_phy_info *phy = &hw->phy;
2187 u16 phy_data, offset, mask;
2189 DEBUGFUNC("e1000_check_polarity_ife");
2191 /* Polarity is determined based on the reversal feature being enabled.
2193 if (phy->polarity_correction) {
2194 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
2195 mask = IFE_PESC_POLARITY_REVERSED;
2197 offset = IFE_PHY_SPECIAL_CONTROL;
2198 mask = IFE_PSC_FORCE_POLARITY;
2201 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2204 phy->cable_polarity = ((phy_data & mask)
2205 ? e1000_rev_polarity_reversed
2206 : e1000_rev_polarity_normal);
2212 * e1000_wait_autoneg - Wait for auto-neg completion
2213 * @hw: pointer to the HW structure
2215 * Waits for auto-negotiation to complete or for the auto-negotiation time
2216 * limit to expire, which ever happens first.
2218 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
2220 s32 ret_val = E1000_SUCCESS;
2223 DEBUGFUNC("e1000_wait_autoneg");
2225 if (!hw->phy.ops.read_reg)
2226 return E1000_SUCCESS;
2228 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
2229 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
2230 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2233 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2236 if (phy_status & MII_SR_AUTONEG_COMPLETE)
2241 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
2248 * e1000_phy_has_link_generic - Polls PHY for link
2249 * @hw: pointer to the HW structure
2250 * @iterations: number of times to poll for link
2251 * @usec_interval: delay between polling attempts
2252 * @success: pointer to whether polling was successful or not
2254 * Polls the PHY status register for link, 'iterations' number of times.
2256 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2257 u32 usec_interval, bool *success)
2259 s32 ret_val = E1000_SUCCESS;
2262 DEBUGFUNC("e1000_phy_has_link_generic");
2264 if (!hw->phy.ops.read_reg)
2265 return E1000_SUCCESS;
2267 for (i = 0; i < iterations; i++) {
2268 /* Some PHYs require the PHY_STATUS register to be read
2269 * twice due to the link bit being sticky. No harm doing
2270 * it across the board.
2272 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2274 /* If the first read fails, another entity may have
2275 * ownership of the resources, wait and try again to
2276 * see if they have relinquished the resources yet.
2278 usec_delay(usec_interval);
2279 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2282 if (phy_status & MII_SR_LINK_STATUS)
2284 if (usec_interval >= 1000)
2285 msec_delay_irq(usec_interval/1000);
2287 usec_delay(usec_interval);
2290 *success = (i < iterations);
2296 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2297 * @hw: pointer to the HW structure
2299 * Reads the PHY specific status register to retrieve the cable length
2300 * information. The cable length is determined by averaging the minimum and
2301 * maximum values to get the "average" cable length. The m88 PHY has four
2302 * possible cable length values, which are:
2303 * Register Value Cable Length
2307 * 3 110 - 140 meters
2310 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
2312 struct e1000_phy_info *phy = &hw->phy;
2314 u16 phy_data, index;
2316 DEBUGFUNC("e1000_get_cable_length_m88");
2318 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2322 index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2323 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
2325 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2326 return -E1000_ERR_PHY;
2328 phy->min_cable_length = e1000_m88_cable_length_table[index];
2329 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2331 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2333 return E1000_SUCCESS;
2336 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
2338 struct e1000_phy_info *phy = &hw->phy;
2340 u16 phy_data, phy_data2, is_cm;
2341 u16 index, default_page;
2343 DEBUGFUNC("e1000_get_cable_length_m88_gen2");
2345 switch (hw->phy.id) {
2347 /* Get cable length from PHY Cable Diagnostics Control Reg */
2348 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2349 (I347AT4_PCDL + phy->addr),
2354 /* Check if the unit of cable length is meters or cm */
2355 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2356 I347AT4_PCDC, &phy_data2);
2360 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2362 /* Populate the phy structure with cable length in meters */
2363 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2364 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2365 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2367 case M88E1543_E_PHY_ID:
2368 case M88E1340M_E_PHY_ID:
2369 case I347AT4_E_PHY_ID:
2370 /* Remember the original page select and set it to 7 */
2371 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2376 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2380 /* Get cable length from PHY Cable Diagnostics Control Reg */
2381 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2386 /* Check if the unit of cable length is meters or cm */
2387 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2391 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2393 /* Populate the phy structure with cable length in meters */
2394 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2395 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2396 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2398 /* Reset the page select to its original value */
2399 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2405 case M88E1112_E_PHY_ID:
2406 /* Remember the original page select and set it to 5 */
2407 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2412 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2416 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2421 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2422 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2424 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2425 return -E1000_ERR_PHY;
2427 phy->min_cable_length = e1000_m88_cable_length_table[index];
2428 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2430 phy->cable_length = (phy->min_cable_length +
2431 phy->max_cable_length) / 2;
2433 /* Reset the page select to its original value */
2434 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2441 return -E1000_ERR_PHY;
2448 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2449 * @hw: pointer to the HW structure
2451 * The automatic gain control (agc) normalizes the amplitude of the
2452 * received signal, adjusting for the attenuation produced by the
2453 * cable. By reading the AGC registers, which represent the
2454 * combination of coarse and fine gain value, the value can be put
2455 * into a lookup table to obtain the approximate cable length
2458 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2460 struct e1000_phy_info *phy = &hw->phy;
2462 u16 phy_data, i, agc_value = 0;
2463 u16 cur_agc_index, max_agc_index = 0;
2464 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2465 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
2466 IGP02E1000_PHY_AGC_A,
2467 IGP02E1000_PHY_AGC_B,
2468 IGP02E1000_PHY_AGC_C,
2469 IGP02E1000_PHY_AGC_D
2472 DEBUGFUNC("e1000_get_cable_length_igp_2");
2474 /* Read the AGC registers for all channels */
2475 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
2476 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2480 /* Getting bits 15:9, which represent the combination of
2481 * coarse and fine gain values. The result is a number
2482 * that can be put into the lookup table to obtain the
2483 * approximate cable length.
2485 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
2486 IGP02E1000_AGC_LENGTH_MASK);
2488 /* Array index bound check. */
2489 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
2490 (cur_agc_index == 0))
2491 return -E1000_ERR_PHY;
2493 /* Remove min & max AGC values from calculation. */
2494 if (e1000_igp_2_cable_length_table[min_agc_index] >
2495 e1000_igp_2_cable_length_table[cur_agc_index])
2496 min_agc_index = cur_agc_index;
2497 if (e1000_igp_2_cable_length_table[max_agc_index] <
2498 e1000_igp_2_cable_length_table[cur_agc_index])
2499 max_agc_index = cur_agc_index;
2501 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
2504 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
2505 e1000_igp_2_cable_length_table[max_agc_index]);
2506 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
2508 /* Calculate cable length with the error range of +/- 10 meters. */
2509 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2510 (agc_value - IGP02E1000_AGC_RANGE) : 0);
2511 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2513 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2515 return E1000_SUCCESS;
2519 * e1000_get_phy_info_m88 - Retrieve PHY information
2520 * @hw: pointer to the HW structure
2522 * Valid for only copper links. Read the PHY status register (sticky read)
2523 * to verify that link is up. Read the PHY special control register to
2524 * determine the polarity and 10base-T extended distance. Read the PHY
2525 * special status register to determine MDI/MDIx and current speed. If
2526 * speed is 1000, then determine cable length, local and remote receiver.
2528 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
2530 struct e1000_phy_info *phy = &hw->phy;
2535 DEBUGFUNC("e1000_get_phy_info_m88");
2537 if (phy->media_type != e1000_media_type_copper) {
2538 DEBUGOUT("Phy info is only valid for copper media\n");
2539 return -E1000_ERR_CONFIG;
2542 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2547 DEBUGOUT("Phy info is only valid if link is up\n");
2548 return -E1000_ERR_CONFIG;
2551 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2555 phy->polarity_correction = !!(phy_data &
2556 M88E1000_PSCR_POLARITY_REVERSAL);
2558 ret_val = e1000_check_polarity_m88(hw);
2562 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2566 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
2568 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2569 ret_val = hw->phy.ops.get_cable_length(hw);
2573 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2577 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2578 ? e1000_1000t_rx_status_ok
2579 : e1000_1000t_rx_status_not_ok;
2581 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2582 ? e1000_1000t_rx_status_ok
2583 : e1000_1000t_rx_status_not_ok;
2585 /* Set values to "undefined" */
2586 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2587 phy->local_rx = e1000_1000t_rx_status_undefined;
2588 phy->remote_rx = e1000_1000t_rx_status_undefined;
2595 * e1000_get_phy_info_igp - Retrieve igp PHY information
2596 * @hw: pointer to the HW structure
2598 * Read PHY status to determine if link is up. If link is up, then
2599 * set/determine 10base-T extended distance and polarity correction. Read
2600 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2601 * determine on the cable length, local and remote receiver.
2603 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
2605 struct e1000_phy_info *phy = &hw->phy;
2610 DEBUGFUNC("e1000_get_phy_info_igp");
2612 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2617 DEBUGOUT("Phy info is only valid if link is up\n");
2618 return -E1000_ERR_CONFIG;
2621 phy->polarity_correction = true;
2623 ret_val = e1000_check_polarity_igp(hw);
2627 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2631 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
2633 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2634 IGP01E1000_PSSR_SPEED_1000MBPS) {
2635 ret_val = phy->ops.get_cable_length(hw);
2639 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2643 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2644 ? e1000_1000t_rx_status_ok
2645 : e1000_1000t_rx_status_not_ok;
2647 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2648 ? e1000_1000t_rx_status_ok
2649 : e1000_1000t_rx_status_not_ok;
2651 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2652 phy->local_rx = e1000_1000t_rx_status_undefined;
2653 phy->remote_rx = e1000_1000t_rx_status_undefined;
2660 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2661 * @hw: pointer to the HW structure
2663 * Populates "phy" structure with various feature states.
2665 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2667 struct e1000_phy_info *phy = &hw->phy;
2672 DEBUGFUNC("e1000_get_phy_info_ife");
2674 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2679 DEBUGOUT("Phy info is only valid if link is up\n");
2680 return -E1000_ERR_CONFIG;
2683 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2686 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2688 if (phy->polarity_correction) {
2689 ret_val = e1000_check_polarity_ife(hw);
2693 /* Polarity is forced */
2694 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2695 ? e1000_rev_polarity_reversed
2696 : e1000_rev_polarity_normal);
2699 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2703 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2705 /* The following parameters are undefined for 10/100 operation. */
2706 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2707 phy->local_rx = e1000_1000t_rx_status_undefined;
2708 phy->remote_rx = e1000_1000t_rx_status_undefined;
2710 return E1000_SUCCESS;
2714 * e1000_phy_sw_reset_generic - PHY software reset
2715 * @hw: pointer to the HW structure
2717 * Does a software reset of the PHY by reading the PHY control register and
2718 * setting/write the control register reset bit to the PHY.
2720 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2725 DEBUGFUNC("e1000_phy_sw_reset_generic");
2727 if (!hw->phy.ops.read_reg)
2728 return E1000_SUCCESS;
2730 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2734 phy_ctrl |= MII_CR_RESET;
2735 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2745 * e1000_phy_hw_reset_generic - PHY hardware reset
2746 * @hw: pointer to the HW structure
2748 * Verify the reset block is not blocking us from resetting. Acquire
2749 * semaphore (if necessary) and read/set/write the device control reset
2750 * bit in the PHY. Wait the appropriate delay time for the device to
2751 * reset and release the semaphore (if necessary).
2753 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2755 struct e1000_phy_info *phy = &hw->phy;
2759 DEBUGFUNC("e1000_phy_hw_reset_generic");
2761 if (phy->ops.check_reset_block) {
2762 ret_val = phy->ops.check_reset_block(hw);
2764 return E1000_SUCCESS;
2767 ret_val = phy->ops.acquire(hw);
2771 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2772 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2773 E1000_WRITE_FLUSH(hw);
2775 usec_delay(phy->reset_delay_us);
2777 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2778 E1000_WRITE_FLUSH(hw);
2782 phy->ops.release(hw);
2784 return phy->ops.get_cfg_done(hw);
2788 * e1000_get_cfg_done_generic - Generic configuration done
2789 * @hw: pointer to the HW structure
2791 * Generic function to wait 10 milli-seconds for configuration to complete
2792 * and return success.
2794 s32 e1000_get_cfg_done_generic(struct e1000_hw E1000_UNUSEDARG *hw)
2796 DEBUGFUNC("e1000_get_cfg_done_generic");
2800 return E1000_SUCCESS;
2804 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2805 * @hw: pointer to the HW structure
2807 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2809 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2811 DEBUGOUT("Running IGP 3 PHY init script\n");
2813 /* PHY init IGP 3 */
2814 /* Enable rise/fall, 10-mode work in class-A */
2815 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2816 /* Remove all caps from Replica path filter */
2817 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2818 /* Bias trimming for ADC, AFE and Driver (Default) */
2819 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2820 /* Increase Hybrid poly bias */
2821 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2822 /* Add 4% to Tx amplitude in Gig mode */
2823 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2824 /* Disable trimming (TTT) */
2825 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2826 /* Poly DC correction to 94.6% + 2% for all channels */
2827 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2828 /* ABS DC correction to 95.9% */
2829 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2830 /* BG temp curve trim */
2831 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2832 /* Increasing ADC OPAMP stage 1 currents to max */
2833 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2834 /* Force 1000 ( required for enabling PHY regs configuration) */
2835 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2836 /* Set upd_freq to 6 */
2837 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2839 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2840 /* Disable adaptive fixed FFE (Default) */
2841 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2842 /* Enable FFE hysteresis */
2843 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2844 /* Fixed FFE for short cable lengths */
2845 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2846 /* Fixed FFE for medium cable lengths */
2847 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2848 /* Fixed FFE for long cable lengths */
2849 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2850 /* Enable Adaptive Clip Threshold */
2851 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2852 /* AHT reset limit to 1 */
2853 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2854 /* Set AHT master delay to 127 msec */
2855 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2856 /* Set scan bits for AHT */
2857 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2858 /* Set AHT Preset bits */
2859 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2860 /* Change integ_factor of channel A to 3 */
2861 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2862 /* Change prop_factor of channels BCD to 8 */
2863 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2864 /* Change cg_icount + enable integbp for channels BCD */
2865 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2866 /* Change cg_icount + enable integbp + change prop_factor_master
2867 * to 8 for channel A
2869 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2870 /* Disable AHT in Slave mode on channel A */
2871 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2872 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2875 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2876 /* Enable restart AN on an1000_dis change */
2877 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2878 /* Enable wh_fifo read clock in 10/100 modes */
2879 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2880 /* Restart AN, Speed selection is 1000 */
2881 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2883 return E1000_SUCCESS;
2887 * e1000_get_phy_type_from_id - Get PHY type from id
2888 * @phy_id: phy_id read from the phy
2890 * Returns the phy type from the id.
2892 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
2894 enum e1000_phy_type phy_type = e1000_phy_unknown;
2897 case M88E1000_I_PHY_ID:
2898 case M88E1000_E_PHY_ID:
2899 case M88E1111_I_PHY_ID:
2900 case M88E1011_I_PHY_ID:
2901 case M88E1543_E_PHY_ID:
2902 case I347AT4_E_PHY_ID:
2903 case M88E1112_E_PHY_ID:
2904 case M88E1340M_E_PHY_ID:
2905 phy_type = e1000_phy_m88;
2907 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2908 phy_type = e1000_phy_igp_2;
2910 case GG82563_E_PHY_ID:
2911 phy_type = e1000_phy_gg82563;
2913 case IGP03E1000_E_PHY_ID:
2914 phy_type = e1000_phy_igp_3;
2917 case IFE_PLUS_E_PHY_ID:
2918 case IFE_C_E_PHY_ID:
2919 phy_type = e1000_phy_ife;
2921 case I82580_I_PHY_ID:
2922 phy_type = e1000_phy_82580;
2925 phy_type = e1000_phy_i210;
2928 phy_type = e1000_phy_unknown;
2935 * e1000_determine_phy_address - Determines PHY address.
2936 * @hw: pointer to the HW structure
2938 * This uses a trial and error method to loop through possible PHY
2939 * addresses. It tests each by reading the PHY ID registers and
2940 * checking for a match.
2942 s32 e1000_determine_phy_address(struct e1000_hw *hw)
2946 enum e1000_phy_type phy_type = e1000_phy_unknown;
2948 hw->phy.id = phy_type;
2950 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2951 hw->phy.addr = phy_addr;
2955 e1000_get_phy_id(hw);
2956 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
2958 /* If phy_type is valid, break - we found our
2961 if (phy_type != e1000_phy_unknown)
2962 return E1000_SUCCESS;
2969 return -E1000_ERR_PHY_TYPE;
2973 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2974 * @hw: pointer to the HW structure
2976 * In the case of a PHY power down to save power, or to turn off link during a
2977 * driver unload, or wake on lan is not enabled, restore the link to previous
2980 void e1000_power_up_phy_copper(struct e1000_hw *hw)
2985 /* The PHY will retain its settings across a power down/up cycle */
2986 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2987 mii_reg &= ~MII_CR_POWER_DOWN;
2988 if (hw->phy.type == e1000_phy_i210) {
2989 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);
2990 power_reg &= ~GS40G_CS_POWER_DOWN;
2991 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);
2993 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2997 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2998 * @hw: pointer to the HW structure
3000 * In the case of a PHY power down to save power, or to turn off link during a
3001 * driver unload, or wake on lan is not enabled, restore the link to previous
3004 void e1000_power_down_phy_copper(struct e1000_hw *hw)
3009 /* The PHY will retain its settings across a power down/up cycle */
3010 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3011 mii_reg |= MII_CR_POWER_DOWN;
3012 /* i210 Phy requires an additional bit for power up/down */
3013 if (hw->phy.type == e1000_phy_i210) {
3014 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);
3015 power_reg |= GS40G_CS_POWER_DOWN;
3016 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);
3018 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3023 * e1000_check_polarity_82577 - Checks the polarity.
3024 * @hw: pointer to the HW structure
3026 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3028 * Polarity is determined based on the PHY specific status register.
3030 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3032 struct e1000_phy_info *phy = &hw->phy;
3036 DEBUGFUNC("e1000_check_polarity_82577");
3038 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3041 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3042 ? e1000_rev_polarity_reversed
3043 : e1000_rev_polarity_normal);
3049 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3050 * @hw: pointer to the HW structure
3052 * Calls the PHY setup function to force speed and duplex.
3054 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3056 struct e1000_phy_info *phy = &hw->phy;
3061 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
3063 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3067 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
3069 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3075 if (phy->autoneg_wait_to_complete) {
3076 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3078 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3084 DEBUGOUT("Link taking longer than expected.\n");
3087 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3095 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3096 * @hw: pointer to the HW structure
3098 * Read PHY status to determine if link is up. If link is up, then
3099 * set/determine 10base-T extended distance and polarity correction. Read
3100 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3101 * determine on the cable length, local and remote receiver.
3103 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3105 struct e1000_phy_info *phy = &hw->phy;
3110 DEBUGFUNC("e1000_get_phy_info_82577");
3112 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3117 DEBUGOUT("Phy info is only valid if link is up\n");
3118 return -E1000_ERR_CONFIG;
3121 phy->polarity_correction = true;
3123 ret_val = e1000_check_polarity_82577(hw);
3127 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3131 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3133 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3134 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3135 ret_val = hw->phy.ops.get_cable_length(hw);
3139 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
3143 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3144 ? e1000_1000t_rx_status_ok
3145 : e1000_1000t_rx_status_not_ok;
3147 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3148 ? e1000_1000t_rx_status_ok
3149 : e1000_1000t_rx_status_not_ok;
3151 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3152 phy->local_rx = e1000_1000t_rx_status_undefined;
3153 phy->remote_rx = e1000_1000t_rx_status_undefined;
3156 return E1000_SUCCESS;
3160 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3161 * @hw: pointer to the HW structure
3163 * Reads the diagnostic status register and verifies result is valid before
3164 * placing it in the phy_cable_length field.
3166 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3168 struct e1000_phy_info *phy = &hw->phy;
3170 u16 phy_data, length;
3172 DEBUGFUNC("e1000_get_cable_length_82577");
3174 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3178 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
3179 I82577_DSTATUS_CABLE_LENGTH_SHIFT);
3181 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3182 return -E1000_ERR_PHY;
3184 phy->cable_length = length;
3186 return E1000_SUCCESS;
3190 * e1000_write_phy_reg_gs40g - Write GS40G PHY register
3191 * @hw: pointer to the HW structure
3192 * @offset: register offset to write to
3193 * @data: data to write at register offset
3195 * Acquires semaphore, if necessary, then writes the data to PHY register
3196 * at the offset. Release any acquired semaphores before exiting.
3198 s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
3201 u16 page = offset >> GS40G_PAGE_SHIFT;
3203 DEBUGFUNC("e1000_write_phy_reg_gs40g");
3205 offset = offset & GS40G_OFFSET_MASK;
3206 ret_val = hw->phy.ops.acquire(hw);
3210 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
3213 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
3216 hw->phy.ops.release(hw);
3221 * e1000_read_phy_reg_gs40g - Read GS40G PHY register
3222 * @hw: pointer to the HW structure
3223 * @offset: lower half is register offset to read to
3224 * upper half is page to use.
3225 * @data: data to read at register offset
3227 * Acquires semaphore, if necessary, then reads the data in the PHY register
3228 * at the offset. Release any acquired semaphores before exiting.
3230 s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
3233 u16 page = offset >> GS40G_PAGE_SHIFT;
3235 DEBUGFUNC("e1000_read_phy_reg_gs40g");
3237 offset = offset & GS40G_OFFSET_MASK;
3238 ret_val = hw->phy.ops.acquire(hw);
3242 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
3245 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
3248 hw->phy.ops.release(hw);
3253 * e1000_read_phy_reg_mphy - Read mPHY control register
3254 * @hw: pointer to the HW structure
3255 * @address: address to be read
3256 * @data: pointer to the read data
3258 * Reads the mPHY control register in the PHY at offset and stores the
3259 * information read to data.
3261 s32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data)
3264 bool locked = false;
3267 DEBUGFUNC("e1000_read_phy_reg_mphy");
3269 /* Check if mPHY is ready to read/write operations */
3270 ready = e1000_is_mphy_ready(hw);
3272 return -E1000_ERR_PHY;
3274 /* Check if mPHY access is disabled and enable it if so */
3275 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
3276 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
3278 ready = e1000_is_mphy_ready(hw);
3280 return -E1000_ERR_PHY;
3281 mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
3282 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
3285 /* Set the address that we want to read */
3286 ready = e1000_is_mphy_ready(hw);
3288 return -E1000_ERR_PHY;
3290 /* We mask address, because we want to use only current lane */
3291 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK &
3292 ~E1000_MPHY_ADDRESS_FNC_OVERRIDE) |
3293 (address & E1000_MPHY_ADDRESS_MASK);
3294 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
3296 /* Read data from the address */
3297 ready = e1000_is_mphy_ready(hw);
3299 return -E1000_ERR_PHY;
3300 *data = E1000_READ_REG(hw, E1000_MPHY_DATA);
3302 /* Disable access to mPHY if it was originally disabled */
3304 ready = e1000_is_mphy_ready(hw);
3306 return -E1000_ERR_PHY;
3307 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
3308 E1000_MPHY_DIS_ACCESS);
3310 return E1000_SUCCESS;
3314 * e1000_write_phy_reg_mphy - Write mPHY control register
3315 * @hw: pointer to the HW structure
3316 * @address: address to write to
3317 * @data: data to write to register at offset
3318 * @line_override: used when we want to use different line than default one
3320 * Writes data to mPHY control register.
3322 s32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data,
3326 bool locked = false;
3329 DEBUGFUNC("e1000_write_phy_reg_mphy");
3331 /* Check if mPHY is ready to read/write operations */
3332 ready = e1000_is_mphy_ready(hw);
3334 return -E1000_ERR_PHY;
3336 /* Check if mPHY access is disabled and enable it if so */
3337 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
3338 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
3340 ready = e1000_is_mphy_ready(hw);
3342 return -E1000_ERR_PHY;
3343 mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
3344 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
3347 /* Set the address that we want to read */
3348 ready = e1000_is_mphy_ready(hw);
3350 return -E1000_ERR_PHY;
3352 /* We mask address, because we want to use only current lane */
3354 mphy_ctrl |= E1000_MPHY_ADDRESS_FNC_OVERRIDE;
3356 mphy_ctrl &= ~E1000_MPHY_ADDRESS_FNC_OVERRIDE;
3357 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK) |
3358 (address & E1000_MPHY_ADDRESS_MASK);
3359 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
3361 /* Read data from the address */
3362 ready = e1000_is_mphy_ready(hw);
3364 return -E1000_ERR_PHY;
3365 E1000_WRITE_REG(hw, E1000_MPHY_DATA, data);
3367 /* Disable access to mPHY if it was originally disabled */
3369 ready = e1000_is_mphy_ready(hw);
3371 return -E1000_ERR_PHY;
3372 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
3373 E1000_MPHY_DIS_ACCESS);
3375 return E1000_SUCCESS;
3379 * e1000_is_mphy_ready - Check if mPHY control register is not busy
3380 * @hw: pointer to the HW structure
3382 * Returns mPHY control register status.
3384 bool e1000_is_mphy_ready(struct e1000_hw *hw)
3386 u16 retry_count = 0;
3390 while (retry_count < 2) {
3391 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
3392 if (mphy_ctrl & E1000_MPHY_BUSY) {
3402 DEBUGOUT("ERROR READING mPHY control register, phy is busy.\n");