1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include "e1000_api.h"
30 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw);
31 /* Cable length tables */
32 static const u16 e1000_m88_cable_length_table[] = {
33 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
34 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
35 (sizeof(e1000_m88_cable_length_table) / \
36 sizeof(e1000_m88_cable_length_table[0]))
38 static const u16 e1000_igp_2_cable_length_table[] = {
39 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
40 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
41 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
42 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
43 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
44 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
45 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
47 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
48 (sizeof(e1000_igp_2_cable_length_table) / \
49 sizeof(e1000_igp_2_cable_length_table[0]))
52 * e1000_init_phy_ops_generic - Initialize PHY function pointers
53 * @hw: pointer to the HW structure
55 * Setups up the function pointers to no-op functions
57 void e1000_init_phy_ops_generic(struct e1000_hw *hw)
59 struct e1000_phy_info *phy = &hw->phy;
60 DEBUGFUNC("e1000_init_phy_ops_generic");
62 /* Initialize function pointers */
63 phy->ops.init_params = e1000_null_ops_generic;
64 phy->ops.acquire = e1000_null_ops_generic;
65 phy->ops.check_polarity = e1000_null_ops_generic;
66 phy->ops.check_reset_block = e1000_null_ops_generic;
67 phy->ops.commit = e1000_null_ops_generic;
68 phy->ops.force_speed_duplex = e1000_null_ops_generic;
69 phy->ops.get_cfg_done = e1000_null_ops_generic;
70 phy->ops.get_cable_length = e1000_null_ops_generic;
71 phy->ops.get_info = e1000_null_ops_generic;
72 phy->ops.set_page = e1000_null_set_page;
73 phy->ops.read_reg = e1000_null_read_reg;
74 phy->ops.read_reg_locked = e1000_null_read_reg;
75 phy->ops.read_reg_page = e1000_null_read_reg;
76 phy->ops.release = e1000_null_phy_generic;
77 phy->ops.reset = e1000_null_ops_generic;
78 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
79 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
80 phy->ops.write_reg = e1000_null_write_reg;
81 phy->ops.write_reg_locked = e1000_null_write_reg;
82 phy->ops.write_reg_page = e1000_null_write_reg;
83 phy->ops.power_up = e1000_null_phy_generic;
84 phy->ops.power_down = e1000_null_phy_generic;
85 phy->ops.read_i2c_byte = e1000_read_i2c_byte_null;
86 phy->ops.write_i2c_byte = e1000_write_i2c_byte_null;
90 * e1000_null_set_page - No-op function, return 0
91 * @hw: pointer to the HW structure
93 s32 e1000_null_set_page(struct e1000_hw *hw, u16 data)
95 DEBUGFUNC("e1000_null_set_page");
100 * e1000_null_read_reg - No-op function, return 0
101 * @hw: pointer to the HW structure
103 s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data)
105 DEBUGFUNC("e1000_null_read_reg");
106 return E1000_SUCCESS;
110 * e1000_null_phy_generic - No-op function, return void
111 * @hw: pointer to the HW structure
113 void e1000_null_phy_generic(struct e1000_hw *hw)
115 DEBUGFUNC("e1000_null_phy_generic");
120 * e1000_null_lplu_state - No-op function, return 0
121 * @hw: pointer to the HW structure
123 s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active)
125 DEBUGFUNC("e1000_null_lplu_state");
126 return E1000_SUCCESS;
130 * e1000_null_write_reg - No-op function, return 0
131 * @hw: pointer to the HW structure
133 s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data)
135 DEBUGFUNC("e1000_null_write_reg");
136 return E1000_SUCCESS;
140 * e1000_read_i2c_byte_null - No-op function, return 0
141 * @hw: pointer to hardware structure
142 * @byte_offset: byte offset to write
143 * @dev_addr: device address
144 * @data: data value read
147 s32 e1000_read_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset,
148 u8 dev_addr, u8 *data)
150 DEBUGFUNC("e1000_read_i2c_byte_null");
151 return E1000_SUCCESS;
155 * e1000_write_i2c_byte_null - No-op function, return 0
156 * @hw: pointer to hardware structure
157 * @byte_offset: byte offset to write
158 * @dev_addr: device address
159 * @data: data value to write
162 s32 e1000_write_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset,
163 u8 dev_addr, u8 data)
165 DEBUGFUNC("e1000_write_i2c_byte_null");
166 return E1000_SUCCESS;
170 * e1000_check_reset_block_generic - Check if PHY reset is blocked
171 * @hw: pointer to the HW structure
173 * Read the PHY management control register and check whether a PHY reset
174 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
175 * return E1000_BLK_PHY_RESET (12).
177 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
181 DEBUGFUNC("e1000_check_reset_block");
183 manc = E1000_READ_REG(hw, E1000_MANC);
185 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
186 E1000_BLK_PHY_RESET : E1000_SUCCESS;
190 * e1000_get_phy_id - Retrieve the PHY ID and revision
191 * @hw: pointer to the HW structure
193 * Reads the PHY registers and stores the PHY ID and possibly the PHY
194 * revision in the hardware structure.
196 s32 e1000_get_phy_id(struct e1000_hw *hw)
198 struct e1000_phy_info *phy = &hw->phy;
199 s32 ret_val = E1000_SUCCESS;
202 DEBUGFUNC("e1000_get_phy_id");
204 if (!phy->ops.read_reg)
205 return E1000_SUCCESS;
207 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
211 phy->id = (u32)(phy_id << 16);
213 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
217 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
218 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
221 return E1000_SUCCESS;
225 * e1000_phy_reset_dsp_generic - Reset PHY DSP
226 * @hw: pointer to the HW structure
228 * Reset the digital signal processor.
230 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
234 DEBUGFUNC("e1000_phy_reset_dsp_generic");
236 if (!hw->phy.ops.write_reg)
237 return E1000_SUCCESS;
239 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
243 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
247 * e1000_read_phy_reg_mdic - Read MDI control register
248 * @hw: pointer to the HW structure
249 * @offset: register offset to be read
250 * @data: pointer to the read data
252 * Reads the MDI control register in the PHY at offset and stores the
253 * information read to data.
255 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
257 struct e1000_phy_info *phy = &hw->phy;
260 DEBUGFUNC("e1000_read_phy_reg_mdic");
262 if (offset > MAX_PHY_REG_ADDRESS) {
263 DEBUGOUT1("PHY Address %d is out of range\n", offset);
264 return -E1000_ERR_PARAM;
268 * Set up Op-code, Phy Address, and register offset in the MDI
269 * Control register. The MAC will take care of interfacing with the
270 * PHY to retrieve the desired data.
272 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
273 (phy->addr << E1000_MDIC_PHY_SHIFT) |
274 (E1000_MDIC_OP_READ));
276 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
279 * Poll the ready bit to see if the MDI read completed
280 * Increasing the time out as testing showed failures with
283 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
285 mdic = E1000_READ_REG(hw, E1000_MDIC);
286 if (mdic & E1000_MDIC_READY)
289 if (!(mdic & E1000_MDIC_READY)) {
290 DEBUGOUT("MDI Read did not complete\n");
291 return -E1000_ERR_PHY;
293 if (mdic & E1000_MDIC_ERROR) {
294 DEBUGOUT("MDI Error\n");
295 return -E1000_ERR_PHY;
299 return E1000_SUCCESS;
303 * e1000_write_phy_reg_mdic - Write MDI control register
304 * @hw: pointer to the HW structure
305 * @offset: register offset to write to
306 * @data: data to write to register at offset
308 * Writes data to MDI control register in the PHY at offset.
310 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
312 struct e1000_phy_info *phy = &hw->phy;
315 DEBUGFUNC("e1000_write_phy_reg_mdic");
317 if (offset > MAX_PHY_REG_ADDRESS) {
318 DEBUGOUT1("PHY Address %d is out of range\n", offset);
319 return -E1000_ERR_PARAM;
323 * Set up Op-code, Phy Address, and register offset in the MDI
324 * Control register. The MAC will take care of interfacing with the
325 * PHY to retrieve the desired data.
327 mdic = (((u32)data) |
328 (offset << E1000_MDIC_REG_SHIFT) |
329 (phy->addr << E1000_MDIC_PHY_SHIFT) |
330 (E1000_MDIC_OP_WRITE));
332 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
335 * Poll the ready bit to see if the MDI read completed
336 * Increasing the time out as testing showed failures with
339 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
341 mdic = E1000_READ_REG(hw, E1000_MDIC);
342 if (mdic & E1000_MDIC_READY)
345 if (!(mdic & E1000_MDIC_READY)) {
346 DEBUGOUT("MDI Write did not complete\n");
347 return -E1000_ERR_PHY;
349 if (mdic & E1000_MDIC_ERROR) {
350 DEBUGOUT("MDI Error\n");
351 return -E1000_ERR_PHY;
354 return E1000_SUCCESS;
358 * e1000_read_phy_reg_i2c - Read PHY register using i2c
359 * @hw: pointer to the HW structure
360 * @offset: register offset to be read
361 * @data: pointer to the read data
363 * Reads the PHY register at offset using the i2c interface and stores the
364 * retrieved information in data.
366 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
368 struct e1000_phy_info *phy = &hw->phy;
371 DEBUGFUNC("e1000_read_phy_reg_i2c");
374 * Set up Op-code, Phy Address, and register address in the I2CCMD
375 * register. The MAC will take care of interfacing with the
376 * PHY to retrieve the desired data.
378 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
379 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
380 (E1000_I2CCMD_OPCODE_READ));
382 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
384 /* Poll the ready bit to see if the I2C read completed */
385 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
387 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
388 if (i2ccmd & E1000_I2CCMD_READY)
391 if (!(i2ccmd & E1000_I2CCMD_READY)) {
392 DEBUGOUT("I2CCMD Read did not complete\n");
393 return -E1000_ERR_PHY;
395 if (i2ccmd & E1000_I2CCMD_ERROR) {
396 DEBUGOUT("I2CCMD Error bit set\n");
397 return -E1000_ERR_PHY;
400 /* Need to byte-swap the 16-bit value. */
401 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
403 return E1000_SUCCESS;
407 * e1000_write_phy_reg_i2c - Write PHY register using i2c
408 * @hw: pointer to the HW structure
409 * @offset: register offset to write to
410 * @data: data to write at register offset
412 * Writes the data to PHY register at the offset using the i2c interface.
414 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
416 struct e1000_phy_info *phy = &hw->phy;
418 u16 phy_data_swapped;
420 DEBUGFUNC("e1000_write_phy_reg_i2c");
422 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/
423 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
424 DEBUGOUT1("PHY I2C Address %d is out of range.\n",
426 return -E1000_ERR_CONFIG;
429 /* Swap the data bytes for the I2C interface */
430 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
433 * Set up Op-code, Phy Address, and register address in the I2CCMD
434 * register. The MAC will take care of interfacing with the
435 * PHY to retrieve the desired data.
437 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
438 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
439 E1000_I2CCMD_OPCODE_WRITE |
442 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
444 /* Poll the ready bit to see if the I2C read completed */
445 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
447 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
448 if (i2ccmd & E1000_I2CCMD_READY)
451 if (!(i2ccmd & E1000_I2CCMD_READY)) {
452 DEBUGOUT("I2CCMD Write did not complete\n");
453 return -E1000_ERR_PHY;
455 if (i2ccmd & E1000_I2CCMD_ERROR) {
456 DEBUGOUT("I2CCMD Error bit set\n");
457 return -E1000_ERR_PHY;
460 return E1000_SUCCESS;
464 * e1000_read_sfp_data_byte - Reads SFP module data.
465 * @hw: pointer to the HW structure
466 * @offset: byte location offset to be read
467 * @data: read data buffer pointer
469 * Reads one byte from SFP module data stored
470 * in SFP resided EEPROM memory or SFP diagnostic area.
471 * Function should be called with
472 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
473 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
476 s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
482 DEBUGFUNC("e1000_read_sfp_data_byte");
484 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
485 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
486 return -E1000_ERR_PHY;
490 * Set up Op-code, EEPROM Address,in the I2CCMD
491 * register. The MAC will take care of interfacing with the
492 * EEPROM to retrieve the desired data.
494 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
495 E1000_I2CCMD_OPCODE_READ);
497 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
499 /* Poll the ready bit to see if the I2C read completed */
500 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
502 data_local = E1000_READ_REG(hw, E1000_I2CCMD);
503 if (data_local & E1000_I2CCMD_READY)
506 if (!(data_local & E1000_I2CCMD_READY)) {
507 DEBUGOUT("I2CCMD Read did not complete\n");
508 return -E1000_ERR_PHY;
510 if (data_local & E1000_I2CCMD_ERROR) {
511 DEBUGOUT("I2CCMD Error bit set\n");
512 return -E1000_ERR_PHY;
514 *data = (u8) data_local & 0xFF;
516 return E1000_SUCCESS;
520 * e1000_write_sfp_data_byte - Writes SFP module data.
521 * @hw: pointer to the HW structure
522 * @offset: byte location offset to write to
523 * @data: data to write
525 * Writes one byte to SFP module data stored
526 * in SFP resided EEPROM memory or SFP diagnostic area.
527 * Function should be called with
528 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
529 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
532 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data)
538 DEBUGFUNC("e1000_write_sfp_data_byte");
540 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
541 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
542 return -E1000_ERR_PHY;
545 * The programming interface is 16 bits wide
546 * so we need to read the whole word first
547 * then update appropriate byte lane and write
548 * the updated word back.
551 * Set up Op-code, EEPROM Address,in the I2CCMD
552 * register. The MAC will take care of interfacing
553 * with an EEPROM to write the data given.
555 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
556 E1000_I2CCMD_OPCODE_READ);
557 /* Set a command to read single word */
558 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
559 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
562 * Poll the ready bit to see if lastly
563 * launched I2C operation completed
565 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
566 if (i2ccmd & E1000_I2CCMD_READY) {
567 /* Check if this is READ or WRITE phase */
568 if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) ==
569 E1000_I2CCMD_OPCODE_READ) {
571 * Write the selected byte
572 * lane and update whole word
574 data_local = i2ccmd & 0xFF00;
577 E1000_I2CCMD_REG_ADDR_SHIFT) |
578 E1000_I2CCMD_OPCODE_WRITE | data_local);
579 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
585 if (!(i2ccmd & E1000_I2CCMD_READY)) {
586 DEBUGOUT("I2CCMD Write did not complete\n");
587 return -E1000_ERR_PHY;
589 if (i2ccmd & E1000_I2CCMD_ERROR) {
590 DEBUGOUT("I2CCMD Error bit set\n");
591 return -E1000_ERR_PHY;
593 return E1000_SUCCESS;
597 * e1000_read_phy_reg_m88 - Read m88 PHY register
598 * @hw: pointer to the HW structure
599 * @offset: register offset to be read
600 * @data: pointer to the read data
602 * Acquires semaphore, if necessary, then reads the PHY register at offset
603 * and storing the retrieved information in data. Release any acquired
604 * semaphores before exiting.
606 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
610 DEBUGFUNC("e1000_read_phy_reg_m88");
612 if (!hw->phy.ops.acquire)
613 return E1000_SUCCESS;
615 ret_val = hw->phy.ops.acquire(hw);
619 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
622 hw->phy.ops.release(hw);
628 * e1000_write_phy_reg_m88 - Write m88 PHY register
629 * @hw: pointer to the HW structure
630 * @offset: register offset to write to
631 * @data: data to write at register offset
633 * Acquires semaphore, if necessary, then writes the data to PHY register
634 * at the offset. Release any acquired semaphores before exiting.
636 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
640 DEBUGFUNC("e1000_write_phy_reg_m88");
642 if (!hw->phy.ops.acquire)
643 return E1000_SUCCESS;
645 ret_val = hw->phy.ops.acquire(hw);
649 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
652 hw->phy.ops.release(hw);
658 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
659 * @hw: pointer to the HW structure
660 * @page: page to set (shifted left when necessary)
662 * Sets PHY page required for PHY register access. Assumes semaphore is
663 * already acquired. Note, this function sets phy.addr to 1 so the caller
664 * must set it appropriately (if necessary) after this function returns.
666 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
668 DEBUGFUNC("e1000_set_page_igp");
670 DEBUGOUT1("Setting page 0x%x\n", page);
674 return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
678 * __e1000_read_phy_reg_igp - Read igp PHY register
679 * @hw: pointer to the HW structure
680 * @offset: register offset to be read
681 * @data: pointer to the read data
682 * @locked: semaphore has already been acquired or not
684 * Acquires semaphore, if necessary, then reads the PHY register at offset
685 * and stores the retrieved information in data. Release any acquired
686 * semaphores before exiting.
688 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
691 s32 ret_val = E1000_SUCCESS;
693 DEBUGFUNC("__e1000_read_phy_reg_igp");
696 if (!hw->phy.ops.acquire)
697 return E1000_SUCCESS;
699 ret_val = hw->phy.ops.acquire(hw);
704 if (offset > MAX_PHY_MULTI_PAGE_REG)
705 ret_val = e1000_write_phy_reg_mdic(hw,
706 IGP01E1000_PHY_PAGE_SELECT,
709 ret_val = e1000_read_phy_reg_mdic(hw,
710 MAX_PHY_REG_ADDRESS & offset,
713 hw->phy.ops.release(hw);
719 * e1000_read_phy_reg_igp - Read igp PHY register
720 * @hw: pointer to the HW structure
721 * @offset: register offset to be read
722 * @data: pointer to the read data
724 * Acquires semaphore then reads the PHY register at offset and stores the
725 * retrieved information in data.
726 * Release the acquired semaphore before exiting.
728 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
730 return __e1000_read_phy_reg_igp(hw, offset, data, false);
734 * e1000_read_phy_reg_igp_locked - Read igp PHY register
735 * @hw: pointer to the HW structure
736 * @offset: register offset to be read
737 * @data: pointer to the read data
739 * Reads the PHY register at offset and stores the retrieved information
740 * in data. Assumes semaphore already acquired.
742 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
744 return __e1000_read_phy_reg_igp(hw, offset, data, true);
748 * e1000_write_phy_reg_igp - Write igp PHY register
749 * @hw: pointer to the HW structure
750 * @offset: register offset to write to
751 * @data: data to write at register offset
752 * @locked: semaphore has already been acquired or not
754 * Acquires semaphore, if necessary, then writes the data to PHY register
755 * at the offset. Release any acquired semaphores before exiting.
757 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
760 s32 ret_val = E1000_SUCCESS;
762 DEBUGFUNC("e1000_write_phy_reg_igp");
765 if (!hw->phy.ops.acquire)
766 return E1000_SUCCESS;
768 ret_val = hw->phy.ops.acquire(hw);
773 if (offset > MAX_PHY_MULTI_PAGE_REG)
774 ret_val = e1000_write_phy_reg_mdic(hw,
775 IGP01E1000_PHY_PAGE_SELECT,
778 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
782 hw->phy.ops.release(hw);
788 * e1000_write_phy_reg_igp - Write igp PHY register
789 * @hw: pointer to the HW structure
790 * @offset: register offset to write to
791 * @data: data to write at register offset
793 * Acquires semaphore then writes the data to PHY register
794 * at the offset. Release any acquired semaphores before exiting.
796 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
798 return __e1000_write_phy_reg_igp(hw, offset, data, false);
802 * e1000_write_phy_reg_igp_locked - Write igp PHY register
803 * @hw: pointer to the HW structure
804 * @offset: register offset to write to
805 * @data: data to write at register offset
807 * Writes the data to PHY register at the offset.
808 * Assumes semaphore already acquired.
810 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
812 return __e1000_write_phy_reg_igp(hw, offset, data, true);
816 * __e1000_read_kmrn_reg - Read kumeran register
817 * @hw: pointer to the HW structure
818 * @offset: register offset to be read
819 * @data: pointer to the read data
820 * @locked: semaphore has already been acquired or not
822 * Acquires semaphore, if necessary. Then reads the PHY register at offset
823 * using the kumeran interface. The information retrieved is stored in data.
824 * Release any acquired semaphores before exiting.
826 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
831 DEBUGFUNC("__e1000_read_kmrn_reg");
834 s32 ret_val = E1000_SUCCESS;
836 if (!hw->phy.ops.acquire)
837 return E1000_SUCCESS;
839 ret_val = hw->phy.ops.acquire(hw);
844 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
845 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
846 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
847 E1000_WRITE_FLUSH(hw);
851 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
852 *data = (u16)kmrnctrlsta;
855 hw->phy.ops.release(hw);
857 return E1000_SUCCESS;
861 * e1000_read_kmrn_reg_generic - Read kumeran register
862 * @hw: pointer to the HW structure
863 * @offset: register offset to be read
864 * @data: pointer to the read data
866 * Acquires semaphore then reads the PHY register at offset using the
867 * kumeran interface. The information retrieved is stored in data.
868 * Release the acquired semaphore before exiting.
870 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
872 return __e1000_read_kmrn_reg(hw, offset, data, false);
876 * e1000_read_kmrn_reg_locked - Read kumeran register
877 * @hw: pointer to the HW structure
878 * @offset: register offset to be read
879 * @data: pointer to the read data
881 * Reads the PHY register at offset using the kumeran interface. The
882 * information retrieved is stored in data.
883 * Assumes semaphore already acquired.
885 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
887 return __e1000_read_kmrn_reg(hw, offset, data, true);
891 * __e1000_write_kmrn_reg - Write kumeran register
892 * @hw: pointer to the HW structure
893 * @offset: register offset to write to
894 * @data: data to write at register offset
895 * @locked: semaphore has already been acquired or not
897 * Acquires semaphore, if necessary. Then write the data to PHY register
898 * at the offset using the kumeran interface. Release any acquired semaphores
901 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
906 DEBUGFUNC("e1000_write_kmrn_reg_generic");
909 s32 ret_val = E1000_SUCCESS;
911 if (!hw->phy.ops.acquire)
912 return E1000_SUCCESS;
914 ret_val = hw->phy.ops.acquire(hw);
919 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
920 E1000_KMRNCTRLSTA_OFFSET) | data;
921 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
922 E1000_WRITE_FLUSH(hw);
927 hw->phy.ops.release(hw);
929 return E1000_SUCCESS;
933 * e1000_write_kmrn_reg_generic - Write kumeran register
934 * @hw: pointer to the HW structure
935 * @offset: register offset to write to
936 * @data: data to write at register offset
938 * Acquires semaphore then writes the data to the PHY register at the offset
939 * using the kumeran interface. Release the acquired semaphore before exiting.
941 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
943 return __e1000_write_kmrn_reg(hw, offset, data, false);
947 * e1000_write_kmrn_reg_locked - Write kumeran register
948 * @hw: pointer to the HW structure
949 * @offset: register offset to write to
950 * @data: data to write at register offset
952 * Write the data to PHY register at the offset using the kumeran interface.
953 * Assumes semaphore already acquired.
955 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
957 return __e1000_write_kmrn_reg(hw, offset, data, true);
961 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
962 * @hw: pointer to the HW structure
964 * Sets up Master/slave mode
966 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
971 /* Resolve Master/Slave mode */
972 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
976 /* load defaults for future use */
977 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
978 ((phy_data & CR_1000T_MS_VALUE) ?
979 e1000_ms_force_master :
980 e1000_ms_force_slave) : e1000_ms_auto;
982 switch (hw->phy.ms_type) {
983 case e1000_ms_force_master:
984 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
986 case e1000_ms_force_slave:
987 phy_data |= CR_1000T_MS_ENABLE;
988 phy_data &= ~(CR_1000T_MS_VALUE);
991 phy_data &= ~CR_1000T_MS_ENABLE;
997 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
1001 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
1002 * @hw: pointer to the HW structure
1004 * Sets up Carrier-sense on Transmit and downshift values.
1006 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
1011 DEBUGFUNC("e1000_copper_link_setup_82577");
1013 if (hw->phy.reset_disable)
1014 return E1000_SUCCESS;
1016 if (hw->phy.type == e1000_phy_82580) {
1017 ret_val = hw->phy.ops.reset(hw);
1019 DEBUGOUT("Error resetting the PHY.\n");
1024 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1025 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
1029 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
1031 /* Enable downshift */
1032 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
1034 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
1038 return e1000_set_master_slave_mode(hw);
1042 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
1043 * @hw: pointer to the HW structure
1045 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
1046 * and downshift values are set also.
1048 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
1050 struct e1000_phy_info *phy = &hw->phy;
1054 DEBUGFUNC("e1000_copper_link_setup_m88");
1056 if (phy->reset_disable)
1057 return E1000_SUCCESS;
1059 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1060 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1064 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1068 * MDI/MDI-X = 0 (default)
1069 * 0 - Auto for all speeds
1072 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1074 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1076 switch (phy->mdix) {
1078 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1081 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1084 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1088 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1094 * disable_polarity_correction = 0 (default)
1095 * Automatic Correction for Reversed Cable Polarity
1099 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1100 if (phy->disable_polarity_correction == 1)
1101 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1103 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1107 if (phy->revision < E1000_REVISION_4) {
1109 * Force TX_CLK in the Extended PHY Specific Control Register
1112 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1117 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1119 if ((phy->revision == E1000_REVISION_2) &&
1120 (phy->id == M88E1111_I_PHY_ID)) {
1121 /* 82573L PHY - set the downshift counter to 5x. */
1122 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
1123 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1125 /* Configure Master and Slave downshift values */
1126 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1127 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1128 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1129 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1131 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1137 /* Commit the changes. */
1138 ret_val = phy->ops.commit(hw);
1140 DEBUGOUT("Error committing the PHY changes\n");
1144 return E1000_SUCCESS;
1148 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
1149 * @hw: pointer to the HW structure
1151 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
1152 * Also enables and sets the downshift parameters.
1154 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)
1156 struct e1000_phy_info *phy = &hw->phy;
1160 DEBUGFUNC("e1000_copper_link_setup_m88_gen2");
1162 if (phy->reset_disable)
1163 return E1000_SUCCESS;
1165 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1166 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1172 * MDI/MDI-X = 0 (default)
1173 * 0 - Auto for all speeds
1176 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1178 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1180 switch (phy->mdix) {
1182 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1185 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1188 /* M88E1112 does not support this mode) */
1189 if (phy->id != M88E1112_E_PHY_ID) {
1190 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1195 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1201 * disable_polarity_correction = 0 (default)
1202 * Automatic Correction for Reversed Cable Polarity
1206 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1207 if (phy->disable_polarity_correction == 1)
1208 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1210 /* Enable downshift and setting it to X6 */
1211 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
1212 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
1213 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
1215 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1219 /* Commit the changes. */
1220 ret_val = phy->ops.commit(hw);
1222 DEBUGOUT("Error committing the PHY changes\n");
1226 return E1000_SUCCESS;
1230 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
1231 * @hw: pointer to the HW structure
1233 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
1236 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
1238 struct e1000_phy_info *phy = &hw->phy;
1242 DEBUGFUNC("e1000_copper_link_setup_igp");
1244 if (phy->reset_disable)
1245 return E1000_SUCCESS;
1247 ret_val = hw->phy.ops.reset(hw);
1249 DEBUGOUT("Error resetting the PHY.\n");
1254 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1255 * timeout issues when LFS is enabled.
1259 /* disable lplu d0 during driver init */
1260 if (hw->phy.ops.set_d0_lplu_state) {
1261 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
1263 DEBUGOUT("Error Disabling LPLU D0\n");
1267 /* Configure mdi-mdix settings */
1268 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1272 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1274 switch (phy->mdix) {
1276 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1279 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1283 data |= IGP01E1000_PSCR_AUTO_MDIX;
1286 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1290 /* set auto-master slave resolution settings */
1291 if (hw->mac.autoneg) {
1293 * when autonegotiation advertisement is only 1000Mbps then we
1294 * should disable SmartSpeed and enable Auto MasterSlave
1295 * resolution as hardware default.
1297 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1298 /* Disable SmartSpeed */
1299 ret_val = phy->ops.read_reg(hw,
1300 IGP01E1000_PHY_PORT_CONFIG,
1305 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1306 ret_val = phy->ops.write_reg(hw,
1307 IGP01E1000_PHY_PORT_CONFIG,
1312 /* Set auto Master/Slave resolution process */
1313 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1317 data &= ~CR_1000T_MS_ENABLE;
1318 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1323 ret_val = e1000_set_master_slave_mode(hw);
1330 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1331 * @hw: pointer to the HW structure
1333 * Reads the MII auto-neg advertisement register and/or the 1000T control
1334 * register and if the PHY is already setup for auto-negotiation, then
1335 * return successful. Otherwise, setup advertisement and flow control to
1336 * the appropriate values for the wanted auto-negotiation.
1338 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1340 struct e1000_phy_info *phy = &hw->phy;
1342 u16 mii_autoneg_adv_reg;
1343 u16 mii_1000t_ctrl_reg = 0;
1345 DEBUGFUNC("e1000_phy_setup_autoneg");
1347 phy->autoneg_advertised &= phy->autoneg_mask;
1349 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1350 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1354 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1355 /* Read the MII 1000Base-T Control Register (Address 9). */
1356 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1357 &mii_1000t_ctrl_reg);
1363 * Need to parse both autoneg_advertised and fc and set up
1364 * the appropriate PHY registers. First we will parse for
1365 * autoneg_advertised software override. Since we can advertise
1366 * a plethora of combinations, we need to check each bit
1371 * First we clear all the 10/100 mb speed bits in the Auto-Neg
1372 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1373 * the 1000Base-T Control Register (Address 9).
1375 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1376 NWAY_AR_100TX_HD_CAPS |
1377 NWAY_AR_10T_FD_CAPS |
1378 NWAY_AR_10T_HD_CAPS);
1379 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1381 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1383 /* Do we want to advertise 10 Mb Half Duplex? */
1384 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1385 DEBUGOUT("Advertise 10mb Half duplex\n");
1386 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1389 /* Do we want to advertise 10 Mb Full Duplex? */
1390 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1391 DEBUGOUT("Advertise 10mb Full duplex\n");
1392 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1395 /* Do we want to advertise 100 Mb Half Duplex? */
1396 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1397 DEBUGOUT("Advertise 100mb Half duplex\n");
1398 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1401 /* Do we want to advertise 100 Mb Full Duplex? */
1402 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1403 DEBUGOUT("Advertise 100mb Full duplex\n");
1404 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1407 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1408 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1409 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1411 /* Do we want to advertise 1000 Mb Full Duplex? */
1412 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1413 DEBUGOUT("Advertise 1000mb Full duplex\n");
1414 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1418 * Check for a software override of the flow control settings, and
1419 * setup the PHY advertisement registers accordingly. If
1420 * auto-negotiation is enabled, then software will have to set the
1421 * "PAUSE" bits to the correct value in the Auto-Negotiation
1422 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1425 * The possible values of the "fc" parameter are:
1426 * 0: Flow control is completely disabled
1427 * 1: Rx flow control is enabled (we can receive pause frames
1428 * but not send pause frames).
1429 * 2: Tx flow control is enabled (we can send pause frames
1430 * but we do not support receiving pause frames).
1431 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1432 * other: No software override. The flow control configuration
1433 * in the EEPROM is used.
1435 switch (hw->fc.current_mode) {
1438 * Flow control (Rx & Tx) is completely disabled by a
1439 * software over-ride.
1441 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1443 case e1000_fc_rx_pause:
1445 * Rx Flow control is enabled, and Tx Flow control is
1446 * disabled, by a software over-ride.
1448 * Since there really isn't a way to advertise that we are
1449 * capable of Rx Pause ONLY, we will advertise that we
1450 * support both symmetric and asymmetric Rx PAUSE. Later
1451 * (in e1000_config_fc_after_link_up) we will disable the
1452 * hw's ability to send PAUSE frames.
1454 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1456 case e1000_fc_tx_pause:
1458 * Tx Flow control is enabled, and Rx Flow control is
1459 * disabled, by a software over-ride.
1461 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1462 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1466 * Flow control (both Rx and Tx) is enabled by a software
1469 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1472 DEBUGOUT("Flow control param set incorrectly\n");
1473 return -E1000_ERR_CONFIG;
1476 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1480 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1482 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1483 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
1484 mii_1000t_ctrl_reg);
1490 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1491 * @hw: pointer to the HW structure
1493 * Performs initial bounds checking on autoneg advertisement parameter, then
1494 * configure to advertise the full capability. Setup the PHY to autoneg
1495 * and restart the negotiation process between the link partner. If
1496 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1498 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1500 struct e1000_phy_info *phy = &hw->phy;
1504 DEBUGFUNC("e1000_copper_link_autoneg");
1507 * Perform some bounds checking on the autoneg advertisement
1510 phy->autoneg_advertised &= phy->autoneg_mask;
1513 * If autoneg_advertised is zero, we assume it was not defaulted
1514 * by the calling code so we set to advertise full capability.
1516 if (phy->autoneg_advertised == 0)
1517 phy->autoneg_advertised = phy->autoneg_mask;
1519 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1520 ret_val = e1000_phy_setup_autoneg(hw);
1522 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1525 DEBUGOUT("Restarting Auto-Neg\n");
1528 * Restart auto-negotiation by setting the Auto Neg Enable bit and
1529 * the Auto Neg Restart bit in the PHY control register.
1531 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1535 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1536 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1541 * Does the user want to wait for Auto-Neg to complete here, or
1542 * check at a later time (for example, callback routine).
1544 if (phy->autoneg_wait_to_complete) {
1545 ret_val = hw->mac.ops.wait_autoneg(hw);
1547 DEBUGOUT("Error while waiting for autoneg to complete\n");
1552 hw->mac.get_link_status = true;
1558 * e1000_setup_copper_link_generic - Configure copper link settings
1559 * @hw: pointer to the HW structure
1561 * Calls the appropriate function to configure the link for auto-neg or forced
1562 * speed and duplex. Then we check for link, once link is established calls
1563 * to configure collision distance and flow control are called. If link is
1564 * not established, we return -E1000_ERR_PHY (-2).
1566 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1571 DEBUGFUNC("e1000_setup_copper_link_generic");
1573 if (hw->mac.autoneg) {
1575 * Setup autoneg and flow control advertisement and perform
1578 ret_val = e1000_copper_link_autoneg(hw);
1583 * PHY will be set to 10H, 10F, 100H or 100F
1584 * depending on user settings.
1586 DEBUGOUT("Forcing Speed and Duplex\n");
1587 ret_val = hw->phy.ops.force_speed_duplex(hw);
1589 DEBUGOUT("Error Forcing Speed and Duplex\n");
1595 * Check link status. Wait up to 100 microseconds for link to become
1598 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1604 DEBUGOUT("Valid link established!!!\n");
1605 hw->mac.ops.config_collision_dist(hw);
1606 ret_val = e1000_config_fc_after_link_up_generic(hw);
1608 DEBUGOUT("Unable to establish link!!!\n");
1615 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1616 * @hw: pointer to the HW structure
1618 * Calls the PHY setup function to force speed and duplex. Clears the
1619 * auto-crossover to force MDI manually. Waits for link and returns
1620 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1622 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1624 struct e1000_phy_info *phy = &hw->phy;
1629 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1631 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1635 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1637 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1642 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1643 * forced whenever speed and duplex are forced.
1645 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1649 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1650 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1652 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1656 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1660 if (phy->autoneg_wait_to_complete) {
1661 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1663 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1669 DEBUGOUT("Link taking longer than expected.\n");
1672 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1680 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1681 * @hw: pointer to the HW structure
1683 * Calls the PHY setup function to force speed and duplex. Clears the
1684 * auto-crossover to force MDI manually. Resets the PHY to commit the
1685 * changes. If time expires while waiting for link up, we reset the DSP.
1686 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1687 * successful completion, else return corresponding error code.
1689 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1691 struct e1000_phy_info *phy = &hw->phy;
1696 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1699 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1700 * forced whenever speed and duplex are forced.
1702 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1706 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1707 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1711 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1713 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1717 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1719 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1723 /* Reset the phy to commit changes. */
1724 ret_val = hw->phy.ops.commit(hw);
1728 if (phy->autoneg_wait_to_complete) {
1729 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1731 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1737 bool reset_dsp = true;
1739 switch (hw->phy.id) {
1740 case I347AT4_E_PHY_ID:
1741 case M88E1340M_E_PHY_ID:
1742 case M88E1112_E_PHY_ID:
1746 if (hw->phy.type != e1000_phy_m88)
1752 DEBUGOUT("Link taking longer than expected.\n");
1755 * We didn't get link.
1756 * Reset the DSP and cross our fingers.
1758 ret_val = phy->ops.write_reg(hw,
1759 M88E1000_PHY_PAGE_SELECT,
1763 ret_val = e1000_phy_reset_dsp_generic(hw);
1770 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1776 if (hw->phy.type != e1000_phy_m88)
1777 return E1000_SUCCESS;
1779 if (hw->phy.id == I347AT4_E_PHY_ID ||
1780 hw->phy.id == M88E1340M_E_PHY_ID ||
1781 hw->phy.id == M88E1112_E_PHY_ID)
1782 return E1000_SUCCESS;
1783 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1788 * Resetting the phy means we need to re-force TX_CLK in the
1789 * Extended PHY Specific Control Register to 25MHz clock from
1790 * the reset value of 2.5MHz.
1792 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1793 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1798 * In addition, we must re-enable CRS on Tx for both half and full
1801 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1805 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1806 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1812 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1813 * @hw: pointer to the HW structure
1815 * Forces the speed and duplex settings of the PHY.
1816 * This is a function pointer entry point only called by
1817 * PHY setup routines.
1819 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1821 struct e1000_phy_info *phy = &hw->phy;
1826 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1828 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1832 e1000_phy_force_speed_duplex_setup(hw, &data);
1834 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1838 /* Disable MDI-X support for 10/100 */
1839 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1843 data &= ~IFE_PMC_AUTO_MDIX;
1844 data &= ~IFE_PMC_FORCE_MDIX;
1846 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1850 DEBUGOUT1("IFE PMC: %X\n", data);
1854 if (phy->autoneg_wait_to_complete) {
1855 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1857 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1863 DEBUGOUT("Link taking longer than expected.\n");
1866 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1872 return E1000_SUCCESS;
1876 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1877 * @hw: pointer to the HW structure
1878 * @phy_ctrl: pointer to current value of PHY_CONTROL
1880 * Forces speed and duplex on the PHY by doing the following: disable flow
1881 * control, force speed/duplex on the MAC, disable auto speed detection,
1882 * disable auto-negotiation, configure duplex, configure speed, configure
1883 * the collision distance, write configuration to CTRL register. The
1884 * caller must write to the PHY_CONTROL register for these settings to
1887 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1889 struct e1000_mac_info *mac = &hw->mac;
1892 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
1894 /* Turn off flow control when forcing speed/duplex */
1895 hw->fc.current_mode = e1000_fc_none;
1897 /* Force speed/duplex on the mac */
1898 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1899 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1900 ctrl &= ~E1000_CTRL_SPD_SEL;
1902 /* Disable Auto Speed Detection */
1903 ctrl &= ~E1000_CTRL_ASDE;
1905 /* Disable autoneg on the phy */
1906 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1908 /* Forcing Full or Half Duplex? */
1909 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1910 ctrl &= ~E1000_CTRL_FD;
1911 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1912 DEBUGOUT("Half Duplex\n");
1914 ctrl |= E1000_CTRL_FD;
1915 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1916 DEBUGOUT("Full Duplex\n");
1919 /* Forcing 10mb or 100mb? */
1920 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1921 ctrl |= E1000_CTRL_SPD_100;
1922 *phy_ctrl |= MII_CR_SPEED_100;
1923 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1924 DEBUGOUT("Forcing 100mb\n");
1926 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1927 *phy_ctrl |= MII_CR_SPEED_10;
1928 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1929 DEBUGOUT("Forcing 10mb\n");
1932 hw->mac.ops.config_collision_dist(hw);
1934 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1938 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
1939 * @hw: pointer to the HW structure
1940 * @active: boolean used to enable/disable lplu
1942 * Success returns 0, Failure returns 1
1944 * The low power link up (lplu) state is set to the power management level D3
1945 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1946 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1947 * is used during Dx states where the power conservation is most important.
1948 * During driver activity, SmartSpeed should be enabled so performance is
1951 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
1953 struct e1000_phy_info *phy = &hw->phy;
1957 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
1959 if (!hw->phy.ops.read_reg)
1960 return E1000_SUCCESS;
1962 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1967 data &= ~IGP02E1000_PM_D3_LPLU;
1968 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1973 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1974 * during Dx states where the power conservation is most
1975 * important. During driver activity we should enable
1976 * SmartSpeed, so performance is maintained.
1978 if (phy->smart_speed == e1000_smart_speed_on) {
1979 ret_val = phy->ops.read_reg(hw,
1980 IGP01E1000_PHY_PORT_CONFIG,
1985 data |= IGP01E1000_PSCFR_SMART_SPEED;
1986 ret_val = phy->ops.write_reg(hw,
1987 IGP01E1000_PHY_PORT_CONFIG,
1991 } else if (phy->smart_speed == e1000_smart_speed_off) {
1992 ret_val = phy->ops.read_reg(hw,
1993 IGP01E1000_PHY_PORT_CONFIG,
1998 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1999 ret_val = phy->ops.write_reg(hw,
2000 IGP01E1000_PHY_PORT_CONFIG,
2005 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2006 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2007 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2008 data |= IGP02E1000_PM_D3_LPLU;
2009 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2014 /* When LPLU is enabled, we should disable SmartSpeed */
2015 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2020 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2021 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2029 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
2030 * @hw: pointer to the HW structure
2032 * Success returns 0, Failure returns 1
2034 * A downshift is detected by querying the PHY link health.
2036 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
2038 struct e1000_phy_info *phy = &hw->phy;
2040 u16 phy_data, offset, mask;
2042 DEBUGFUNC("e1000_check_downshift_generic");
2044 switch (phy->type) {
2046 case e1000_phy_gg82563:
2047 offset = M88E1000_PHY_SPEC_STATUS;
2048 mask = M88E1000_PSSR_DOWNSHIFT;
2050 case e1000_phy_igp_2:
2051 case e1000_phy_igp_3:
2052 offset = IGP01E1000_PHY_LINK_HEALTH;
2053 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
2056 /* speed downshift not supported */
2057 phy->speed_downgraded = false;
2058 return E1000_SUCCESS;
2061 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2064 phy->speed_downgraded = !!(phy_data & mask);
2070 * e1000_check_polarity_m88 - Checks the polarity.
2071 * @hw: pointer to the HW structure
2073 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2075 * Polarity is determined based on the PHY specific status register.
2077 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
2079 struct e1000_phy_info *phy = &hw->phy;
2083 DEBUGFUNC("e1000_check_polarity_m88");
2085 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
2088 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
2089 ? e1000_rev_polarity_reversed
2090 : e1000_rev_polarity_normal;
2096 * e1000_check_polarity_igp - Checks the polarity.
2097 * @hw: pointer to the HW structure
2099 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2101 * Polarity is determined based on the PHY port status register, and the
2102 * current speed (since there is no polarity at 100Mbps).
2104 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
2106 struct e1000_phy_info *phy = &hw->phy;
2108 u16 data, offset, mask;
2110 DEBUGFUNC("e1000_check_polarity_igp");
2113 * Polarity is determined based on the speed of
2116 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2120 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2121 IGP01E1000_PSSR_SPEED_1000MBPS) {
2122 offset = IGP01E1000_PHY_PCS_INIT_REG;
2123 mask = IGP01E1000_PHY_POLARITY_MASK;
2126 * This really only applies to 10Mbps since
2127 * there is no polarity for 100Mbps (always 0).
2129 offset = IGP01E1000_PHY_PORT_STATUS;
2130 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
2133 ret_val = phy->ops.read_reg(hw, offset, &data);
2136 phy->cable_polarity = (data & mask)
2137 ? e1000_rev_polarity_reversed
2138 : e1000_rev_polarity_normal;
2144 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
2145 * @hw: pointer to the HW structure
2147 * Polarity is determined on the polarity reversal feature being enabled.
2149 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
2151 struct e1000_phy_info *phy = &hw->phy;
2153 u16 phy_data, offset, mask;
2155 DEBUGFUNC("e1000_check_polarity_ife");
2158 * Polarity is determined based on the reversal feature being enabled.
2160 if (phy->polarity_correction) {
2161 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
2162 mask = IFE_PESC_POLARITY_REVERSED;
2164 offset = IFE_PHY_SPECIAL_CONTROL;
2165 mask = IFE_PSC_FORCE_POLARITY;
2168 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2171 phy->cable_polarity = (phy_data & mask)
2172 ? e1000_rev_polarity_reversed
2173 : e1000_rev_polarity_normal;
2179 * e1000_wait_autoneg_generic - Wait for auto-neg completion
2180 * @hw: pointer to the HW structure
2182 * Waits for auto-negotiation to complete or for the auto-negotiation time
2183 * limit to expire, which ever happens first.
2185 s32 e1000_wait_autoneg_generic(struct e1000_hw *hw)
2187 s32 ret_val = E1000_SUCCESS;
2190 DEBUGFUNC("e1000_wait_autoneg_generic");
2192 if (!hw->phy.ops.read_reg)
2193 return E1000_SUCCESS;
2195 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
2196 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
2197 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2200 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2203 if (phy_status & MII_SR_AUTONEG_COMPLETE)
2209 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
2216 * e1000_phy_has_link_generic - Polls PHY for link
2217 * @hw: pointer to the HW structure
2218 * @iterations: number of times to poll for link
2219 * @usec_interval: delay between polling attempts
2220 * @success: pointer to whether polling was successful or not
2222 * Polls the PHY status register for link, 'iterations' number of times.
2224 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2225 u32 usec_interval, bool *success)
2227 s32 ret_val = E1000_SUCCESS;
2230 DEBUGFUNC("e1000_phy_has_link_generic");
2232 if (!hw->phy.ops.read_reg)
2233 return E1000_SUCCESS;
2235 for (i = 0; i < iterations; i++) {
2237 * Some PHYs require the PHY_STATUS register to be read
2238 * twice due to the link bit being sticky. No harm doing
2239 * it across the board.
2241 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2244 * If the first read fails, another entity may have
2245 * ownership of the resources, wait and try again to
2246 * see if they have relinquished the resources yet.
2248 usec_delay(usec_interval);
2249 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2252 if (phy_status & MII_SR_LINK_STATUS)
2254 if (usec_interval >= 1000)
2255 msec_delay_irq(usec_interval/1000);
2257 usec_delay(usec_interval);
2260 *success = (i < iterations);
2266 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2267 * @hw: pointer to the HW structure
2269 * Reads the PHY specific status register to retrieve the cable length
2270 * information. The cable length is determined by averaging the minimum and
2271 * maximum values to get the "average" cable length. The m88 PHY has four
2272 * possible cable length values, which are:
2273 * Register Value Cable Length
2277 * 3 110 - 140 meters
2280 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
2282 struct e1000_phy_info *phy = &hw->phy;
2284 u16 phy_data, index;
2286 DEBUGFUNC("e1000_get_cable_length_m88");
2288 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2292 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2293 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2295 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2296 return -E1000_ERR_PHY;
2298 phy->min_cable_length = e1000_m88_cable_length_table[index];
2299 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2301 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2303 return E1000_SUCCESS;
2306 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
2308 struct e1000_phy_info *phy = &hw->phy;
2310 u16 phy_data, phy_data2, index, default_page, is_cm;
2312 DEBUGFUNC("e1000_get_cable_length_m88_gen2");
2314 switch (hw->phy.id) {
2315 case M88E1340M_E_PHY_ID:
2316 case I347AT4_E_PHY_ID:
2317 /* Remember the original page select and set it to 7 */
2318 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2323 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2327 /* Get cable length from PHY Cable Diagnostics Control Reg */
2328 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2333 /* Check if the unit of cable length is meters or cm */
2334 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2338 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2340 /* Populate the phy structure with cable length in meters */
2341 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2342 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2343 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2345 /* Reset the page select to its original value */
2346 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2352 case M88E1112_E_PHY_ID:
2353 /* Remember the original page select and set it to 5 */
2354 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2359 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2363 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2368 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2369 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2371 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2372 return -E1000_ERR_PHY;
2374 phy->min_cable_length = e1000_m88_cable_length_table[index];
2375 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2377 phy->cable_length = (phy->min_cable_length +
2378 phy->max_cable_length) / 2;
2380 /* Reset the page select to its original value */
2381 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2388 return -E1000_ERR_PHY;
2395 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2396 * @hw: pointer to the HW structure
2398 * The automatic gain control (agc) normalizes the amplitude of the
2399 * received signal, adjusting for the attenuation produced by the
2400 * cable. By reading the AGC registers, which represent the
2401 * combination of coarse and fine gain value, the value can be put
2402 * into a lookup table to obtain the approximate cable length
2405 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2407 struct e1000_phy_info *phy = &hw->phy;
2409 u16 phy_data, i, agc_value = 0;
2410 u16 cur_agc_index, max_agc_index = 0;
2411 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2412 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
2413 IGP02E1000_PHY_AGC_A,
2414 IGP02E1000_PHY_AGC_B,
2415 IGP02E1000_PHY_AGC_C,
2416 IGP02E1000_PHY_AGC_D
2419 DEBUGFUNC("e1000_get_cable_length_igp_2");
2421 /* Read the AGC registers for all channels */
2422 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
2423 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2428 * Getting bits 15:9, which represent the combination of
2429 * coarse and fine gain values. The result is a number
2430 * that can be put into the lookup table to obtain the
2431 * approximate cable length.
2433 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
2434 IGP02E1000_AGC_LENGTH_MASK;
2436 /* Array index bound check. */
2437 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
2438 (cur_agc_index == 0))
2439 return -E1000_ERR_PHY;
2441 /* Remove min & max AGC values from calculation. */
2442 if (e1000_igp_2_cable_length_table[min_agc_index] >
2443 e1000_igp_2_cable_length_table[cur_agc_index])
2444 min_agc_index = cur_agc_index;
2445 if (e1000_igp_2_cable_length_table[max_agc_index] <
2446 e1000_igp_2_cable_length_table[cur_agc_index])
2447 max_agc_index = cur_agc_index;
2449 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
2452 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
2453 e1000_igp_2_cable_length_table[max_agc_index]);
2454 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
2456 /* Calculate cable length with the error range of +/- 10 meters. */
2457 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2458 (agc_value - IGP02E1000_AGC_RANGE) : 0;
2459 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2461 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2463 return E1000_SUCCESS;
2467 * e1000_get_phy_info_m88 - Retrieve PHY information
2468 * @hw: pointer to the HW structure
2470 * Valid for only copper links. Read the PHY status register (sticky read)
2471 * to verify that link is up. Read the PHY special control register to
2472 * determine the polarity and 10base-T extended distance. Read the PHY
2473 * special status register to determine MDI/MDIx and current speed. If
2474 * speed is 1000, then determine cable length, local and remote receiver.
2476 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
2478 struct e1000_phy_info *phy = &hw->phy;
2483 DEBUGFUNC("e1000_get_phy_info_m88");
2485 if (phy->media_type != e1000_media_type_copper) {
2486 DEBUGOUT("Phy info is only valid for copper media\n");
2487 return -E1000_ERR_CONFIG;
2490 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2495 DEBUGOUT("Phy info is only valid if link is up\n");
2496 return -E1000_ERR_CONFIG;
2499 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2503 phy->polarity_correction = !!(phy_data &
2504 M88E1000_PSCR_POLARITY_REVERSAL);
2506 ret_val = e1000_check_polarity_m88(hw);
2510 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2514 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
2516 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2517 ret_val = hw->phy.ops.get_cable_length(hw);
2521 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2525 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2526 ? e1000_1000t_rx_status_ok
2527 : e1000_1000t_rx_status_not_ok;
2529 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2530 ? e1000_1000t_rx_status_ok
2531 : e1000_1000t_rx_status_not_ok;
2533 /* Set values to "undefined" */
2534 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2535 phy->local_rx = e1000_1000t_rx_status_undefined;
2536 phy->remote_rx = e1000_1000t_rx_status_undefined;
2543 * e1000_get_phy_info_igp - Retrieve igp PHY information
2544 * @hw: pointer to the HW structure
2546 * Read PHY status to determine if link is up. If link is up, then
2547 * set/determine 10base-T extended distance and polarity correction. Read
2548 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2549 * determine on the cable length, local and remote receiver.
2551 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
2553 struct e1000_phy_info *phy = &hw->phy;
2558 DEBUGFUNC("e1000_get_phy_info_igp");
2560 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2565 DEBUGOUT("Phy info is only valid if link is up\n");
2566 return -E1000_ERR_CONFIG;
2569 phy->polarity_correction = true;
2571 ret_val = e1000_check_polarity_igp(hw);
2575 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2579 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
2581 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2582 IGP01E1000_PSSR_SPEED_1000MBPS) {
2583 ret_val = phy->ops.get_cable_length(hw);
2587 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2591 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2592 ? e1000_1000t_rx_status_ok
2593 : e1000_1000t_rx_status_not_ok;
2595 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2596 ? e1000_1000t_rx_status_ok
2597 : e1000_1000t_rx_status_not_ok;
2599 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2600 phy->local_rx = e1000_1000t_rx_status_undefined;
2601 phy->remote_rx = e1000_1000t_rx_status_undefined;
2608 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2609 * @hw: pointer to the HW structure
2611 * Populates "phy" structure with various feature states.
2613 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2615 struct e1000_phy_info *phy = &hw->phy;
2620 DEBUGFUNC("e1000_get_phy_info_ife");
2622 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2627 DEBUGOUT("Phy info is only valid if link is up\n");
2628 return -E1000_ERR_CONFIG;
2631 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2634 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2636 if (phy->polarity_correction) {
2637 ret_val = e1000_check_polarity_ife(hw);
2641 /* Polarity is forced */
2642 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
2643 ? e1000_rev_polarity_reversed
2644 : e1000_rev_polarity_normal;
2647 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2651 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2653 /* The following parameters are undefined for 10/100 operation. */
2654 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2655 phy->local_rx = e1000_1000t_rx_status_undefined;
2656 phy->remote_rx = e1000_1000t_rx_status_undefined;
2658 return E1000_SUCCESS;
2662 * e1000_phy_sw_reset_generic - PHY software reset
2663 * @hw: pointer to the HW structure
2665 * Does a software reset of the PHY by reading the PHY control register and
2666 * setting/write the control register reset bit to the PHY.
2668 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2673 DEBUGFUNC("e1000_phy_sw_reset_generic");
2675 if (!hw->phy.ops.read_reg)
2676 return E1000_SUCCESS;
2678 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2682 phy_ctrl |= MII_CR_RESET;
2683 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2693 * e1000_phy_hw_reset_generic - PHY hardware reset
2694 * @hw: pointer to the HW structure
2696 * Verify the reset block is not blocking us from resetting. Acquire
2697 * semaphore (if necessary) and read/set/write the device control reset
2698 * bit in the PHY. Wait the appropriate delay time for the device to
2699 * reset and release the semaphore (if necessary).
2701 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2703 struct e1000_phy_info *phy = &hw->phy;
2707 DEBUGFUNC("e1000_phy_hw_reset_generic");
2709 ret_val = phy->ops.check_reset_block(hw);
2711 return E1000_SUCCESS;
2713 ret_val = phy->ops.acquire(hw);
2717 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2718 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2719 E1000_WRITE_FLUSH(hw);
2721 usec_delay(phy->reset_delay_us);
2723 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2724 E1000_WRITE_FLUSH(hw);
2728 phy->ops.release(hw);
2730 return phy->ops.get_cfg_done(hw);
2734 * e1000_get_cfg_done_generic - Generic configuration done
2735 * @hw: pointer to the HW structure
2737 * Generic function to wait 10 milli-seconds for configuration to complete
2738 * and return success.
2740 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw)
2742 DEBUGFUNC("e1000_get_cfg_done_generic");
2746 return E1000_SUCCESS;
2750 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2751 * @hw: pointer to the HW structure
2753 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2755 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2757 DEBUGOUT("Running IGP 3 PHY init script\n");
2759 /* PHY init IGP 3 */
2760 /* Enable rise/fall, 10-mode work in class-A */
2761 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2762 /* Remove all caps from Replica path filter */
2763 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2764 /* Bias trimming for ADC, AFE and Driver (Default) */
2765 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2766 /* Increase Hybrid poly bias */
2767 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2768 /* Add 4% to Tx amplitude in Gig mode */
2769 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2770 /* Disable trimming (TTT) */
2771 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2772 /* Poly DC correction to 94.6% + 2% for all channels */
2773 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2774 /* ABS DC correction to 95.9% */
2775 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2776 /* BG temp curve trim */
2777 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2778 /* Increasing ADC OPAMP stage 1 currents to max */
2779 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2780 /* Force 1000 ( required for enabling PHY regs configuration) */
2781 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2782 /* Set upd_freq to 6 */
2783 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2785 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2786 /* Disable adaptive fixed FFE (Default) */
2787 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2788 /* Enable FFE hysteresis */
2789 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2790 /* Fixed FFE for short cable lengths */
2791 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2792 /* Fixed FFE for medium cable lengths */
2793 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2794 /* Fixed FFE for long cable lengths */
2795 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2796 /* Enable Adaptive Clip Threshold */
2797 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2798 /* AHT reset limit to 1 */
2799 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2800 /* Set AHT master delay to 127 msec */
2801 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2802 /* Set scan bits for AHT */
2803 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2804 /* Set AHT Preset bits */
2805 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2806 /* Change integ_factor of channel A to 3 */
2807 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2808 /* Change prop_factor of channels BCD to 8 */
2809 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2810 /* Change cg_icount + enable integbp for channels BCD */
2811 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2813 * Change cg_icount + enable integbp + change prop_factor_master
2814 * to 8 for channel A
2816 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2817 /* Disable AHT in Slave mode on channel A */
2818 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2820 * Enable LPLU and disable AN to 1000 in non-D0a states,
2823 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2824 /* Enable restart AN on an1000_dis change */
2825 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2826 /* Enable wh_fifo read clock in 10/100 modes */
2827 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2828 /* Restart AN, Speed selection is 1000 */
2829 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2831 return E1000_SUCCESS;
2835 * e1000_get_phy_type_from_id - Get PHY type from id
2836 * @phy_id: phy_id read from the phy
2838 * Returns the phy type from the id.
2840 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
2842 enum e1000_phy_type phy_type = e1000_phy_unknown;
2845 case M88E1000_I_PHY_ID:
2846 case M88E1000_E_PHY_ID:
2847 case M88E1111_I_PHY_ID:
2848 case M88E1011_I_PHY_ID:
2849 case I347AT4_E_PHY_ID:
2850 case M88E1112_E_PHY_ID:
2851 case M88E1340M_E_PHY_ID:
2852 phy_type = e1000_phy_m88;
2854 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2855 phy_type = e1000_phy_igp_2;
2857 case GG82563_E_PHY_ID:
2858 phy_type = e1000_phy_gg82563;
2860 case IGP03E1000_E_PHY_ID:
2861 phy_type = e1000_phy_igp_3;
2864 case IFE_PLUS_E_PHY_ID:
2865 case IFE_C_E_PHY_ID:
2866 phy_type = e1000_phy_ife;
2868 case I82580_I_PHY_ID:
2869 phy_type = e1000_phy_82580;
2872 phy_type = e1000_phy_unknown;
2879 * e1000_determine_phy_address - Determines PHY address.
2880 * @hw: pointer to the HW structure
2882 * This uses a trial and error method to loop through possible PHY
2883 * addresses. It tests each by reading the PHY ID registers and
2884 * checking for a match.
2886 s32 e1000_determine_phy_address(struct e1000_hw *hw)
2890 enum e1000_phy_type phy_type = e1000_phy_unknown;
2892 hw->phy.id = phy_type;
2894 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2895 hw->phy.addr = phy_addr;
2899 e1000_get_phy_id(hw);
2900 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
2903 * If phy_type is valid, break - we found our
2906 if (phy_type != e1000_phy_unknown)
2907 return E1000_SUCCESS;
2914 return -E1000_ERR_PHY_TYPE;
2918 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2919 * @hw: pointer to the HW structure
2921 * In the case of a PHY power down to save power, or to turn off link during a
2922 * driver unload, or wake on lan is not enabled, restore the link to previous
2925 void e1000_power_up_phy_copper(struct e1000_hw *hw)
2929 /* The PHY will retain its settings across a power down/up cycle */
2930 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2931 mii_reg &= ~MII_CR_POWER_DOWN;
2932 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2936 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2937 * @hw: pointer to the HW structure
2939 * In the case of a PHY power down to save power, or to turn off link during a
2940 * driver unload, or wake on lan is not enabled, restore the link to previous
2943 void e1000_power_down_phy_copper(struct e1000_hw *hw)
2947 /* The PHY will retain its settings across a power down/up cycle */
2948 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2949 mii_reg |= MII_CR_POWER_DOWN;
2950 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2955 * e1000_check_polarity_82577 - Checks the polarity.
2956 * @hw: pointer to the HW structure
2958 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2960 * Polarity is determined based on the PHY specific status register.
2962 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
2964 struct e1000_phy_info *phy = &hw->phy;
2968 DEBUGFUNC("e1000_check_polarity_82577");
2970 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
2973 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
2974 ? e1000_rev_polarity_reversed
2975 : e1000_rev_polarity_normal;
2981 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
2982 * @hw: pointer to the HW structure
2984 * Calls the PHY setup function to force speed and duplex.
2986 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
2988 struct e1000_phy_info *phy = &hw->phy;
2993 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
2995 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
2999 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
3001 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3007 if (phy->autoneg_wait_to_complete) {
3008 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3010 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3016 DEBUGOUT("Link taking longer than expected.\n");
3019 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3027 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3028 * @hw: pointer to the HW structure
3030 * Read PHY status to determine if link is up. If link is up, then
3031 * set/determine 10base-T extended distance and polarity correction. Read
3032 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3033 * determine on the cable length, local and remote receiver.
3035 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3037 struct e1000_phy_info *phy = &hw->phy;
3042 DEBUGFUNC("e1000_get_phy_info_82577");
3044 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3049 DEBUGOUT("Phy info is only valid if link is up\n");
3050 return -E1000_ERR_CONFIG;
3053 phy->polarity_correction = true;
3055 ret_val = e1000_check_polarity_82577(hw);
3059 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3063 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3065 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3066 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3067 ret_val = hw->phy.ops.get_cable_length(hw);
3071 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
3075 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3076 ? e1000_1000t_rx_status_ok
3077 : e1000_1000t_rx_status_not_ok;
3079 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3080 ? e1000_1000t_rx_status_ok
3081 : e1000_1000t_rx_status_not_ok;
3083 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3084 phy->local_rx = e1000_1000t_rx_status_undefined;
3085 phy->remote_rx = e1000_1000t_rx_status_undefined;
3088 return E1000_SUCCESS;
3092 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3093 * @hw: pointer to the HW structure
3095 * Reads the diagnostic status register and verifies result is valid before
3096 * placing it in the phy_cable_length field.
3098 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3100 struct e1000_phy_info *phy = &hw->phy;
3102 u16 phy_data, length;
3104 DEBUGFUNC("e1000_get_cable_length_82577");
3106 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3110 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
3111 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
3113 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3114 ret_val = -E1000_ERR_PHY;
3116 phy->cable_length = length;
3118 return E1000_SUCCESS;