1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "LICENSE.GPL".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
31 void e1000_init_phy_ops_generic(struct e1000_hw *hw);
32 s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data);
33 void e1000_null_phy_generic(struct e1000_hw *hw);
34 s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active);
35 s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data);
36 s32 e1000_null_set_page(struct e1000_hw *hw, u16 data);
37 s32 e1000_read_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset,
38 u8 dev_addr, u8 *data);
39 s32 e1000_write_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset,
40 u8 dev_addr, u8 data);
41 s32 e1000_check_downshift_generic(struct e1000_hw *hw);
42 s32 e1000_check_polarity_m88(struct e1000_hw *hw);
43 s32 e1000_check_polarity_igp(struct e1000_hw *hw);
44 s32 e1000_check_polarity_ife(struct e1000_hw *hw);
45 s32 e1000_check_reset_block_generic(struct e1000_hw *hw);
46 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw);
47 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw);
48 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw);
49 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw);
50 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw);
51 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
52 s32 e1000_get_cable_length_m88(struct e1000_hw *hw);
53 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw);
54 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw);
55 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw);
56 s32 e1000_get_phy_id(struct e1000_hw *hw);
57 s32 e1000_get_phy_info_igp(struct e1000_hw *hw);
58 s32 e1000_get_phy_info_m88(struct e1000_hw *hw);
59 s32 e1000_get_phy_info_ife(struct e1000_hw *hw);
60 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw);
61 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
62 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw);
63 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw);
64 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data);
65 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data);
66 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page);
67 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
68 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data);
69 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
70 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active);
71 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw);
72 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data);
73 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data);
74 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
75 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data);
76 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
77 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
78 u32 usec_interval, bool *success);
79 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw);
80 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id);
81 s32 e1000_determine_phy_address(struct e1000_hw *hw);
82 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);
83 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);
84 void e1000_power_up_phy_copper(struct e1000_hw *hw);
85 void e1000_power_down_phy_copper(struct e1000_hw *hw);
86 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
87 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
88 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
89 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
90 s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data);
91 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data);
92 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw);
93 s32 e1000_check_polarity_82577(struct e1000_hw *hw);
94 s32 e1000_get_phy_info_82577(struct e1000_hw *hw);
95 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
96 s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
97 s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data);
98 s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data);
99 s32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data);
100 s32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data,
102 bool e1000_is_mphy_ready(struct e1000_hw *hw);
104 #define E1000_MAX_PHY_ADDR 8
106 /* IGP01E1000 Specific Registers */
107 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
108 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
109 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
110 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
111 #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
112 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
113 #define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */
114 #define IGP_PAGE_SHIFT 5
115 #define PHY_REG_MASK 0x1F
117 /* GS40G - I210 PHY defines */
118 #define GS40G_PAGE_SELECT 0x16
119 #define GS40G_PAGE_SHIFT 16
120 #define GS40G_OFFSET_MASK 0xFFFF
121 #define GS40G_PAGE_2 0x20000
122 #define GS40G_MAC_REG2 0x15
123 #define GS40G_MAC_LB 0x4140
124 #define GS40G_MAC_SPEED_1G 0X0006
125 #define GS40G_COPPER_SPEC 0x0010
126 #define GS40G_CS_POWER_DOWN 0x0002
128 #define HV_INTC_FC_PAGE_START 768
129 #define I82578_ADDR_REG 29
130 #define I82577_ADDR_REG 16
131 #define I82577_CFG_REG 22
132 #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15)
133 #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift */
134 #define I82577_CTRL_REG 23
136 /* 82577 specific PHY registers */
137 #define I82577_PHY_CTRL_2 18
138 #define I82577_PHY_LBK_CTRL 19
139 #define I82577_PHY_STATUS_2 26
140 #define I82577_PHY_DIAG_STATUS 31
142 /* I82577 PHY Status 2 */
143 #define I82577_PHY_STATUS2_REV_POLARITY 0x0400
144 #define I82577_PHY_STATUS2_MDIX 0x0800
145 #define I82577_PHY_STATUS2_SPEED_MASK 0x0300
146 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
148 /* I82577 PHY Control 2 */
149 #define I82577_PHY_CTRL2_MANUAL_MDIX 0x0200
150 #define I82577_PHY_CTRL2_AUTO_MDI_MDIX 0x0400
151 #define I82577_PHY_CTRL2_MDIX_CFG_MASK 0x0600
153 /* I82577 PHY Diagnostics Status */
154 #define I82577_DSTATUS_CABLE_LENGTH 0x03FC
155 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
157 /* 82580 PHY Power Management */
158 #define E1000_82580_PHY_POWER_MGMT 0xE14
159 #define E1000_82580_PM_SPD 0x0001 /* Smart Power Down */
160 #define E1000_82580_PM_D0_LPLU 0x0002 /* For D0a states */
161 #define E1000_82580_PM_D3_LPLU 0x0004 /* For all other states */
162 #define E1000_82580_PM_GO_LINKD 0x0020 /* Go Link Disconnect */
164 #define E1000_MPHY_DIS_ACCESS 0x80000000 /* disable_access bit */
165 #define E1000_MPHY_ENA_ACCESS 0x40000000 /* enable_access bit */
166 #define E1000_MPHY_BUSY 0x00010000 /* busy bit */
167 #define E1000_MPHY_ADDRESS_FNC_OVERRIDE 0x20000000 /* fnc_override bit */
168 #define E1000_MPHY_ADDRESS_MASK 0x0000FFFF /* address mask */
170 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
171 #define IGP01E1000_PHY_POLARITY_MASK 0x0078
173 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000
174 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
176 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080
178 #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
179 #define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
180 #define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
182 #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
184 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
185 #define IGP01E1000_PSSR_MDIX 0x0800
186 #define IGP01E1000_PSSR_SPEED_MASK 0xC000
187 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
189 #define IGP02E1000_PHY_CHANNEL_NUM 4
190 #define IGP02E1000_PHY_AGC_A 0x11B1
191 #define IGP02E1000_PHY_AGC_B 0x12B1
192 #define IGP02E1000_PHY_AGC_C 0x14B1
193 #define IGP02E1000_PHY_AGC_D 0x18B1
195 #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course=15:13, Fine=12:9 */
196 #define IGP02E1000_AGC_LENGTH_MASK 0x7F
197 #define IGP02E1000_AGC_RANGE 15
199 #define E1000_CABLE_LENGTH_UNDEFINED 0xFF
201 #define E1000_KMRNCTRLSTA_OFFSET 0x001F0000
202 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16
203 #define E1000_KMRNCTRLSTA_REN 0x00200000
204 #define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */
205 #define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */
206 #define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */
207 #define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */
208 #define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */
210 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
211 #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Ctrl */
212 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Ctrl */
213 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
215 /* IFE PHY Extended Status Control */
216 #define IFE_PESC_POLARITY_REVERSED 0x0100
218 /* IFE PHY Special Control */
219 #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
220 #define IFE_PSC_FORCE_POLARITY 0x0020
222 /* IFE PHY Special Control and LED Control */
223 #define IFE_PSCL_PROBE_MODE 0x0020
224 #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
225 #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
227 /* IFE PHY MDIX Control */
228 #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
229 #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */
230 #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto, 0=disable */
232 /* SFP modules ID memory locations */
233 #define E1000_SFF_IDENTIFIER_OFFSET 0x00
234 #define E1000_SFF_IDENTIFIER_SFF 0x02
235 #define E1000_SFF_IDENTIFIER_SFP 0x03
237 #define E1000_SFF_ETH_FLAGS_OFFSET 0x06
238 /* Flags for SFP modules compatible with ETH up to 1Gb */
239 struct sfp_e1000_flags {
250 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
251 #define E1000_SFF_VENDOR_OUI_TYCO 0x00407600
252 #define E1000_SFF_VENDOR_OUI_FTL 0x00906500
253 #define E1000_SFF_VENDOR_OUI_AVAGO 0x00176A00
254 #define E1000_SFF_VENDOR_OUI_INTEL 0x001B2100