1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "LICENSE.GPL".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
35 #include <linux/pci.h>
36 #include <linux/netdevice.h>
37 #ifdef HAVE_IRQ_AFFINITY_HINT
38 #include <linux/cpumask.h>
39 #endif /* HAVE_IRQ_AFFINITY_HINT */
40 #include <linux/vmalloc.h>
43 #include <linux/ethtool.h>
45 #ifdef NETIF_F_HW_VLAN_TX
46 #include <linux/if_vlan.h>
48 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
50 #include <linux/dca.h>
52 #include "ixgbe_dcb.h"
57 #include <linux/sctp.h>
60 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
62 #include "ixgbe_fcoe.h"
63 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
65 #if defined(CONFIG_PTP_1588_CLOCK) || defined(CONFIG_PTP_1588_CLOCK_MODULE)
66 #define HAVE_IXGBE_PTP
69 #include "ixgbe_api.h"
72 #define DPRINTK(nlevel, klevel, fmt, args...) \
73 ((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
74 printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
77 /* TX/RX descriptor defines */
78 #define IXGBE_DEFAULT_TXD 512
79 #define IXGBE_DEFAULT_TX_WORK 256
80 #define IXGBE_MAX_TXD 4096
81 #define IXGBE_MIN_TXD 64
83 #define IXGBE_DEFAULT_RXD 512
84 #define IXGBE_DEFAULT_RX_WORK 256
85 #define IXGBE_MAX_RXD 4096
86 #define IXGBE_MIN_RXD 64
90 #define IXGBE_MIN_FCRTL 0x40
91 #define IXGBE_MAX_FCRTL 0x7FF80
92 #define IXGBE_MIN_FCRTH 0x600
93 #define IXGBE_MAX_FCRTH 0x7FFF0
94 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF
95 #define IXGBE_MIN_FCPAUSE 0
96 #define IXGBE_MAX_FCPAUSE 0xFFFF
98 /* Supported Rx Buffer Sizes */
99 #define IXGBE_RXBUFFER_512 512 /* Used for packet split */
100 #ifdef CONFIG_IXGBE_DISABLE_PACKET_SPLIT
101 #define IXGBE_RXBUFFER_1536 1536
102 #define IXGBE_RXBUFFER_2K 2048
103 #define IXGBE_RXBUFFER_3K 3072
104 #define IXGBE_RXBUFFER_4K 4096
105 #define IXGBE_RXBUFFER_7K 7168
106 #define IXGBE_RXBUFFER_8K 8192
107 #define IXGBE_RXBUFFER_15K 15360
108 #endif /* CONFIG_IXGBE_DISABLE_PACKET_SPLIT */
109 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for single descriptor */
112 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
113 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
114 * this adds up to 512 bytes of extra data meaning the smallest allocation
115 * we could have is 1K.
116 * i.e. RXBUFFER_512 --> size-1024 slab
118 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
120 #define MAXIMUM_ETHERNET_VLAN_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
122 /* How many Rx Buffers do we bundle into one write to the hardware ? */
123 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
125 #define IXGBE_TX_FLAGS_CSUM (u32)(1)
126 #define IXGBE_TX_FLAGS_HW_VLAN (u32)(1 << 1)
127 #define IXGBE_TX_FLAGS_SW_VLAN (u32)(1 << 2)
128 #define IXGBE_TX_FLAGS_TSO (u32)(1 << 3)
129 #define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 4)
130 #define IXGBE_TX_FLAGS_FCOE (u32)(1 << 5)
131 #define IXGBE_TX_FLAGS_FSO (u32)(1 << 6)
132 #define IXGBE_TX_FLAGS_TXSW (u32)(1 << 7)
133 #define IXGBE_TX_FLAGS_TSTAMP (u32)(1 << 8)
134 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
135 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
136 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29
137 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16
139 #define IXGBE_MAX_RX_DESC_POLL 10
141 #define IXGBE_MAX_VF_MC_ENTRIES 30
142 #define IXGBE_MAX_VF_FUNCTIONS 64
143 #define IXGBE_MAX_VFTA_ENTRIES 128
144 #define MAX_EMULATION_MAC_ADDRS 16
145 #define IXGBE_MAX_PF_MACVLANS 15
146 #define IXGBE_82599_VF_DEVICE_ID 0x10ED
147 #define IXGBE_X540_VF_DEVICE_ID 0x1515
149 #ifdef CONFIG_PCI_IOV
150 #define VMDQ_P(p) ((p) + adapter->num_vfs)
152 #define VMDQ_P(p) (p)
155 #define UPDATE_VF_COUNTER_32bit(reg, last_counter, counter) \
157 u32 current_counter = IXGBE_READ_REG(hw, reg); \
158 if (current_counter < last_counter) \
159 counter += 0x100000000LL; \
160 last_counter = current_counter; \
161 counter &= 0xFFFFFFFF00000000LL; \
162 counter |= current_counter; \
165 #define UPDATE_VF_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \
167 u64 current_counter_lsb = IXGBE_READ_REG(hw, reg_lsb); \
168 u64 current_counter_msb = IXGBE_READ_REG(hw, reg_msb); \
169 u64 current_counter = (current_counter_msb << 32) | \
170 current_counter_lsb; \
171 if (current_counter < last_counter) \
172 counter += 0x1000000000LL; \
173 last_counter = current_counter; \
174 counter &= 0xFFFFFFF000000000LL; \
175 counter |= current_counter; \
186 struct vf_data_storage {
187 unsigned char vf_mac_addresses[ETH_ALEN];
188 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
189 u16 num_vf_mc_hashes;
190 u16 default_vf_vlan_id;
193 struct vf_stats vfstats;
194 struct vf_stats last_vfstats;
195 struct vf_stats saved_rst_vfstats;
197 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
202 struct pci_dev *vfdev;
210 u8 vf_macvlan[ETH_ALEN];
214 #define IXGBE_LRO_MAX 32 /*Maximum number of LRO descriptors*/
215 #define IXGBE_LRO_GLOBAL 10
217 struct ixgbe_lro_stats {
223 * ixgbe_lro_header - header format to be aggregated by LRO
224 * @iph: IP header without options
226 * @ts: Optional TCP timestamp data in TCP options
228 * This structure relies on the check above that verifies that the header
229 * is IPv4 and does not contain any options.
231 struct ixgbe_lrohdr {
237 struct ixgbe_lro_list {
238 struct sk_buff_head active;
239 struct ixgbe_lro_stats stats;
242 #endif /* IXGBE_NO_LRO */
243 #define IXGBE_MAX_TXD_PWR 14
244 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
246 /* Tx Descriptors needed, worst case */
247 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
249 #define DESC_NEEDED ((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4)
251 #define DESC_NEEDED 4
254 /* wrapper around a pointer to a socket buffer,
255 * so a DMA handle can be stored along with the buffer */
256 struct ixgbe_tx_buffer {
257 union ixgbe_adv_tx_desc *next_to_watch;
258 unsigned long time_stamp;
260 unsigned int bytecount;
261 unsigned short gso_segs;
263 DEFINE_DMA_UNMAP_ADDR(dma);
264 DEFINE_DMA_UNMAP_LEN(len);
268 struct ixgbe_rx_buffer {
271 #ifndef CONFIG_IXGBE_DISABLE_PACKET_SPLIT
273 unsigned int page_offset;
277 struct ixgbe_queue_stats {
282 struct ixgbe_tx_queue_stats {
288 struct ixgbe_rx_queue_stats {
292 u64 alloc_rx_page_failed;
293 u64 alloc_rx_buff_failed;
297 enum ixgbe_ring_state_t {
298 __IXGBE_TX_FDIR_INIT_DONE,
299 __IXGBE_TX_DETECT_HANG,
300 __IXGBE_HANG_CHECK_ARMED,
301 __IXGBE_RX_RSC_ENABLED,
302 #ifndef HAVE_NDO_SET_FEATURES
303 __IXGBE_RX_CSUM_ENABLED,
305 __IXGBE_RX_CSUM_UDP_ZERO_ERR,
307 __IXGBE_RX_FCOE_BUFSZ,
311 #define check_for_tx_hang(ring) \
312 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
313 #define set_check_for_tx_hang(ring) \
314 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
315 #define clear_check_for_tx_hang(ring) \
316 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
317 #ifndef IXGBE_NO_HW_RSC
318 #define ring_is_rsc_enabled(ring) \
319 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
321 #define ring_is_rsc_enabled(ring) false
323 #define set_ring_rsc_enabled(ring) \
324 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
325 #define clear_ring_rsc_enabled(ring) \
326 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
327 #define netdev_ring(ring) (ring->netdev)
328 #define ring_queue_index(ring) (ring->queue_index)
332 struct ixgbe_ring *next; /* pointer to next ring in q_vector */
333 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */
334 struct net_device *netdev; /* netdev ring belongs to */
335 struct device *dev; /* device for DMA mapping */
336 void *desc; /* descriptor ring memory */
338 struct ixgbe_tx_buffer *tx_buffer_info;
339 struct ixgbe_rx_buffer *rx_buffer_info;
343 dma_addr_t dma; /* phys. address of descriptor ring */
344 unsigned int size; /* length in bytes */
346 u16 count; /* amount of descriptors */
348 u8 queue_index; /* needed for multiqueue queue management */
349 u8 reg_idx; /* holds the special value that gets
350 * the hardware register offset
351 * associated with this ring, which is
352 * different for DCB and RSS modes
358 #ifdef CONFIG_IXGBE_DISABLE_PACKET_SPLIT
370 struct ixgbe_queue_stats stats;
372 struct ixgbe_tx_queue_stats tx_stats;
373 struct ixgbe_rx_queue_stats rx_stats;
375 } ____cacheline_internodealigned_in_smp;
377 enum ixgbe_ring_f_enum {
379 RING_F_VMDQ, /* SR-IOV uses the same ring feature */
384 #endif /* IXGBE_FCOE */
385 RING_F_ARRAY_SIZE /* must be last in enum set */
388 #define IXGBE_MAX_DCB_INDICES 8
389 #define IXGBE_MAX_RSS_INDICES 16
390 #define IXGBE_MAX_VMDQ_INDICES 64
391 #define IXGBE_MAX_FDIR_INDICES 64
393 #define IXGBE_MAX_FCOE_INDICES 8
394 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
395 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
397 #define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
398 #define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
399 #endif /* IXGBE_FCOE */
400 struct ixgbe_ring_feature {
405 #ifndef CONFIG_IXGBE_DISABLE_PACKET_SPLIT
407 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since
408 * this is twice the size of a half page we need to double the page order
409 * for FCoE enabled Rx queues.
411 #if defined(IXGBE_FCOE) && (PAGE_SIZE < 8192)
412 static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring)
414 return test_bit(__IXGBE_RX_FCOE_BUFSZ, &ring->state) ? 1 : 0;
417 #define ixgbe_rx_pg_order(_ring) 0
419 #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring))
420 #define ixgbe_rx_bufsz(_ring) ((PAGE_SIZE / 2) << ixgbe_rx_pg_order(_ring))
423 struct ixgbe_ring_container {
424 struct ixgbe_ring *ring; /* pointer to linked list of rings */
425 unsigned int total_bytes; /* total bytes processed this int */
426 unsigned int total_packets; /* total packets processed this int */
427 u16 work_limit; /* total work allowed per interrupt */
428 u8 count; /* total number of rings in vector */
429 u8 itr; /* current ITR setting for ring */
432 /* iterator for handling rings in ring container */
433 #define ixgbe_for_each_ring(pos, head) \
434 for (pos = (head).ring; pos != NULL; pos = pos->next)
436 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
438 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
440 /* MAX_MSIX_Q_VECTORS of these are allocated,
441 * but we only use one per queue-specific vector.
443 struct ixgbe_q_vector {
444 struct ixgbe_adapter *adapter;
445 int cpu; /* CPU for DCA */
446 u16 v_idx; /* index of q_vector within array, also used for
447 * finding the bit in EICR and friends that
448 * represents the vector for this ring */
449 u16 itr; /* Interrupt throttle rate written to EITR */
450 struct ixgbe_ring_container rx, tx;
452 #ifdef CONFIG_IXGBE_NAPI
453 struct napi_struct napi;
455 #ifndef HAVE_NETDEV_NAPI_LIST
456 struct net_device poll_dev;
458 #ifdef HAVE_IRQ_AFFINITY_HINT
459 cpumask_t affinity_mask;
462 struct ixgbe_lro_list lrolist; /* LRO list for queue vector*/
465 char name[IFNAMSIZ + 9];
467 /* for dynamic allocation of rings associated with this q_vector */
468 struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp;
472 * microsecond values for various ITR rates shifted by 2 to fit itr register
473 * with the first 3 bits reserved 0
475 #define IXGBE_MIN_RSC_ITR 24
476 #define IXGBE_100K_ITR 40
477 #define IXGBE_20K_ITR 200
478 #define IXGBE_16K_ITR 248
479 #define IXGBE_10K_ITR 400
480 #define IXGBE_8K_ITR 500
482 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */
483 static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
484 const u32 stat_err_bits)
486 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
489 /* ixgbe_desc_unused - calculate if we have unused descriptors */
490 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
492 u16 ntc = ring->next_to_clean;
493 u16 ntu = ring->next_to_use;
495 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
498 #define IXGBE_RX_DESC(R, i) \
499 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
500 #define IXGBE_TX_DESC(R, i) \
501 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
502 #define IXGBE_TX_CTXTDESC(R, i) \
503 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
505 #define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
507 /* use 3K as the baby jumbo frame size for FCoE */
508 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
509 #endif /* IXGBE_FCOE */
511 #define TCP_TIMER_VECTOR 0
512 #define OTHER_VECTOR 1
513 #define NON_Q_VECTORS (OTHER_VECTOR + TCP_TIMER_VECTOR)
515 #define IXGBE_MAX_MSIX_Q_VECTORS_82599 64
516 #define IXGBE_MAX_MSIX_Q_VECTORS_82598 16
518 struct ixgbe_mac_addr {
521 u16 state; /* bitmask */
523 #define IXGBE_MAC_STATE_DEFAULT 0x1
524 #define IXGBE_MAC_STATE_MODIFIED 0x2
525 #define IXGBE_MAC_STATE_IN_USE 0x4
528 struct ixgbe_therm_proc_data {
530 struct ixgbe_thermal_diode_data *sensor_data;
533 #endif /* IXGBE_PROCFS */
536 * Only for array allocations in our adapter struct. On 82598, there will be
537 * unused entries in the array, but that's not a big deal. Also, in 82599,
538 * we can actually assign 64 queue vectors based on our extended-extended
539 * interrupt registers. This is different than 82598, which is limited to 16.
541 #define MAX_MSIX_Q_VECTORS IXGBE_MAX_MSIX_Q_VECTORS_82599
542 #define MAX_MSIX_COUNT IXGBE_MAX_MSIX_VECTORS_82599
544 #define MIN_MSIX_Q_VECTORS 1
545 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
547 /* default to trying for four seconds */
548 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
550 /* board specific private data structure */
551 struct ixgbe_adapter {
552 #ifdef NETIF_F_HW_VLAN_TX
553 #ifdef HAVE_VLAN_RX_REGISTER
554 struct vlan_group *vlgrp; /* must be first, see ixgbe_receive_skb */
556 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
558 #endif /* NETIF_F_HW_VLAN_TX */
559 /* OS defined structs */
560 struct net_device *netdev;
561 struct pci_dev *pdev;
565 /* Some features need tri-state capability,
566 * thus the additional *_CAPABLE flags.
569 #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 0)
570 #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 1)
571 #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 2)
572 #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 3)
574 #define IXGBE_FLAG_LLI_PUSH (u32)(1 << 4)
576 #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 8)
577 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
578 #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 9)
579 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 10)
580 #define IXGBE_FLAG_DCA_ENABLED_DATA (u32)(1 << 11)
582 #define IXGBE_FLAG_DCA_ENABLED (u32)0
583 #define IXGBE_FLAG_DCA_CAPABLE (u32)0
584 #define IXGBE_FLAG_DCA_ENABLED_DATA (u32)0
586 #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 12)
587 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 13)
588 #define IXGBE_FLAG_DCB_CAPABLE (u32)(1 << 14)
589 #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 15)
590 #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 16)
591 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 18)
592 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 19)
593 #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 20)
594 #define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 21)
595 #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 22)
596 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 23)
598 #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 24)
599 #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 25)
600 #endif /* IXGBE_FCOE */
601 #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 26)
602 #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 27)
603 #define IXGBE_FLAG_SRIOV_REPLICATION_ENABLE (u32)(1 << 28)
604 #define IXGBE_FLAG_SRIOV_L2SWITCH_ENABLE (u32)(1 << 29)
605 #define IXGBE_FLAG_SRIOV_L2LOOPBACK_ENABLE (u32)(1 << 30)
606 #define IXGBE_FLAG_RX_BB_CAPABLE (u32)(1 << 31)
609 #ifndef IXGBE_NO_HW_RSC
610 #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
611 #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
613 #define IXGBE_FLAG2_RSC_CAPABLE 0
614 #define IXGBE_FLAG2_RSC_ENABLED 0
616 #define IXGBE_FLAG2_VMDQ_DEFAULT_OVERRIDE (u32)(1 << 2)
617 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 4)
618 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 5)
619 #define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 6)
620 #define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 7)
621 #define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 8)
622 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 9)
623 #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 10)
624 #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 11)
625 #define IXGBE_FLAG2_OVERFLOW_CHECK_ENABLED (u32)(1 << 12)
627 /* Tx fast path data */
632 /* Rx fast path data */
638 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
642 u32 tx_timeout_count;
645 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES];
646 int num_rx_pools; /* == num_rx_queues in 82598 */
647 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
648 u64 hw_csum_rx_error;
649 u64 hw_rx_no_dma_resources;
653 #ifndef CONFIG_IXGBE_NAPI
654 u64 rx_dropped_backlog; /* count drops from rx intr handler */
656 u32 alloc_rx_page_failed;
657 u32 alloc_rx_buff_failed;
659 struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
661 #ifdef HAVE_DCBNL_IEEE
662 struct ieee_pfc *ixgbe_ieee_pfc;
663 struct ieee_ets *ixgbe_ieee_ets;
665 struct ixgbe_dcb_config dcb_cfg;
666 struct ixgbe_dcb_config temp_dcb_cfg;
672 enum ixgbe_fc_mode last_lfc_mode;
674 int num_msix_vectors;
675 int max_msix_q_vectors; /* true count of q_vectors for device */
676 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
677 struct msix_entry *msix_entries;
679 #ifndef HAVE_NETDEV_STATS_IN_NETDEV
680 struct net_device_stats net_stats;
683 struct ixgbe_lro_stats lro_stats;
688 struct ixgbe_ring test_tx_ring;
689 struct ixgbe_ring test_rx_ring;
692 /* structs defined in ixgbe_hw.h */
695 struct ixgbe_hw_stats stats;
701 #endif /* IXGBE_NO_LLI */
705 unsigned int tx_ring_count;
706 unsigned int rx_ring_count;
710 unsigned long link_check_timeout;
712 struct timer_list service_timer;
713 struct work_struct service_task;
715 struct hlist_head fdir_filter_list;
716 unsigned long fdir_overflow; /* number of times ATR was backed off */
717 union ixgbe_atr_input fdir_mask;
718 int fdir_filter_count;
721 spinlock_t fdir_perfect_lock;
724 struct ixgbe_fcoe fcoe;
725 #endif /* IXGBE_FCOE */
732 bool netdev_registered;
734 #ifdef HAVE_ETHTOOL_SET_PHYS_ID
738 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
739 unsigned int num_vfs;
740 struct vf_data_storage *vfinfo;
741 int vf_rate_link_speed;
742 struct vf_macvlans vf_mvs;
743 struct vf_macvlans *mv_list;
744 #ifdef CONFIG_PCI_IOV
745 u32 timer_event_accumulator;
748 struct ixgbe_mac_addr *mac_table;
750 struct kobject *info_kobj;
751 struct kobject *therm_kobj[IXGBE_MAX_SENSORS];
752 #else /* IXGBE_SYSFS */
754 struct proc_dir_entry *eth_dir;
755 struct proc_dir_entry *info_dir;
756 struct proc_dir_entry *therm_dir[IXGBE_MAX_SENSORS];
757 struct ixgbe_therm_proc_data therm_data[IXGBE_MAX_SENSORS];
758 #endif /* IXGBE_PROCFS */
759 #endif /* IXGBE_SYSFS */
762 struct ixgbe_fdir_filter {
763 struct hlist_node fdir_node;
764 union ixgbe_atr_input filter;
773 __IXGBE_SERVICE_SCHED,
778 #ifdef CONFIG_IXGBE_DISABLE_PACKET_SPLIT
779 union { /* Union defining head/tail partner */
780 struct sk_buff *head;
781 struct sk_buff *tail;
786 __be32 tsecr; /* timestamp echo response */
787 u32 tsval; /* timestamp value in host order */
788 u32 next_seq; /* next expected sequence number */
789 u16 free; /* 65521 minus total size */
790 u16 mss; /* size of data portion of packet */
791 #endif /* IXGBE_NO_LRO */
792 #ifdef HAVE_VLAN_RX_REGISTER
793 u16 vid; /* VLAN tag */
795 u16 append_cnt; /* number of skb's appended */
796 #ifndef CONFIG_IXGBE_DISABLE_PACKET_SPLIT
800 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb)
803 void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter);
804 int ixgbe_sysfs_init(struct ixgbe_adapter *adapter);
805 #endif /* IXGBE_SYSFS */
807 void ixgbe_procfs_exit(struct ixgbe_adapter *adapter);
808 int ixgbe_procfs_init(struct ixgbe_adapter *adapter);
809 int ixgbe_procfs_topdir_init(void);
810 void ixgbe_procfs_topdir_exit(void);
811 #endif /* IXGBE_PROCFS */
813 extern struct dcbnl_rtnl_ops dcbnl_ops;
814 extern int ixgbe_copy_dcb_cfg(struct ixgbe_adapter *adapter, int tc_max);
816 extern u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 index);
818 /* needed by ixgbe_main.c */
819 extern int ixgbe_validate_mac_addr(u8 *mc_addr);
820 extern void ixgbe_check_options(struct ixgbe_adapter *adapter);
821 extern void ixgbe_assign_netdev_ops(struct net_device *netdev);
823 /* needed by ixgbe_ethtool.c */
824 extern char ixgbe_driver_name[];
825 extern const char ixgbe_driver_version[];
827 extern void ixgbe_up(struct ixgbe_adapter *adapter);
828 extern void ixgbe_down(struct ixgbe_adapter *adapter);
829 extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
830 extern void ixgbe_reset(struct ixgbe_adapter *adapter);
831 extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
832 extern int ixgbe_setup_rx_resources(struct ixgbe_ring *);
833 extern int ixgbe_setup_tx_resources(struct ixgbe_ring *);
834 extern void ixgbe_free_rx_resources(struct ixgbe_ring *);
835 extern void ixgbe_free_tx_resources(struct ixgbe_ring *);
836 extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,
837 struct ixgbe_ring *);
838 extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,
839 struct ixgbe_ring *);
840 extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
841 extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
842 extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
843 extern bool ixgbe_is_ixgbe(struct pci_dev *pcidev);
844 extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
845 struct ixgbe_adapter *,
846 struct ixgbe_ring *);
847 extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
848 struct ixgbe_tx_buffer *);
849 extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
850 extern void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
851 struct ixgbe_ring *);
852 extern void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
853 struct ixgbe_ring *);
854 extern void ixgbe_set_rx_mode(struct net_device *netdev);
855 extern int ixgbe_write_mc_addr_list(struct net_device *netdev);
856 extern int ixgbe_setup_tc(struct net_device *dev, u8 tc);
858 extern void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
859 #endif /* IXGBE_FCOE */
860 extern void ixgbe_do_reset(struct net_device *netdev);
861 extern void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector);
862 extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
863 struct ixgbe_ring *);
864 extern void ixgbe_vlan_stripping_enable(struct ixgbe_adapter *adapter);
865 extern void ixgbe_vlan_stripping_disable(struct ixgbe_adapter *adapter);
866 #ifdef ETHTOOL_OPS_COMPAT
867 extern int ethtool_ioctl(struct ifreq *ifr);
871 extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
872 extern int ixgbe_fso(struct ixgbe_ring *tx_ring,
873 struct ixgbe_tx_buffer *first,
875 extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
876 extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
877 union ixgbe_adv_rx_desc *rx_desc,
878 struct sk_buff *skb);
879 extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
880 struct scatterlist *sgl, unsigned int sgc);
881 #ifdef HAVE_NETDEV_OPS_FCOE_DDP_TARGET
882 extern int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
883 struct scatterlist *sgl, unsigned int sgc);
884 #endif /* HAVE_NETDEV_OPS_FCOE_DDP_TARGET */
885 extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
886 #ifdef HAVE_NETDEV_OPS_FCOE_ENABLE
887 extern int ixgbe_fcoe_enable(struct net_device *netdev);
888 extern int ixgbe_fcoe_disable(struct net_device *netdev);
889 #endif /* HAVE_NETDEV_OPS_FCOE_ENABLE */
891 #ifdef HAVE_DCBNL_OPS_GETAPP
892 extern u8 ixgbe_fcoe_getapp(struct net_device *netdev);
893 #endif /* HAVE_DCBNL_OPS_GETAPP */
894 extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
895 #endif /* CONFIG_DCB */
896 #ifdef HAVE_NETDEV_OPS_FCOE_GETWWN
897 extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
899 #endif /* IXGBE_FCOE */
902 #ifdef HAVE_DCBNL_IEEE
903 s32 ixgbe_dcb_hw_ets(struct ixgbe_hw *hw, struct ieee_ets *ets, int max_frame);
904 #endif /* HAVE_DCBNL_IEEE */
905 #endif /* CONFIG_DCB */
907 extern void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring);
908 extern int ixgbe_get_settings(struct net_device *netdev,
909 struct ethtool_cmd *ecmd);
910 extern int ixgbe_write_uc_addr_list(struct ixgbe_adapter *adapter,
911 struct net_device *netdev, unsigned int vfn);
912 extern void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter);
913 extern int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
914 u8 *addr, u16 queue);
915 extern int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
916 u8 *addr, u16 queue);
917 extern int ixgbe_available_rars(struct ixgbe_adapter *adapter);
918 #ifndef HAVE_VLAN_RX_REGISTER
919 extern void ixgbe_vlan_mode(struct net_device *, u32);
921 #ifndef ixgbe_get_netdev_tc_txq
922 #define ixgbe_get_netdev_tc_txq(dev, tc) (&dev->tc_to_txq[tc])
924 extern void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter);
925 #endif /* _IXGBE_H_ */