1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "LICENSE.GPL".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include "ixgbe_type.h"
29 #include "ixgbe_82599.h"
30 #include "ixgbe_api.h"
31 #include "ixgbe_common.h"
32 #include "ixgbe_phy.h"
34 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
35 ixgbe_link_speed speed,
37 bool autoneg_wait_to_complete);
38 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
39 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
40 u16 offset, u16 *data);
41 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
42 u16 words, u16 *data);
43 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
44 u8 dev_addr, u8 *data);
45 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
46 u8 dev_addr, u8 data);
48 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
50 struct ixgbe_mac_info *mac = &hw->mac;
52 /* enable the laser control functions for SFP+ fiber */
53 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
54 mac->ops.disable_tx_laser =
55 &ixgbe_disable_tx_laser_multispeed_fiber;
56 mac->ops.enable_tx_laser =
57 &ixgbe_enable_tx_laser_multispeed_fiber;
58 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
61 mac->ops.disable_tx_laser = NULL;
62 mac->ops.enable_tx_laser = NULL;
63 mac->ops.flap_tx_laser = NULL;
66 if (hw->phy.multispeed_fiber) {
67 /* Set up dual speed SFP+ support */
68 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
70 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
71 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
72 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
73 !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
74 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
76 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
82 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
83 * @hw: pointer to hardware structure
85 * Initialize any function pointers that were not able to be
86 * set during init_shared_code because the PHY/SFP type was
87 * not known. Perform the SFP init if necessary.
90 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
92 struct ixgbe_mac_info *mac = &hw->mac;
93 struct ixgbe_phy_info *phy = &hw->phy;
97 if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) {
98 /* Store flag indicating I2C bus access control unit. */
99 hw->phy.qsfp_shared_i2c_bus = TRUE;
101 /* Initialize access to QSFP+ I2C bus */
102 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
103 esdp |= IXGBE_ESDP_SDP0_DIR;
104 esdp &= ~IXGBE_ESDP_SDP1_DIR;
105 esdp &= ~IXGBE_ESDP_SDP0;
106 esdp &= ~IXGBE_ESDP_SDP0_NATIVE;
107 esdp &= ~IXGBE_ESDP_SDP1_NATIVE;
108 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
109 IXGBE_WRITE_FLUSH(hw);
111 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_82599;
112 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_82599;
114 /* Identify the PHY or SFP module */
115 ret_val = phy->ops.identify(hw);
116 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
117 goto init_phy_ops_out;
119 /* Setup function pointers based on detected SFP module and speeds */
120 ixgbe_init_mac_link_ops_82599(hw);
121 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown)
122 hw->phy.ops.reset = NULL;
124 /* If copper media, overwrite with copper function pointers */
125 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
126 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
127 mac->ops.get_link_capabilities =
128 &ixgbe_get_copper_link_capabilities_generic;
131 /* Set necessary function pointers based on phy type */
132 switch (hw->phy.type) {
134 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
135 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
136 phy->ops.get_firmware_version =
137 &ixgbe_get_phy_firmware_version_tnx;
146 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
151 u16 list_offset, data_offset, data_value;
153 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
154 ixgbe_init_mac_link_ops_82599(hw);
156 hw->phy.ops.reset = NULL;
158 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
163 /* PHY config will finish before releasing the semaphore */
164 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
165 IXGBE_GSSR_MAC_CSR_SM);
167 ret_val = IXGBE_ERR_SWFW_SYNC;
171 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
172 while (data_value != 0xffff) {
173 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
174 IXGBE_WRITE_FLUSH(hw);
175 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
178 /* Release the semaphore */
179 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
180 /* Delay obtaining semaphore again to allow FW access */
181 msleep(hw->eeprom.semaphore_delay);
183 /* Now restart DSP by setting Restart_AN and clearing LMS */
184 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
185 IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) |
186 IXGBE_AUTOC_AN_RESTART));
188 /* Wait for AN to leave state 0 */
189 for (i = 0; i < 10; i++) {
191 reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);
192 if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)
195 if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) {
196 hw_dbg(hw, "sfp module setup not complete\n");
197 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
201 /* Restart DSP by setting Restart_AN and return to SFI mode */
202 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
203 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL |
204 IXGBE_AUTOC_AN_RESTART));
212 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
213 * @hw: pointer to hardware structure
215 * Initialize the function pointers and assign the MAC type for 82599.
216 * Does not touch the hardware.
219 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
221 struct ixgbe_mac_info *mac = &hw->mac;
222 struct ixgbe_phy_info *phy = &hw->phy;
223 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
226 ixgbe_init_phy_ops_generic(hw);
227 ret_val = ixgbe_init_ops_generic(hw);
230 phy->ops.identify = &ixgbe_identify_phy_82599;
231 phy->ops.init = &ixgbe_init_phy_ops_82599;
234 mac->ops.reset_hw = &ixgbe_reset_hw_82599;
235 mac->ops.get_media_type = &ixgbe_get_media_type_82599;
236 mac->ops.get_supported_physical_layer =
237 &ixgbe_get_supported_physical_layer_82599;
238 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
239 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
240 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599;
241 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599;
242 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599;
243 mac->ops.start_hw = &ixgbe_start_hw_82599;
244 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
245 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
246 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
247 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
248 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
250 /* RAR, Multicast, VLAN */
251 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
252 mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
253 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
254 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
255 mac->rar_highwater = 1;
256 mac->ops.set_vfta = &ixgbe_set_vfta_generic;
257 mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
258 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
259 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
260 mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599;
261 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
262 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
265 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599;
266 mac->ops.check_link = &ixgbe_check_mac_link_generic;
267 mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
268 ixgbe_init_mac_link_ops_82599(hw);
270 mac->mcft_size = 128;
272 mac->num_rar_entries = 128;
273 mac->rx_pb_size = 512;
274 mac->max_tx_queues = 128;
275 mac->max_rx_queues = 128;
276 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
278 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
279 IXGBE_FWSM_MODE_MASK) ? true : false;
281 //hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
284 eeprom->ops.read = &ixgbe_read_eeprom_82599;
285 eeprom->ops.read_buffer = &ixgbe_read_eeprom_buffer_82599;
287 /* Manageability interface */
288 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
290 mac->ops.get_thermal_sensor_data =
291 &ixgbe_get_thermal_sensor_data_generic;
292 mac->ops.init_thermal_sensor_thresh =
293 &ixgbe_init_thermal_sensor_thresh_generic;
299 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
300 * @hw: pointer to hardware structure
301 * @speed: pointer to link speed
302 * @negotiation: true when autoneg or autotry is enabled
304 * Determines the link capabilities by reading the AUTOC register.
306 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
307 ixgbe_link_speed *speed,
313 /* Check if 1G SFP module. */
314 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
315 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
316 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
317 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
318 *speed = IXGBE_LINK_SPEED_1GB_FULL;
324 * Determine link capabilities based on the stored value of AUTOC,
325 * which represents EEPROM defaults. If AUTOC value has not
326 * been stored, use the current register values.
328 if (hw->mac.orig_link_settings_stored)
329 autoc = hw->mac.orig_autoc;
331 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
333 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
334 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
335 *speed = IXGBE_LINK_SPEED_1GB_FULL;
336 *negotiation = false;
339 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
340 *speed = IXGBE_LINK_SPEED_10GB_FULL;
341 *negotiation = false;
344 case IXGBE_AUTOC_LMS_1G_AN:
345 *speed = IXGBE_LINK_SPEED_1GB_FULL;
349 case IXGBE_AUTOC_LMS_10G_SERIAL:
350 *speed = IXGBE_LINK_SPEED_10GB_FULL;
351 *negotiation = false;
354 case IXGBE_AUTOC_LMS_KX4_KX_KR:
355 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
356 *speed = IXGBE_LINK_SPEED_UNKNOWN;
357 if (autoc & IXGBE_AUTOC_KR_SUPP)
358 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
359 if (autoc & IXGBE_AUTOC_KX4_SUPP)
360 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
361 if (autoc & IXGBE_AUTOC_KX_SUPP)
362 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
366 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
367 *speed = IXGBE_LINK_SPEED_100_FULL;
368 if (autoc & IXGBE_AUTOC_KR_SUPP)
369 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
370 if (autoc & IXGBE_AUTOC_KX4_SUPP)
371 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
372 if (autoc & IXGBE_AUTOC_KX_SUPP)
373 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
377 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
378 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
379 *negotiation = false;
383 status = IXGBE_ERR_LINK_SETUP;
388 if (hw->phy.multispeed_fiber) {
389 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
390 IXGBE_LINK_SPEED_1GB_FULL;
399 * ixgbe_get_media_type_82599 - Get media type
400 * @hw: pointer to hardware structure
402 * Returns the media type (fiber, copper, backplane)
404 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
406 enum ixgbe_media_type media_type;
408 /* Detect if there is a copper PHY attached. */
409 switch (hw->phy.type) {
410 case ixgbe_phy_cu_unknown:
412 media_type = ixgbe_media_type_copper;
418 switch (hw->device_id) {
419 case IXGBE_DEV_ID_82599_KX4:
420 case IXGBE_DEV_ID_82599_KX4_MEZZ:
421 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
422 case IXGBE_DEV_ID_82599_KR:
423 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
424 case IXGBE_DEV_ID_82599_XAUI_LOM:
425 /* Default device ID is mezzanine card KX/KX4 */
426 media_type = ixgbe_media_type_backplane;
428 case IXGBE_DEV_ID_82599_SFP:
429 case IXGBE_DEV_ID_82599_SFP_FCOE:
430 case IXGBE_DEV_ID_82599_SFP_EM:
431 case IXGBE_DEV_ID_82599_SFP_SF2:
432 case IXGBE_DEV_ID_82599EN_SFP:
433 media_type = ixgbe_media_type_fiber;
435 case IXGBE_DEV_ID_82599_CX4:
436 media_type = ixgbe_media_type_cx4;
438 case IXGBE_DEV_ID_82599_T3_LOM:
439 media_type = ixgbe_media_type_copper;
441 case IXGBE_DEV_ID_82599_LS:
442 media_type = ixgbe_media_type_fiber_lco;
444 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
445 media_type = ixgbe_media_type_fiber_qsfp;
448 media_type = ixgbe_media_type_unknown;
456 * ixgbe_start_mac_link_82599 - Setup MAC link settings
457 * @hw: pointer to hardware structure
458 * @autoneg_wait_to_complete: true when waiting for completion is needed
460 * Configures link settings based on values in the ixgbe_hw struct.
461 * Restarts the link. Performs autonegotiation if needed.
463 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
464 bool autoneg_wait_to_complete)
472 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
473 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
474 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
476 /* Only poll for autoneg to complete if specified to do so */
477 if (autoneg_wait_to_complete) {
478 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
479 IXGBE_AUTOC_LMS_KX4_KX_KR ||
480 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
481 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
482 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
483 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
484 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
485 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
486 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
490 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
491 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
492 hw_dbg(hw, "Autoneg did not complete.\n");
497 /* Add delay to filter out noises during initial link setup */
504 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
505 * @hw: pointer to hardware structure
507 * The base drivers may require better control over SFP+ module
508 * PHY states. This includes selectively shutting down the Tx
509 * laser on the PHY, effectively halting physical link.
511 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
513 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
515 /* Disable tx laser; allow 100us to go dark per spec */
516 esdp_reg |= IXGBE_ESDP_SDP3;
517 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
518 IXGBE_WRITE_FLUSH(hw);
523 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
524 * @hw: pointer to hardware structure
526 * The base drivers may require better control over SFP+ module
527 * PHY states. This includes selectively turning on the Tx
528 * laser on the PHY, effectively starting physical link.
530 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
532 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
534 /* Enable tx laser; allow 100ms to light up */
535 esdp_reg &= ~IXGBE_ESDP_SDP3;
536 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
537 IXGBE_WRITE_FLUSH(hw);
542 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
543 * @hw: pointer to hardware structure
545 * When the driver changes the link speeds that it can support,
546 * it sets autotry_restart to true to indicate that we need to
547 * initiate a new autotry session with the link partner. To do
548 * so, we set the speed then disable and re-enable the tx laser, to
549 * alert the link partner that it also needs to restart autotry on its
550 * end. This is consistent with true clause 37 autoneg, which also
551 * involves a loss of signal.
553 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
555 if (hw->mac.autotry_restart) {
556 ixgbe_disable_tx_laser_multispeed_fiber(hw);
557 ixgbe_enable_tx_laser_multispeed_fiber(hw);
558 hw->mac.autotry_restart = false;
563 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
564 * @hw: pointer to hardware structure
565 * @speed: new link speed
566 * @autoneg: true if autonegotiation enabled
567 * @autoneg_wait_to_complete: true when waiting for completion is needed
569 * Set the link speed in the AUTOC register and restarts link.
571 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
572 ixgbe_link_speed speed, bool autoneg,
573 bool autoneg_wait_to_complete)
576 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
577 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
579 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
581 bool link_up = false;
584 /* Mask off requested but non-supported speeds */
585 status = ixgbe_get_link_capabilities(hw, &link_speed, &negotiation);
592 * Try each speed one by one, highest priority first. We do this in
593 * software because 10gb fiber doesn't support speed autonegotiation.
595 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
597 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
599 /* If we already have link at this speed, just jump out */
600 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
604 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
607 /* Set the module link speed */
608 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
609 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
610 IXGBE_WRITE_FLUSH(hw);
612 /* Allow module to change analog characteristics (1G->10G) */
615 status = ixgbe_setup_mac_link_82599(hw,
616 IXGBE_LINK_SPEED_10GB_FULL,
618 autoneg_wait_to_complete);
622 /* Flap the tx laser if it has not already been done */
623 ixgbe_flap_tx_laser(hw);
626 * Wait for the controller to acquire link. Per IEEE 802.3ap,
627 * Section 73.10.2, we may have to wait up to 500ms if KR is
628 * attempted. 82599 uses the same timing for 10g SFI.
630 for (i = 0; i < 5; i++) {
631 /* Wait for the link partner to also set speed */
634 /* If we have link, just jump out */
635 status = ixgbe_check_link(hw, &link_speed,
645 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
647 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
648 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
650 /* If we already have link at this speed, just jump out */
651 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
655 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
658 /* Set the module link speed */
659 esdp_reg &= ~IXGBE_ESDP_SDP5;
660 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
661 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
662 IXGBE_WRITE_FLUSH(hw);
664 /* Allow module to change analog characteristics (10G->1G) */
667 status = ixgbe_setup_mac_link_82599(hw,
668 IXGBE_LINK_SPEED_1GB_FULL,
670 autoneg_wait_to_complete);
674 /* Flap the tx laser if it has not already been done */
675 ixgbe_flap_tx_laser(hw);
677 /* Wait for the link partner to also set speed */
680 /* If we have link, just jump out */
681 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
690 * We didn't get link. Configure back to the highest speed we tried,
691 * (if there was more than one). We call ourselves back with just the
692 * single highest speed that the user requested.
695 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
696 highest_link_speed, autoneg, autoneg_wait_to_complete);
699 /* Set autoneg_advertised value based on input link speed */
700 hw->phy.autoneg_advertised = 0;
702 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
703 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
705 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
706 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
712 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
713 * @hw: pointer to hardware structure
714 * @speed: new link speed
715 * @autoneg: true if autonegotiation enabled
716 * @autoneg_wait_to_complete: true when waiting for completion is needed
718 * Implements the Intel SmartSpeed algorithm.
720 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
721 ixgbe_link_speed speed, bool autoneg,
722 bool autoneg_wait_to_complete)
725 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
727 bool link_up = false;
728 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
730 /* Set autoneg_advertised value based on input link speed */
731 hw->phy.autoneg_advertised = 0;
733 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
734 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
736 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
737 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
739 if (speed & IXGBE_LINK_SPEED_100_FULL)
740 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
743 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
744 * autoneg advertisement if link is unable to be established at the
745 * highest negotiated rate. This can sometimes happen due to integrity
746 * issues with the physical media connection.
749 /* First, try to get link with full advertisement */
750 hw->phy.smart_speed_active = false;
751 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
752 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
753 autoneg_wait_to_complete);
758 * Wait for the controller to acquire link. Per IEEE 802.3ap,
759 * Section 73.10.2, we may have to wait up to 500ms if KR is
760 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
761 * Table 9 in the AN MAS.
763 for (i = 0; i < 5; i++) {
766 /* If we have link, just jump out */
767 status = ixgbe_check_link(hw, &link_speed, &link_up,
778 * We didn't get link. If we advertised KR plus one of KX4/KX
779 * (or BX4/BX), then disable KR and try again.
781 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
782 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
785 /* Turn SmartSpeed on to disable KR support */
786 hw->phy.smart_speed_active = true;
787 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
788 autoneg_wait_to_complete);
793 * Wait for the controller to acquire link. 600ms will allow for
794 * the AN link_fail_inhibit_timer as well for multiple cycles of
795 * parallel detect, both 10g and 1g. This allows for the maximum
796 * connect attempts as defined in the AN MAS table 73-7.
798 for (i = 0; i < 6; i++) {
801 /* If we have link, just jump out */
802 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
810 /* We didn't get link. Turn SmartSpeed back off. */
811 hw->phy.smart_speed_active = false;
812 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
813 autoneg_wait_to_complete);
816 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
817 hw_dbg(hw, "Smartspeed has downgraded the link speed "
818 "from the maximum advertised\n");
823 * ixgbe_setup_mac_link_82599 - Set MAC link speed
824 * @hw: pointer to hardware structure
825 * @speed: new link speed
826 * @autoneg: true if autonegotiation enabled
827 * @autoneg_wait_to_complete: true when waiting for completion is needed
829 * Set the link speed in the AUTOC register and restarts link.
831 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
832 ixgbe_link_speed speed, bool autoneg,
833 bool autoneg_wait_to_complete)
836 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
837 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
838 u32 start_autoc = autoc;
840 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
841 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
842 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
845 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
847 /* Check to see if speed passed in is supported. */
848 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
852 speed &= link_capabilities;
854 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
855 status = IXGBE_ERR_LINK_SETUP;
859 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
860 if (hw->mac.orig_link_settings_stored)
861 orig_autoc = hw->mac.orig_autoc;
865 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
866 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
867 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
868 /* Set KX4/KX/KR support according to speed requested */
869 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
870 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
871 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
872 autoc |= IXGBE_AUTOC_KX4_SUPP;
873 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
874 (hw->phy.smart_speed_active == false))
875 autoc |= IXGBE_AUTOC_KR_SUPP;
877 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
878 autoc |= IXGBE_AUTOC_KX_SUPP;
879 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
880 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
881 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
882 /* Switch from 1G SFI to 10G SFI if requested */
883 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
884 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
885 autoc &= ~IXGBE_AUTOC_LMS_MASK;
886 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
888 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
889 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
890 /* Switch from 10G SFI to 1G SFI if requested */
891 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
892 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
893 autoc &= ~IXGBE_AUTOC_LMS_MASK;
895 autoc |= IXGBE_AUTOC_LMS_1G_AN;
897 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
901 if (autoc != start_autoc) {
903 autoc |= IXGBE_AUTOC_AN_RESTART;
904 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
906 /* Only poll for autoneg to complete if specified to do so */
907 if (autoneg_wait_to_complete) {
908 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
909 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
910 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
911 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
913 IXGBE_READ_REG(hw, IXGBE_LINKS);
914 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
918 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
920 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
921 hw_dbg(hw, "Autoneg did not complete.\n");
926 /* Add delay to filter out noises during initial link setup */
935 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
936 * @hw: pointer to hardware structure
937 * @speed: new link speed
938 * @autoneg: true if autonegotiation enabled
939 * @autoneg_wait_to_complete: true if waiting is needed to complete
941 * Restarts link on PHY and MAC based on settings passed in.
943 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
944 ixgbe_link_speed speed,
946 bool autoneg_wait_to_complete)
950 /* Setup the PHY according to input speed */
951 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
952 autoneg_wait_to_complete);
954 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
960 * ixgbe_reset_hw_82599 - Perform hardware reset
961 * @hw: pointer to hardware structure
963 * Resets the hardware by resetting the transmit and receive units, masks
964 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
967 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
969 // ixgbe_link_speed link_speed;
971 // u32 ctrl, i, autoc, autoc2;
972 // bool link_up = false;
975 /* Call adapter stop to disable tx/rx and clear interrupts */
976 status = hw->mac.ops.stop_adapter(hw);
980 /* flush pending Tx transactions */
981 ixgbe_clear_tx_pending(hw);
983 /* PHY ops must be identified and initialized prior to reset */
985 /* Identify PHY and related function pointers */
986 status = hw->phy.ops.init(hw);
988 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
991 /* Setup SFP module if there is one present. */
992 if (hw->phy.sfp_setup_needed) {
993 status = hw->mac.ops.setup_sfp(hw);
994 hw->phy.sfp_setup_needed = false;
997 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1001 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
1002 hw->phy.ops.reset(hw);
1006 * Issue global reset to the MAC. Needs to be SW reset if link is up.
1007 * If link reset is used when link is up, it might reset the PHY when
1008 * mng is using it. If link is down or the flag to force full link
1009 * reset is set, then perform link reset.
1011 ctrl = IXGBE_CTRL_LNK_RST;
1012 if (!hw->force_full_reset) {
1013 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1015 ctrl = IXGBE_CTRL_RST;
1018 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1019 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1020 IXGBE_WRITE_FLUSH(hw);
1022 /* Poll for reset bit to self-clear indicating reset is complete */
1023 for (i = 0; i < 10; i++) {
1025 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1026 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1030 if (ctrl & IXGBE_CTRL_RST_MASK) {
1031 status = IXGBE_ERR_RESET_FAILED;
1032 hw_dbg(hw, "Reset polling failed to complete.\n");
1038 * Double resets are required for recovery from certain error
1039 * conditions. Between resets, it is necessary to stall to allow time
1040 * for any pending HW events to complete.
1042 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1043 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1048 * Store the original AUTOC/AUTOC2 values if they have not been
1049 * stored off yet. Otherwise restore the stored original
1050 * values since the reset operation sets back to defaults.
1052 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1053 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1054 if (hw->mac.orig_link_settings_stored == false) {
1055 hw->mac.orig_autoc = autoc;
1056 hw->mac.orig_autoc2 = autoc2;
1057 hw->mac.orig_link_settings_stored = true;
1059 if (autoc != hw->mac.orig_autoc)
1060 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
1061 IXGBE_AUTOC_AN_RESTART));
1063 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1064 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1065 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1066 autoc2 |= (hw->mac.orig_autoc2 &
1067 IXGBE_AUTOC2_UPPER_MASK);
1068 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1073 /* Store the permanent mac address */
1074 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1077 * Store MAC address from RAR0, clear receive address registers, and
1078 * clear the multicast table. Also reset num_rar_entries to 128,
1079 * since we modify this value when programming the SAN MAC address.
1081 hw->mac.num_rar_entries = 128;
1082 hw->mac.ops.init_rx_addrs(hw);
1084 /* Store the permanent SAN mac address */
1085 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1087 /* Add the SAN MAC address to the RAR only if it's a valid address */
1088 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1089 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1090 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1092 /* Save the SAN MAC RAR index */
1093 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1095 /* Reserve the last RAR for the SAN MAC address */
1096 hw->mac.num_rar_entries--;
1099 /* Store the alternative WWNN/WWPN prefix */
1100 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1101 &hw->mac.wwpn_prefix);
1108 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1109 * @hw: pointer to hardware structure
1111 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1114 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1115 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1118 * Before starting reinitialization process,
1119 * FDIRCMD.CMD must be zero.
1121 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1122 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1123 IXGBE_FDIRCMD_CMD_MASK))
1127 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1128 hw_dbg(hw, "Flow Director previous command isn't complete, "
1129 "aborting table re-initialization.\n");
1130 return IXGBE_ERR_FDIR_REINIT_FAILED;
1133 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1134 IXGBE_WRITE_FLUSH(hw);
1136 * 82599 adapters flow director init flow cannot be restarted,
1137 * Workaround 82599 silicon errata by performing the following steps
1138 * before re-writing the FDIRCTRL control register with the same value.
1139 * - write 1 to bit 8 of FDIRCMD register &
1140 * - write 0 to bit 8 of FDIRCMD register
1142 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1143 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1144 IXGBE_FDIRCMD_CLEARHT));
1145 IXGBE_WRITE_FLUSH(hw);
1146 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1147 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1148 ~IXGBE_FDIRCMD_CLEARHT));
1149 IXGBE_WRITE_FLUSH(hw);
1151 * Clear FDIR Hash register to clear any leftover hashes
1152 * waiting to be programmed.
1154 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1155 IXGBE_WRITE_FLUSH(hw);
1157 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1158 IXGBE_WRITE_FLUSH(hw);
1160 /* Poll init-done after we write FDIRCTRL register */
1161 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1162 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1163 IXGBE_FDIRCTRL_INIT_DONE)
1167 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1168 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1169 return IXGBE_ERR_FDIR_REINIT_FAILED;
1172 /* Clear FDIR statistics registers (read to clear) */
1173 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1174 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1175 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1176 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1177 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1183 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1184 * @hw: pointer to hardware structure
1185 * @fdirctrl: value to write to flow director control register
1187 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1191 /* Prime the keys for hashing */
1192 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1193 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1196 * Poll init-done after we write the register. Estimated times:
1197 * 10G: PBALLOC = 11b, timing is 60us
1198 * 1G: PBALLOC = 11b, timing is 600us
1199 * 100M: PBALLOC = 11b, timing is 6ms
1201 * Multiple these timings by 4 if under full Rx load
1203 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1204 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1205 * this might not finish in our poll time, but we can live with that
1208 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1209 IXGBE_WRITE_FLUSH(hw);
1210 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1211 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1212 IXGBE_FDIRCTRL_INIT_DONE)
1217 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1218 hw_dbg(hw, "Flow Director poll time exceeded!\n");
1222 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1223 * @hw: pointer to hardware structure
1224 * @fdirctrl: value to write to flow director control register, initially
1225 * contains just the value of the Rx packet buffer allocation
1227 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1230 * Continue setup of fdirctrl register bits:
1231 * Move the flexible bytes to use the ethertype - shift 6 words
1232 * Set the maximum length per hash bucket to 0xA filters
1233 * Send interrupt when 64 filters are left
1235 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1236 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1237 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1239 /* write hashes and fdirctrl register, poll for completion */
1240 ixgbe_fdir_enable_82599(hw, fdirctrl);
1246 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1247 * @hw: pointer to hardware structure
1248 * @fdirctrl: value to write to flow director control register, initially
1249 * contains just the value of the Rx packet buffer allocation
1251 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1254 * Continue setup of fdirctrl register bits:
1255 * Turn perfect match filtering on
1256 * Report hash in RSS field of Rx wb descriptor
1257 * Initialize the drop queue
1258 * Move the flexible bytes to use the ethertype - shift 6 words
1259 * Set the maximum length per hash bucket to 0xA filters
1260 * Send interrupt when 64 (0x4 * 16) filters are left
1262 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1263 IXGBE_FDIRCTRL_REPORT_STATUS |
1264 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1265 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1266 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1267 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1269 /* write hashes and fdirctrl register, poll for completion */
1270 ixgbe_fdir_enable_82599(hw, fdirctrl);
1276 * These defines allow us to quickly generate all of the necessary instructions
1277 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1278 * for values 0 through 15
1280 #define IXGBE_ATR_COMMON_HASH_KEY \
1281 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1282 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1285 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1286 common_hash ^= lo_hash_dword >> n; \
1287 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1288 bucket_hash ^= lo_hash_dword >> n; \
1289 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1290 sig_hash ^= lo_hash_dword << (16 - n); \
1291 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1292 common_hash ^= hi_hash_dword >> n; \
1293 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1294 bucket_hash ^= hi_hash_dword >> n; \
1295 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1296 sig_hash ^= hi_hash_dword << (16 - n); \
1300 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1301 * @stream: input bitstream to compute the hash on
1303 * This function is almost identical to the function above but contains
1304 * several optomizations such as unwinding all of the loops, letting the
1305 * compiler work out all of the conditional ifs since the keys are static
1306 * defines, and computing two keys at once since the hashed dword stream
1307 * will be the same for both keys.
1309 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1310 union ixgbe_atr_hash_dword common)
1312 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1313 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1315 /* record the flow_vm_vlan bits as they are a key part to the hash */
1316 flow_vm_vlan = IXGBE_NTOHL(input.dword);
1318 /* generate common hash dword */
1319 hi_hash_dword = IXGBE_NTOHL(common.dword);
1321 /* low dword is word swapped version of common */
1322 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1324 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1325 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1327 /* Process bits 0 and 16 */
1328 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1331 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1332 * delay this because bit 0 of the stream should not be processed
1333 * so we do not add the vlan until after bit 0 was processed
1335 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1337 /* Process remaining 30 bit of the key */
1338 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1339 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1340 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1341 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1342 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1343 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1344 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1345 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1346 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1347 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1348 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1349 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1350 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1351 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1352 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1354 /* combine common_hash result with signature and bucket hashes */
1355 bucket_hash ^= common_hash;
1356 bucket_hash &= IXGBE_ATR_HASH_MASK;
1358 sig_hash ^= common_hash << 16;
1359 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1361 /* return completed signature hash */
1362 return sig_hash ^ bucket_hash;
1366 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1367 * @hw: pointer to hardware structure
1368 * @input: unique input dword
1369 * @common: compressed common input dword
1370 * @queue: queue index to direct traffic to
1372 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1373 union ixgbe_atr_hash_dword input,
1374 union ixgbe_atr_hash_dword common,
1381 * Get the flow_type in order to program FDIRCMD properly
1382 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1384 switch (input.formatted.flow_type) {
1385 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1386 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1387 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1388 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1389 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1390 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1393 hw_dbg(hw, " Error on flow type input\n");
1394 return IXGBE_ERR_CONFIG;
1397 /* configure FDIRCMD register */
1398 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1399 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1400 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1401 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1404 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1405 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1407 fdirhashcmd = (u64)fdircmd << 32;
1408 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1409 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1411 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1416 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1419 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1420 bucket_hash ^= lo_hash_dword >> n; \
1421 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1422 bucket_hash ^= hi_hash_dword >> n; \
1426 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1427 * @atr_input: input bitstream to compute the hash on
1428 * @input_mask: mask for the input bitstream
1430 * This function serves two main purposes. First it applys the input_mask
1431 * to the atr_input resulting in a cleaned up atr_input data stream.
1432 * Secondly it computes the hash and stores it in the bkt_hash field at
1433 * the end of the input byte stream. This way it will be available for
1434 * future use without needing to recompute the hash.
1436 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1437 union ixgbe_atr_input *input_mask)
1440 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1441 u32 bucket_hash = 0;
1443 /* Apply masks to input data */
1444 input->dword_stream[0] &= input_mask->dword_stream[0];
1445 input->dword_stream[1] &= input_mask->dword_stream[1];
1446 input->dword_stream[2] &= input_mask->dword_stream[2];
1447 input->dword_stream[3] &= input_mask->dword_stream[3];
1448 input->dword_stream[4] &= input_mask->dword_stream[4];
1449 input->dword_stream[5] &= input_mask->dword_stream[5];
1450 input->dword_stream[6] &= input_mask->dword_stream[6];
1451 input->dword_stream[7] &= input_mask->dword_stream[7];
1452 input->dword_stream[8] &= input_mask->dword_stream[8];
1453 input->dword_stream[9] &= input_mask->dword_stream[9];
1454 input->dword_stream[10] &= input_mask->dword_stream[10];
1456 /* record the flow_vm_vlan bits as they are a key part to the hash */
1457 flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
1459 /* generate common hash dword */
1460 hi_hash_dword = IXGBE_NTOHL(input->dword_stream[1] ^
1461 input->dword_stream[2] ^
1462 input->dword_stream[3] ^
1463 input->dword_stream[4] ^
1464 input->dword_stream[5] ^
1465 input->dword_stream[6] ^
1466 input->dword_stream[7] ^
1467 input->dword_stream[8] ^
1468 input->dword_stream[9] ^
1469 input->dword_stream[10]);
1471 /* low dword is word swapped version of common */
1472 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1474 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1475 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1477 /* Process bits 0 and 16 */
1478 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1481 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1482 * delay this because bit 0 of the stream should not be processed
1483 * so we do not add the vlan until after bit 0 was processed
1485 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1487 /* Process remaining 30 bit of the key */
1488 IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
1489 IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
1490 IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
1491 IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
1492 IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
1493 IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
1494 IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
1495 IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
1496 IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
1497 IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
1498 IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
1499 IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
1500 IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
1501 IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
1502 IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
1505 * Limit hash to 13 bits since max bucket count is 8K.
1506 * Store result at the end of the input stream.
1508 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1512 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1513 * @input_mask: mask to be bit swapped
1515 * The source and destination port masks for flow director are bit swapped
1516 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1517 * generate a correctly swapped value we need to bit swap the mask and that
1518 * is what is accomplished by this function.
1520 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1522 u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);
1523 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1524 mask |= IXGBE_NTOHS(input_mask->formatted.src_port);
1525 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1526 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1527 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1528 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1532 * These two macros are meant to address the fact that we have registers
1533 * that are either all or in part big-endian. As a result on big-endian
1534 * systems we will end up byte swapping the value to little-endian before
1535 * it is byte swapped again and written to the hardware in the original
1536 * big-endian format.
1538 #define IXGBE_STORE_AS_BE32(_value) \
1539 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1540 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1542 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1543 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))
1545 #define IXGBE_STORE_AS_BE16(_value) \
1546 IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1548 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1549 union ixgbe_atr_input *input_mask)
1551 /* mask IPv6 since it is currently not supported */
1552 u32 fdirm = IXGBE_FDIRM_DIPv6;
1556 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1557 * are zero, then assume a full mask for that field. Also assume that
1558 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1559 * cannot be masked out in this implementation.
1561 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1565 /* verify bucket hash is cleared on hash generation */
1566 if (input_mask->formatted.bkt_hash)
1567 hw_dbg(hw, " bucket hash should always be 0 in mask\n");
1569 /* Program FDIRM and verify partial masks */
1570 switch (input_mask->formatted.vm_pool & 0x7F) {
1572 fdirm |= IXGBE_FDIRM_POOL;
1576 hw_dbg(hw, " Error on vm pool mask\n");
1577 return IXGBE_ERR_CONFIG;
1580 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1582 fdirm |= IXGBE_FDIRM_L4P;
1583 if (input_mask->formatted.dst_port ||
1584 input_mask->formatted.src_port) {
1585 hw_dbg(hw, " Error on src/dst port mask\n");
1586 return IXGBE_ERR_CONFIG;
1588 case IXGBE_ATR_L4TYPE_MASK:
1591 hw_dbg(hw, " Error on flow type mask\n");
1592 return IXGBE_ERR_CONFIG;
1595 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {
1597 /* mask VLAN ID, fall through to mask VLAN priority */
1598 fdirm |= IXGBE_FDIRM_VLANID;
1600 /* mask VLAN priority */
1601 fdirm |= IXGBE_FDIRM_VLANP;
1604 /* mask VLAN ID only, fall through */
1605 fdirm |= IXGBE_FDIRM_VLANID;
1607 /* no VLAN fields masked */
1610 hw_dbg(hw, " Error on VLAN mask\n");
1611 return IXGBE_ERR_CONFIG;
1614 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1616 /* Mask Flex Bytes, fall through */
1617 fdirm |= IXGBE_FDIRM_FLEX;
1621 hw_dbg(hw, " Error on flexible byte mask\n");
1622 return IXGBE_ERR_CONFIG;
1625 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1626 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1628 /* store the TCP/UDP port masks, bit reversed from port layout */
1629 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1631 /* write both the same so that UDP and TCP use the same mask */
1632 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1633 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1635 /* store source and destination IP masks (big-enian) */
1636 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1637 ~input_mask->formatted.src_ip[0]);
1638 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1639 ~input_mask->formatted.dst_ip[0]);
1644 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1645 union ixgbe_atr_input *input,
1646 u16 soft_id, u8 queue)
1648 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1650 /* currently IPv6 is not supported, must be programmed with 0 */
1651 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1652 input->formatted.src_ip[0]);
1653 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1654 input->formatted.src_ip[1]);
1655 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1656 input->formatted.src_ip[2]);
1658 /* record the source address (big-endian) */
1659 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1661 /* record the first 32 bits of the destination address (big-endian) */
1662 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1664 /* record source and destination port (little-endian)*/
1665 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
1666 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1667 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
1668 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1670 /* record vlan (little-endian) and flex_bytes(big-endian) */
1671 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1672 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1673 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
1674 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1676 /* configure FDIRHASH register */
1677 fdirhash = input->formatted.bkt_hash;
1678 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1679 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1682 * flush all previous writes to make certain registers are
1683 * programmed prior to issuing the command
1685 IXGBE_WRITE_FLUSH(hw);
1687 /* configure FDIRCMD register */
1688 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1689 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1690 if (queue == IXGBE_FDIR_DROP_QUEUE)
1691 fdircmd |= IXGBE_FDIRCMD_DROP;
1692 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1693 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1694 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1696 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1701 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1702 union ixgbe_atr_input *input,
1710 /* configure FDIRHASH register */
1711 fdirhash = input->formatted.bkt_hash;
1712 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1713 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1715 /* flush hash to HW */
1716 IXGBE_WRITE_FLUSH(hw);
1718 /* Query if filter is present */
1719 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1721 for (retry_count = 10; retry_count; retry_count--) {
1722 /* allow 10us for query to process */
1724 /* verify query completed successfully */
1725 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1726 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1731 err = IXGBE_ERR_FDIR_REINIT_FAILED;
1733 /* if filter exists in hardware then remove it */
1734 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1735 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1736 IXGBE_WRITE_FLUSH(hw);
1737 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1738 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1745 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1746 * @hw: pointer to hardware structure
1747 * @input: input bitstream
1748 * @input_mask: mask for the input bitstream
1749 * @soft_id: software index for the filters
1750 * @queue: queue index to direct traffic to
1752 * Note that the caller to this function must lock before calling, since the
1753 * hardware writes must be protected from one another.
1755 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1756 union ixgbe_atr_input *input,
1757 union ixgbe_atr_input *input_mask,
1758 u16 soft_id, u8 queue)
1760 s32 err = IXGBE_ERR_CONFIG;
1763 * Check flow_type formatting, and bail out before we touch the hardware
1764 * if there's a configuration issue
1766 switch (input->formatted.flow_type) {
1767 case IXGBE_ATR_FLOW_TYPE_IPV4:
1768 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
1769 if (input->formatted.dst_port || input->formatted.src_port) {
1770 hw_dbg(hw, " Error on src/dst port\n");
1771 return IXGBE_ERR_CONFIG;
1774 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1775 if (input->formatted.dst_port || input->formatted.src_port) {
1776 hw_dbg(hw, " Error on src/dst port\n");
1777 return IXGBE_ERR_CONFIG;
1779 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1780 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1781 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
1782 IXGBE_ATR_L4TYPE_MASK;
1785 hw_dbg(hw, " Error on flow type input\n");
1789 /* program input mask into the HW */
1790 err = ixgbe_fdir_set_input_mask_82599(hw, input_mask);
1794 /* apply mask and compute/store hash */
1795 ixgbe_atr_compute_perfect_hash_82599(input, input_mask);
1797 /* program filters to filter memory */
1798 return ixgbe_fdir_write_perfect_filter_82599(hw, input,
1803 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1804 * @hw: pointer to hardware structure
1805 * @reg: analog register to read
1808 * Performs read operation to Omer analog register specified.
1810 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1814 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1816 IXGBE_WRITE_FLUSH(hw);
1818 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1819 *val = (u8)core_ctl;
1825 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1826 * @hw: pointer to hardware structure
1827 * @reg: atlas register to write
1828 * @val: value to write
1830 * Performs write operation to Omer analog register specified.
1832 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1836 core_ctl = (reg << 8) | val;
1837 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1838 IXGBE_WRITE_FLUSH(hw);
1845 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1846 * @hw: pointer to hardware structure
1848 * Starts the hardware using the generic start_hw function
1849 * and the generation start_hw function.
1850 * Then performs revision-specific operations, if any.
1852 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1856 ret_val = ixgbe_start_hw_generic(hw);
1860 ret_val = ixgbe_start_hw_gen2(hw);
1864 /* We need to run link autotry after the driver loads */
1865 hw->mac.autotry_restart = true;
1868 ret_val = ixgbe_verify_fw_version_82599(hw);
1874 * ixgbe_identify_phy_82599 - Get physical layer module
1875 * @hw: pointer to hardware structure
1877 * Determines the physical layer module found on the current adapter.
1878 * If PHY already detected, maintains current PHY type in hw struct,
1879 * otherwise executes the PHY detection routine.
1881 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1883 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1885 /* Detect PHY if not unknown - returns success if already detected. */
1886 status = ixgbe_identify_phy_generic(hw);
1888 /* 82599 10GBASE-T requires an external PHY */
1889 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
1892 status = ixgbe_identify_module_generic(hw);
1895 /* Set PHY type none if no PHY detected */
1896 if (hw->phy.type == ixgbe_phy_unknown) {
1897 hw->phy.type = ixgbe_phy_none;
1901 /* Return error if SFP module has been detected but is not supported */
1902 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1903 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1910 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1911 * @hw: pointer to hardware structure
1913 * Determines physical layer capabilities of the current configuration.
1915 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1917 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1918 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1919 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1920 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1921 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1922 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1923 u16 ext_ability = 0;
1924 u8 comp_codes_10g = 0;
1925 u8 comp_codes_1g = 0;
1927 hw->phy.ops.identify(hw);
1929 switch (hw->phy.type) {
1931 case ixgbe_phy_cu_unknown:
1932 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
1933 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
1934 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
1935 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1936 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
1937 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1938 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
1939 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1945 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1946 case IXGBE_AUTOC_LMS_1G_AN:
1947 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1948 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1949 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1950 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1953 /* SFI mode so read SFP module */
1956 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1957 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1958 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1959 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1960 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1961 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
1962 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
1965 case IXGBE_AUTOC_LMS_10G_SERIAL:
1966 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1967 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1969 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1972 case IXGBE_AUTOC_LMS_KX4_KX_KR:
1973 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1974 if (autoc & IXGBE_AUTOC_KX_SUPP)
1975 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1976 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1977 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1978 if (autoc & IXGBE_AUTOC_KR_SUPP)
1979 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1988 /* SFP check must be done last since DA modules are sometimes used to
1989 * test KR mode - we need to id KR mode correctly before SFP module.
1990 * Call identify_sfp because the pluggable module may have changed */
1991 hw->phy.ops.identify_sfp(hw);
1992 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1995 switch (hw->phy.type) {
1996 case ixgbe_phy_sfp_passive_tyco:
1997 case ixgbe_phy_sfp_passive_unknown:
1998 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2000 case ixgbe_phy_sfp_ftl_active:
2001 case ixgbe_phy_sfp_active_unknown:
2002 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
2004 case ixgbe_phy_sfp_avago:
2005 case ixgbe_phy_sfp_ftl:
2006 case ixgbe_phy_sfp_intel:
2007 case ixgbe_phy_sfp_unknown:
2008 hw->phy.ops.read_i2c_eeprom(hw,
2009 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
2010 hw->phy.ops.read_i2c_eeprom(hw,
2011 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2012 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2013 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2014 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2015 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2016 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
2017 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
2018 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
2019 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
2026 return physical_layer;
2030 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2031 * @hw: pointer to hardware structure
2032 * @regval: register value to write to RXCTRL
2034 * Enables the Rx DMA unit for 82599
2036 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2040 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2041 * If traffic is incoming before we enable the Rx unit, it could hang
2042 * the Rx DMA unit. Therefore, make sure the security engine is
2043 * completely disabled prior to enabling the Rx unit.
2046 hw->mac.ops.disable_sec_rx_path(hw);
2048 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2050 hw->mac.ops.enable_sec_rx_path(hw);
2056 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2057 * @hw: pointer to hardware structure
2059 * Verifies that installed the firmware version is 0.6 or higher
2060 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2062 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2063 * if the FW version is not supported.
2065 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2067 s32 status = IXGBE_ERR_EEPROM_VERSION;
2068 u16 fw_offset, fw_ptp_cfg_offset;
2071 /* firmware check is only necessary for SFI devices */
2072 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2074 goto fw_version_out;
2077 /* get the offset to the Firmware Module block */
2078 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2080 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2081 goto fw_version_out;
2083 /* get the offset to the Pass Through Patch Configuration block */
2084 hw->eeprom.ops.read(hw, (fw_offset +
2085 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2086 &fw_ptp_cfg_offset);
2088 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2089 goto fw_version_out;
2091 /* get the firmware version */
2092 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2093 IXGBE_FW_PATCH_VERSION_4), &fw_version);
2095 if (fw_version > 0x5)
2103 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2104 * @hw: pointer to hardware structure
2106 * Returns true if the LESM FW module is present and enabled. Otherwise
2107 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2109 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2111 bool lesm_enabled = false;
2112 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2115 /* get the offset to the Firmware Module block */
2116 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2118 if ((status != 0) ||
2119 (fw_offset == 0) || (fw_offset == 0xFFFF))
2122 /* get the offset to the LESM Parameters block */
2123 status = hw->eeprom.ops.read(hw, (fw_offset +
2124 IXGBE_FW_LESM_PARAMETERS_PTR),
2125 &fw_lesm_param_offset);
2127 if ((status != 0) ||
2128 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2131 /* get the lesm state word */
2132 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2133 IXGBE_FW_LESM_STATE_1),
2136 if ((status == 0) &&
2137 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2138 lesm_enabled = true;
2141 return lesm_enabled;
2145 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2146 * fastest available method
2148 * @hw: pointer to hardware structure
2149 * @offset: offset of word in EEPROM to read
2150 * @words: number of words
2151 * @data: word(s) read from the EEPROM
2153 * Retrieves 16 bit word(s) read from EEPROM
2155 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2156 u16 words, u16 *data)
2158 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2159 s32 ret_val = IXGBE_ERR_CONFIG;
2162 * If EEPROM is detected and can be addressed using 14 bits,
2163 * use EERD otherwise use bit bang
2165 if ((eeprom->type == ixgbe_eeprom_spi) &&
2166 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2167 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2170 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2178 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2179 * fastest available method
2181 * @hw: pointer to hardware structure
2182 * @offset: offset of word in the EEPROM to read
2183 * @data: word read from the EEPROM
2185 * Reads a 16 bit word from the EEPROM
2187 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2188 u16 offset, u16 *data)
2190 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2191 s32 ret_val = IXGBE_ERR_CONFIG;
2194 * If EEPROM is detected and can be addressed using 14 bits,
2195 * use EERD otherwise use bit bang
2197 if ((eeprom->type == ixgbe_eeprom_spi) &&
2198 (offset <= IXGBE_EERD_MAX_ADDR))
2199 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2201 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2207 * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C
2208 * @hw: pointer to hardware structure
2209 * @byte_offset: byte offset to read
2212 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2213 * a specified device address.
2215 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2216 u8 dev_addr, u8 *data)
2222 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2223 /* Acquire I2C bus ownership. */
2224 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2225 esdp |= IXGBE_ESDP_SDP0;
2226 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2227 IXGBE_WRITE_FLUSH(hw);
2230 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2231 if (esdp & IXGBE_ESDP_SDP1)
2239 hw_dbg(hw, "Driver can't access resource,"
2240 " acquiring I2C bus timeout.\n");
2241 status = IXGBE_ERR_I2C;
2242 goto release_i2c_access;
2246 status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2250 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2251 /* Release I2C bus ownership. */
2252 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2253 esdp &= ~IXGBE_ESDP_SDP0;
2254 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2255 IXGBE_WRITE_FLUSH(hw);
2262 * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C
2263 * @hw: pointer to hardware structure
2264 * @byte_offset: byte offset to write
2265 * @data: value to write
2267 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2268 * a specified device address.
2270 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2271 u8 dev_addr, u8 data)
2277 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2278 /* Acquire I2C bus ownership. */
2279 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2280 esdp |= IXGBE_ESDP_SDP0;
2281 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2282 IXGBE_WRITE_FLUSH(hw);
2285 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2286 if (esdp & IXGBE_ESDP_SDP1)
2294 hw_dbg(hw, "Driver can't access resource,"
2295 " acquiring I2C bus timeout.\n");
2296 status = IXGBE_ERR_I2C;
2297 goto release_i2c_access;
2301 status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2305 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2306 /* Release I2C bus ownership. */
2307 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2308 esdp &= ~IXGBE_ESDP_SDP0;
2309 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2310 IXGBE_WRITE_FLUSH(hw);