1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include "ixgbe_common.h"
29 #include "ixgbe_phy.h"
30 #include "ixgbe_api.h"
32 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
33 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
34 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
35 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
36 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
37 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
39 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
40 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
41 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
42 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
44 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
45 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
47 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
48 u16 words, u16 *data);
49 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
50 u16 words, u16 *data);
51 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
55 * ixgbe_init_ops_generic - Inits function ptrs
56 * @hw: pointer to the hardware structure
58 * Initialize the function pointers.
60 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
62 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
63 struct ixgbe_mac_info *mac = &hw->mac;
64 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
67 eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic;
68 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
69 if (eec & IXGBE_EEC_PRES) {
70 eeprom->ops.read = &ixgbe_read_eerd_generic;
71 eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_generic;
73 eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic;
74 eeprom->ops.read_buffer =
75 &ixgbe_read_eeprom_buffer_bit_bang_generic;
77 eeprom->ops.write = &ixgbe_write_eeprom_generic;
78 eeprom->ops.write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic;
79 eeprom->ops.validate_checksum =
80 &ixgbe_validate_eeprom_checksum_generic;
81 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic;
82 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_generic;
85 mac->ops.init_hw = &ixgbe_init_hw_generic;
86 mac->ops.reset_hw = NULL;
87 mac->ops.start_hw = &ixgbe_start_hw_generic;
88 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic;
89 mac->ops.get_media_type = NULL;
90 mac->ops.get_supported_physical_layer = NULL;
91 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic;
92 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic;
93 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic;
94 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic;
95 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie;
96 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync;
97 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync;
100 mac->ops.led_on = &ixgbe_led_on_generic;
101 mac->ops.led_off = &ixgbe_led_off_generic;
102 mac->ops.blink_led_start = &ixgbe_blink_led_start_generic;
103 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic;
105 /* RAR, Multicast, VLAN */
106 mac->ops.set_rar = &ixgbe_set_rar_generic;
107 mac->ops.clear_rar = &ixgbe_clear_rar_generic;
108 mac->ops.insert_mac_addr = NULL;
109 mac->ops.set_vmdq = NULL;
110 mac->ops.clear_vmdq = NULL;
111 mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic;
112 mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic;
113 mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic;
114 mac->ops.enable_mc = &ixgbe_enable_mc_generic;
115 mac->ops.disable_mc = &ixgbe_disable_mc_generic;
116 mac->ops.clear_vfta = NULL;
117 mac->ops.set_vfta = NULL;
118 mac->ops.set_vlvf = NULL;
119 mac->ops.init_uta_tables = NULL;
122 mac->ops.fc_enable = &ixgbe_fc_enable_generic;
125 mac->ops.get_link_capabilities = NULL;
126 mac->ops.setup_link = NULL;
127 mac->ops.check_link = NULL;
133 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
135 * @hw: pointer to hardware structure
137 * There are several phys that do not support autoneg flow control. This
138 * function check the device id to see if the associated phy supports
139 * autoneg flow control.
141 static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
144 switch (hw->device_id) {
145 case IXGBE_DEV_ID_X540T:
147 case IXGBE_DEV_ID_82599_T3_LOM:
150 return IXGBE_ERR_FC_NOT_SUPPORTED;
155 * ixgbe_setup_fc - Set up flow control
156 * @hw: pointer to hardware structure
158 * Called at init time to set up flow control.
160 static s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
163 u32 reg = 0, reg_bp = 0;
167 * Validate the requested mode. Strict IEEE mode does not allow
168 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
170 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
171 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
172 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
177 * 10gig parts do not have a word in the EEPROM to determine the
178 * default flow control setting, so we explicitly set it to full.
180 if (hw->fc.requested_mode == ixgbe_fc_default)
181 hw->fc.requested_mode = ixgbe_fc_full;
184 * Set up the 1G and 10G flow control advertisement registers so the
185 * HW will be able to do fc autoneg once the cable is plugged in. If
186 * we link at 10G, the 1G advertisement is harmless and vice versa.
188 switch (hw->phy.media_type) {
189 case ixgbe_media_type_fiber:
190 case ixgbe_media_type_backplane:
191 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
192 reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
194 case ixgbe_media_type_copper:
195 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
196 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
203 * The possible values of fc.requested_mode are:
204 * 0: Flow control is completely disabled
205 * 1: Rx flow control is enabled (we can receive pause frames,
206 * but not send pause frames).
207 * 2: Tx flow control is enabled (we can send pause frames but
208 * we do not support receiving pause frames).
209 * 3: Both Rx and Tx flow control (symmetric) are enabled.
212 switch (hw->fc.requested_mode) {
214 /* Flow control completely disabled by software override. */
215 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
216 if (hw->phy.media_type == ixgbe_media_type_backplane)
217 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
218 IXGBE_AUTOC_ASM_PAUSE);
219 else if (hw->phy.media_type == ixgbe_media_type_copper)
220 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
222 case ixgbe_fc_tx_pause:
224 * Tx Flow control is enabled, and Rx Flow control is
225 * disabled by software override.
227 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
228 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
229 if (hw->phy.media_type == ixgbe_media_type_backplane) {
230 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
231 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
232 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
233 reg_cu |= IXGBE_TAF_ASM_PAUSE;
234 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
237 case ixgbe_fc_rx_pause:
239 * Rx Flow control is enabled and Tx Flow control is
240 * disabled by software override. Since there really
241 * isn't a way to advertise that we are capable of RX
242 * Pause ONLY, we will advertise that we support both
243 * symmetric and asymmetric Rx PAUSE, as such we fall
244 * through to the fc_full statement. Later, we will
245 * disable the adapter's ability to send PAUSE frames.
248 /* Flow control (both Rx and Tx) is enabled by SW override. */
249 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
250 if (hw->phy.media_type == ixgbe_media_type_backplane)
251 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
252 IXGBE_AUTOC_ASM_PAUSE;
253 else if (hw->phy.media_type == ixgbe_media_type_copper)
254 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
257 hw_dbg(hw, "Flow control param set incorrectly\n");
258 ret_val = IXGBE_ERR_CONFIG;
263 if (hw->mac.type != ixgbe_mac_X540) {
265 * Enable auto-negotiation between the MAC & PHY;
266 * the MAC will advertise clause 37 flow control.
268 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
269 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
271 /* Disable AN timeout */
272 if (hw->fc.strict_ieee)
273 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
275 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
276 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
280 * AUTOC restart handles negotiation of 1G and 10G on backplane
281 * and copper. There is no need to set the PCS1GCTL register.
284 if (hw->phy.media_type == ixgbe_media_type_backplane) {
285 reg_bp |= IXGBE_AUTOC_AN_RESTART;
286 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
287 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
288 (ixgbe_device_supports_autoneg_fc(hw) == 0)) {
289 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
290 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
293 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
299 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
300 * @hw: pointer to hardware structure
302 * Starts the hardware by filling the bus info structure and media type, clears
303 * all on chip counters, initializes receive address registers, multicast
304 * table, VLAN filter table, calls routine to set up link and flow control
305 * settings, and leaves transmit and receive units disabled and uninitialized
307 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
312 /* Set the media type */
313 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
315 /* PHY ops initialization must be done in reset_hw() */
317 /* Clear the VLAN filter table */
318 hw->mac.ops.clear_vfta(hw);
320 /* Clear statistics registers */
321 hw->mac.ops.clear_hw_cntrs(hw);
323 /* Set No Snoop Disable */
324 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
325 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
326 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
327 IXGBE_WRITE_FLUSH(hw);
329 /* Setup flow control */
330 ret_val = ixgbe_setup_fc(hw);
334 /* Clear adapter stopped flag */
335 hw->adapter_stopped = false;
342 * ixgbe_start_hw_gen2 - Init sequence for common device family
343 * @hw: pointer to hw structure
345 * Performs the init sequence common to the second generation
347 * Devices in the second generation:
351 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
356 /* Clear the rate limiters */
357 for (i = 0; i < hw->mac.max_tx_queues; i++) {
358 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
359 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
361 IXGBE_WRITE_FLUSH(hw);
363 /* Disable relaxed ordering */
364 for (i = 0; i < hw->mac.max_tx_queues; i++) {
365 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
366 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
367 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
370 for (i = 0; i < hw->mac.max_rx_queues; i++) {
371 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
372 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
373 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
374 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
381 * ixgbe_init_hw_generic - Generic hardware initialization
382 * @hw: pointer to hardware structure
384 * Initialize the hardware by resetting the hardware, filling the bus info
385 * structure and media type, clears all on chip counters, initializes receive
386 * address registers, multicast table, VLAN filter table, calls routine to set
387 * up link and flow control settings, and leaves transmit and receive units
388 * disabled and uninitialized
390 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
394 /* Reset the hardware */
395 status = hw->mac.ops.reset_hw(hw);
399 status = hw->mac.ops.start_hw(hw);
406 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
407 * @hw: pointer to hardware structure
409 * Clears all hardware statistics counters by reading them from the hardware
410 * Statistics counters are clear on read.
412 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
416 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
417 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
418 IXGBE_READ_REG(hw, IXGBE_ERRBC);
419 IXGBE_READ_REG(hw, IXGBE_MSPDC);
420 for (i = 0; i < 8; i++)
421 IXGBE_READ_REG(hw, IXGBE_MPC(i));
423 IXGBE_READ_REG(hw, IXGBE_MLFC);
424 IXGBE_READ_REG(hw, IXGBE_MRFC);
425 IXGBE_READ_REG(hw, IXGBE_RLEC);
426 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
427 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
428 if (hw->mac.type >= ixgbe_mac_82599EB) {
429 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
430 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
432 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
433 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
436 for (i = 0; i < 8; i++) {
437 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
438 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
439 if (hw->mac.type >= ixgbe_mac_82599EB) {
440 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
441 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
443 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
444 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
447 if (hw->mac.type >= ixgbe_mac_82599EB)
448 for (i = 0; i < 8; i++)
449 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
450 IXGBE_READ_REG(hw, IXGBE_PRC64);
451 IXGBE_READ_REG(hw, IXGBE_PRC127);
452 IXGBE_READ_REG(hw, IXGBE_PRC255);
453 IXGBE_READ_REG(hw, IXGBE_PRC511);
454 IXGBE_READ_REG(hw, IXGBE_PRC1023);
455 IXGBE_READ_REG(hw, IXGBE_PRC1522);
456 IXGBE_READ_REG(hw, IXGBE_GPRC);
457 IXGBE_READ_REG(hw, IXGBE_BPRC);
458 IXGBE_READ_REG(hw, IXGBE_MPRC);
459 IXGBE_READ_REG(hw, IXGBE_GPTC);
460 IXGBE_READ_REG(hw, IXGBE_GORCL);
461 IXGBE_READ_REG(hw, IXGBE_GORCH);
462 IXGBE_READ_REG(hw, IXGBE_GOTCL);
463 IXGBE_READ_REG(hw, IXGBE_GOTCH);
464 if (hw->mac.type == ixgbe_mac_82598EB)
465 for (i = 0; i < 8; i++)
466 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
467 IXGBE_READ_REG(hw, IXGBE_RUC);
468 IXGBE_READ_REG(hw, IXGBE_RFC);
469 IXGBE_READ_REG(hw, IXGBE_ROC);
470 IXGBE_READ_REG(hw, IXGBE_RJC);
471 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
472 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
473 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
474 IXGBE_READ_REG(hw, IXGBE_TORL);
475 IXGBE_READ_REG(hw, IXGBE_TORH);
476 IXGBE_READ_REG(hw, IXGBE_TPR);
477 IXGBE_READ_REG(hw, IXGBE_TPT);
478 IXGBE_READ_REG(hw, IXGBE_PTC64);
479 IXGBE_READ_REG(hw, IXGBE_PTC127);
480 IXGBE_READ_REG(hw, IXGBE_PTC255);
481 IXGBE_READ_REG(hw, IXGBE_PTC511);
482 IXGBE_READ_REG(hw, IXGBE_PTC1023);
483 IXGBE_READ_REG(hw, IXGBE_PTC1522);
484 IXGBE_READ_REG(hw, IXGBE_MPTC);
485 IXGBE_READ_REG(hw, IXGBE_BPTC);
486 for (i = 0; i < 16; i++) {
487 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
488 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
489 if (hw->mac.type >= ixgbe_mac_82599EB) {
490 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
491 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
492 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
493 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
494 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
496 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
497 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
501 if (hw->mac.type == ixgbe_mac_X540) {
503 ixgbe_identify_phy(hw);
504 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
505 IXGBE_MDIO_PCS_DEV_TYPE, &i);
506 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
507 IXGBE_MDIO_PCS_DEV_TYPE, &i);
508 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
509 IXGBE_MDIO_PCS_DEV_TYPE, &i);
510 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
511 IXGBE_MDIO_PCS_DEV_TYPE, &i);
518 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
519 * @hw: pointer to hardware structure
520 * @pba_num: stores the part number string from the EEPROM
521 * @pba_num_size: part number string buffer length
523 * Reads the part number string from the EEPROM.
525 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
534 if (pba_num == NULL) {
535 hw_dbg(hw, "PBA string buffer was null\n");
536 return IXGBE_ERR_INVALID_ARGUMENT;
539 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
541 hw_dbg(hw, "NVM Read Error\n");
545 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
547 hw_dbg(hw, "NVM Read Error\n");
552 * if data is not ptr guard the PBA must be in legacy format which
553 * means pba_ptr is actually our second data word for the PBA number
554 * and we can decode it into an ascii string
556 if (data != IXGBE_PBANUM_PTR_GUARD) {
557 hw_dbg(hw, "NVM PBA number is not stored as string\n");
559 /* we will need 11 characters to store the PBA */
560 if (pba_num_size < 11) {
561 hw_dbg(hw, "PBA string buffer too small\n");
562 return IXGBE_ERR_NO_SPACE;
565 /* extract hex string from data and pba_ptr */
566 pba_num[0] = (data >> 12) & 0xF;
567 pba_num[1] = (data >> 8) & 0xF;
568 pba_num[2] = (data >> 4) & 0xF;
569 pba_num[3] = data & 0xF;
570 pba_num[4] = (pba_ptr >> 12) & 0xF;
571 pba_num[5] = (pba_ptr >> 8) & 0xF;
574 pba_num[8] = (pba_ptr >> 4) & 0xF;
575 pba_num[9] = pba_ptr & 0xF;
577 /* put a null character on the end of our string */
580 /* switch all the data but the '-' to hex char */
581 for (offset = 0; offset < 10; offset++) {
582 if (pba_num[offset] < 0xA)
583 pba_num[offset] += '0';
584 else if (pba_num[offset] < 0x10)
585 pba_num[offset] += 'A' - 0xA;
591 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
593 hw_dbg(hw, "NVM Read Error\n");
597 if (length == 0xFFFF || length == 0) {
598 hw_dbg(hw, "NVM PBA number section invalid length\n");
599 return IXGBE_ERR_PBA_SECTION;
602 /* check if pba_num buffer is big enough */
603 if (pba_num_size < (((u32)length * 2) - 1)) {
604 hw_dbg(hw, "PBA string buffer too small\n");
605 return IXGBE_ERR_NO_SPACE;
608 /* trim pba length from start of string */
612 for (offset = 0; offset < length; offset++) {
613 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
615 hw_dbg(hw, "NVM Read Error\n");
618 pba_num[offset * 2] = (u8)(data >> 8);
619 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
621 pba_num[offset * 2] = '\0';
627 * ixgbe_get_mac_addr_generic - Generic get MAC address
628 * @hw: pointer to hardware structure
629 * @mac_addr: Adapter MAC address
631 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
632 * A reset of the adapter must be performed prior to calling this function
633 * in order for the MAC address to have been loaded from the EEPROM into RAR0
635 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
641 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
642 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
644 for (i = 0; i < 4; i++)
645 mac_addr[i] = (u8)(rar_low >> (i*8));
647 for (i = 0; i < 2; i++)
648 mac_addr[i+4] = (u8)(rar_high >> (i*8));
654 * ixgbe_get_bus_info_generic - Generic set PCI bus info
655 * @hw: pointer to hardware structure
657 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
659 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
661 struct ixgbe_mac_info *mac = &hw->mac;
664 hw->bus.type = ixgbe_bus_type_pci_express;
666 /* Get the negotiated link width and speed from PCI config space */
667 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
669 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
670 case IXGBE_PCI_LINK_WIDTH_1:
671 hw->bus.width = ixgbe_bus_width_pcie_x1;
673 case IXGBE_PCI_LINK_WIDTH_2:
674 hw->bus.width = ixgbe_bus_width_pcie_x2;
676 case IXGBE_PCI_LINK_WIDTH_4:
677 hw->bus.width = ixgbe_bus_width_pcie_x4;
679 case IXGBE_PCI_LINK_WIDTH_8:
680 hw->bus.width = ixgbe_bus_width_pcie_x8;
683 hw->bus.width = ixgbe_bus_width_unknown;
687 switch (link_status & IXGBE_PCI_LINK_SPEED) {
688 case IXGBE_PCI_LINK_SPEED_2500:
689 hw->bus.speed = ixgbe_bus_speed_2500;
691 case IXGBE_PCI_LINK_SPEED_5000:
692 hw->bus.speed = ixgbe_bus_speed_5000;
694 case IXGBE_PCI_LINK_SPEED_8000:
695 hw->bus.speed = ixgbe_bus_speed_8000;
698 hw->bus.speed = ixgbe_bus_speed_unknown;
702 mac->ops.set_lan_id(hw);
708 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
709 * @hw: pointer to the HW structure
711 * Determines the LAN function id by reading memory-mapped registers
712 * and swaps the port value if requested.
714 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
716 struct ixgbe_bus_info *bus = &hw->bus;
719 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
720 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
721 bus->lan_id = bus->func;
723 /* check for a port swap */
724 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
725 if (reg & IXGBE_FACTPS_LFS)
730 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
731 * @hw: pointer to hardware structure
733 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
734 * disables transmit and receive units. The adapter_stopped flag is used by
735 * the shared code and drivers to determine if the adapter is in a stopped
736 * state and should not touch the hardware.
738 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
744 * Set the adapter_stopped flag so other driver functions stop touching
747 hw->adapter_stopped = true;
749 /* Disable the receive unit */
750 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0);
752 /* Clear interrupt mask to stop interrupts from being generated */
753 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
755 /* Clear any pending interrupts, flush previous writes */
756 IXGBE_READ_REG(hw, IXGBE_EICR);
758 /* Disable the transmit unit. Each queue must be disabled. */
759 for (i = 0; i < hw->mac.max_tx_queues; i++)
760 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
762 /* Disable the receive unit by stopping each queue */
763 for (i = 0; i < hw->mac.max_rx_queues; i++) {
764 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
765 reg_val &= ~IXGBE_RXDCTL_ENABLE;
766 reg_val |= IXGBE_RXDCTL_SWFLSH;
767 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
770 /* flush all queues disables */
771 IXGBE_WRITE_FLUSH(hw);
775 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
776 * access and verify no pending requests
778 return ixgbe_disable_pcie_master(hw);
782 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
783 * @hw: pointer to hardware structure
784 * @index: led number to turn on
786 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
788 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
790 /* To turn on the LED, set mode to ON. */
791 led_reg &= ~IXGBE_LED_MODE_MASK(index);
792 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
793 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
794 IXGBE_WRITE_FLUSH(hw);
800 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
801 * @hw: pointer to hardware structure
802 * @index: led number to turn off
804 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
806 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
808 /* To turn off the LED, set mode to OFF. */
809 led_reg &= ~IXGBE_LED_MODE_MASK(index);
810 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
811 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
812 IXGBE_WRITE_FLUSH(hw);
818 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
819 * @hw: pointer to hardware structure
821 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
822 * ixgbe_hw struct in order to set up EEPROM access.
824 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
826 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
830 if (eeprom->type == ixgbe_eeprom_uninitialized) {
831 eeprom->type = ixgbe_eeprom_none;
832 /* Set default semaphore delay to 10ms which is a well
834 eeprom->semaphore_delay = 10;
835 /* Clear EEPROM page size, it will be initialized as needed */
836 eeprom->word_page_size = 0;
839 * Check for EEPROM present first.
840 * If not present leave as none
842 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
843 if (eec & IXGBE_EEC_PRES) {
844 eeprom->type = ixgbe_eeprom_spi;
847 * SPI EEPROM is assumed here. This code would need to
848 * change if a future EEPROM is not SPI.
850 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
851 IXGBE_EEC_SIZE_SHIFT);
852 eeprom->word_size = 1 << (eeprom_size +
853 IXGBE_EEPROM_WORD_SIZE_SHIFT);
856 if (eec & IXGBE_EEC_ADDR_SIZE)
857 eeprom->address_bits = 16;
859 eeprom->address_bits = 8;
860 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
861 "%d\n", eeprom->type, eeprom->word_size,
862 eeprom->address_bits);
869 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
870 * @hw: pointer to hardware structure
871 * @offset: offset within the EEPROM to write
872 * @words: number of word(s)
873 * @data: 16 bit word(s) to write to EEPROM
875 * Reads 16 bit word(s) from EEPROM through bit-bang method
877 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
878 u16 words, u16 *data)
883 hw->eeprom.ops.init_params(hw);
886 status = IXGBE_ERR_INVALID_ARGUMENT;
890 if (offset + words > hw->eeprom.word_size) {
891 status = IXGBE_ERR_EEPROM;
896 * The EEPROM page size cannot be queried from the chip. We do lazy
897 * initialization. It is worth to do that when we write large buffer.
899 if ((hw->eeprom.word_page_size == 0) &&
900 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
901 ixgbe_detect_eeprom_page_size_generic(hw, offset);
904 * We cannot hold synchronization semaphores for too long
905 * to avoid other entity starvation. However it is more efficient
906 * to read in bursts than synchronizing access for each word.
908 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
909 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
910 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
911 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
923 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
924 * @hw: pointer to hardware structure
925 * @offset: offset within the EEPROM to be written to
926 * @words: number of word(s)
927 * @data: 16 bit word(s) to be written to the EEPROM
929 * If ixgbe_eeprom_update_checksum is not called after this function, the
930 * EEPROM will most likely contain an invalid checksum.
932 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
933 u16 words, u16 *data)
939 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
941 /* Prepare the EEPROM for writing */
942 status = ixgbe_acquire_eeprom(hw);
945 if (ixgbe_ready_eeprom(hw) != 0) {
946 ixgbe_release_eeprom(hw);
947 status = IXGBE_ERR_EEPROM;
952 for (i = 0; i < words; i++) {
953 ixgbe_standby_eeprom(hw);
955 /* Send the WRITE ENABLE command (8 bit opcode ) */
956 ixgbe_shift_out_eeprom_bits(hw,
957 IXGBE_EEPROM_WREN_OPCODE_SPI,
958 IXGBE_EEPROM_OPCODE_BITS);
960 ixgbe_standby_eeprom(hw);
963 * Some SPI eeproms use the 8th address bit embedded
966 if ((hw->eeprom.address_bits == 8) &&
967 ((offset + i) >= 128))
968 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
970 /* Send the Write command (8-bit opcode + addr) */
971 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
972 IXGBE_EEPROM_OPCODE_BITS);
973 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
974 hw->eeprom.address_bits);
976 page_size = hw->eeprom.word_page_size;
978 /* Send the data in burst via SPI*/
981 word = (word >> 8) | (word << 8);
982 ixgbe_shift_out_eeprom_bits(hw, word, 16);
987 /* do not wrap around page */
988 if (((offset + i) & (page_size - 1)) ==
991 } while (++i < words);
993 ixgbe_standby_eeprom(hw);
996 /* Done with writing - release the EEPROM */
997 ixgbe_release_eeprom(hw);
1004 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1005 * @hw: pointer to hardware structure
1006 * @offset: offset within the EEPROM to be written to
1007 * @data: 16 bit word to be written to the EEPROM
1009 * If ixgbe_eeprom_update_checksum is not called after this function, the
1010 * EEPROM will most likely contain an invalid checksum.
1012 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1016 hw->eeprom.ops.init_params(hw);
1018 if (offset >= hw->eeprom.word_size) {
1019 status = IXGBE_ERR_EEPROM;
1023 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1030 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1031 * @hw: pointer to hardware structure
1032 * @offset: offset within the EEPROM to be read
1033 * @data: read 16 bit words(s) from EEPROM
1034 * @words: number of word(s)
1036 * Reads 16 bit word(s) from EEPROM through bit-bang method
1038 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1039 u16 words, u16 *data)
1044 hw->eeprom.ops.init_params(hw);
1047 status = IXGBE_ERR_INVALID_ARGUMENT;
1051 if (offset + words > hw->eeprom.word_size) {
1052 status = IXGBE_ERR_EEPROM;
1057 * We cannot hold synchronization semaphores for too long
1058 * to avoid other entity starvation. However it is more efficient
1059 * to read in bursts than synchronizing access for each word.
1061 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1062 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1063 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1065 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1077 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1078 * @hw: pointer to hardware structure
1079 * @offset: offset within the EEPROM to be read
1080 * @words: number of word(s)
1081 * @data: read 16 bit word(s) from EEPROM
1083 * Reads 16 bit word(s) from EEPROM through bit-bang method
1085 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1086 u16 words, u16 *data)
1090 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1093 /* Prepare the EEPROM for reading */
1094 status = ixgbe_acquire_eeprom(hw);
1097 if (ixgbe_ready_eeprom(hw) != 0) {
1098 ixgbe_release_eeprom(hw);
1099 status = IXGBE_ERR_EEPROM;
1104 for (i = 0; i < words; i++) {
1105 ixgbe_standby_eeprom(hw);
1107 * Some SPI eeproms use the 8th address bit embedded
1110 if ((hw->eeprom.address_bits == 8) &&
1111 ((offset + i) >= 128))
1112 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1114 /* Send the READ command (opcode + addr) */
1115 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1116 IXGBE_EEPROM_OPCODE_BITS);
1117 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1118 hw->eeprom.address_bits);
1120 /* Read the data. */
1121 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1122 data[i] = (word_in >> 8) | (word_in << 8);
1125 /* End this read operation */
1126 ixgbe_release_eeprom(hw);
1133 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1134 * @hw: pointer to hardware structure
1135 * @offset: offset within the EEPROM to be read
1136 * @data: read 16 bit value from EEPROM
1138 * Reads 16 bit value from EEPROM through bit-bang method
1140 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1145 hw->eeprom.ops.init_params(hw);
1147 if (offset >= hw->eeprom.word_size) {
1148 status = IXGBE_ERR_EEPROM;
1152 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1159 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1160 * @hw: pointer to hardware structure
1161 * @offset: offset of word in the EEPROM to read
1162 * @words: number of word(s)
1163 * @data: 16 bit word(s) from the EEPROM
1165 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1167 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1168 u16 words, u16 *data)
1174 hw->eeprom.ops.init_params(hw);
1177 status = IXGBE_ERR_INVALID_ARGUMENT;
1181 if (offset >= hw->eeprom.word_size) {
1182 status = IXGBE_ERR_EEPROM;
1186 for (i = 0; i < words; i++) {
1187 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) +
1188 IXGBE_EEPROM_RW_REG_START;
1190 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1191 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1194 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1195 IXGBE_EEPROM_RW_REG_DATA);
1197 hw_dbg(hw, "Eeprom read timed out\n");
1206 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1207 * @hw: pointer to hardware structure
1208 * @offset: offset within the EEPROM to be used as a scratch pad
1210 * Discover EEPROM page size by writing marching data at given offset.
1211 * This function is called only when we are writing a new large buffer
1212 * at given offset so the data would be overwritten anyway.
1214 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1217 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1221 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1224 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1225 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1226 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1227 hw->eeprom.word_page_size = 0;
1231 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1236 * When writing in burst more than the actual page size
1237 * EEPROM address wraps around current page.
1239 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1241 hw_dbg(hw, "Detected EEPROM page size = %d words.",
1242 hw->eeprom.word_page_size);
1248 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1249 * @hw: pointer to hardware structure
1250 * @offset: offset of word in the EEPROM to read
1251 * @data: word read from the EEPROM
1253 * Reads a 16 bit word from the EEPROM using the EERD register.
1255 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1257 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1261 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1262 * @hw: pointer to hardware structure
1263 * @offset: offset of word in the EEPROM to write
1264 * @words: number of word(s)
1265 * @data: word(s) write to the EEPROM
1267 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1269 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1270 u16 words, u16 *data)
1276 hw->eeprom.ops.init_params(hw);
1279 status = IXGBE_ERR_INVALID_ARGUMENT;
1283 if (offset >= hw->eeprom.word_size) {
1284 status = IXGBE_ERR_EEPROM;
1288 for (i = 0; i < words; i++) {
1289 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1290 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1291 IXGBE_EEPROM_RW_REG_START;
1293 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1295 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1299 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1301 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1303 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1313 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1314 * @hw: pointer to hardware structure
1315 * @offset: offset of word in the EEPROM to write
1316 * @data: word write to the EEPROM
1318 * Write a 16 bit word to the EEPROM using the EEWR register.
1320 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1322 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1326 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1327 * @hw: pointer to hardware structure
1328 * @ee_reg: EEPROM flag for polling
1330 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1331 * read or write is done respectively.
1333 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1337 s32 status = IXGBE_ERR_EEPROM;
1339 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1340 if (ee_reg == IXGBE_NVM_POLL_READ)
1341 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1343 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1345 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1355 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1356 * @hw: pointer to hardware structure
1358 * Prepares EEPROM for access using bit-bang method. This function should
1359 * be called before issuing a command to the EEPROM.
1361 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1367 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1369 status = IXGBE_ERR_SWFW_SYNC;
1372 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1374 /* Request EEPROM Access */
1375 eec |= IXGBE_EEC_REQ;
1376 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1378 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1379 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1380 if (eec & IXGBE_EEC_GNT)
1385 /* Release if grant not acquired */
1386 if (!(eec & IXGBE_EEC_GNT)) {
1387 eec &= ~IXGBE_EEC_REQ;
1388 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1389 hw_dbg(hw, "Could not acquire EEPROM grant\n");
1391 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1392 status = IXGBE_ERR_EEPROM;
1395 /* Setup EEPROM for Read/Write */
1397 /* Clear CS and SK */
1398 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1399 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1400 IXGBE_WRITE_FLUSH(hw);
1408 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1409 * @hw: pointer to hardware structure
1411 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1413 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1415 s32 status = IXGBE_ERR_EEPROM;
1420 /* Get SMBI software semaphore between device drivers first */
1421 for (i = 0; i < timeout; i++) {
1423 * If the SMBI bit is 0 when we read it, then the bit will be
1424 * set and we have the semaphore
1426 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1427 if (!(swsm & IXGBE_SWSM_SMBI)) {
1435 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore "
1438 * this release is particularly important because our attempts
1439 * above to get the semaphore may have succeeded, and if there
1440 * was a timeout, we should unconditionally clear the semaphore
1441 * bits to free the driver to make progress
1443 ixgbe_release_eeprom_semaphore(hw);
1448 * If the SMBI bit is 0 when we read it, then the bit will be
1449 * set and we have the semaphore
1451 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1452 if (!(swsm & IXGBE_SWSM_SMBI))
1456 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1458 for (i = 0; i < timeout; i++) {
1459 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1461 /* Set the SW EEPROM semaphore bit to request access */
1462 swsm |= IXGBE_SWSM_SWESMBI;
1463 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1466 * If we set the bit successfully then we got the
1469 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1470 if (swsm & IXGBE_SWSM_SWESMBI)
1477 * Release semaphores and return error if SW EEPROM semaphore
1478 * was not granted because we don't have access to the EEPROM
1481 hw_dbg(hw, "SWESMBI Software EEPROM semaphore "
1483 ixgbe_release_eeprom_semaphore(hw);
1484 status = IXGBE_ERR_EEPROM;
1487 hw_dbg(hw, "Software semaphore SMBI between device drivers "
1495 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1496 * @hw: pointer to hardware structure
1498 * This function clears hardware semaphore bits.
1500 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1504 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1506 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1507 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1508 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1509 IXGBE_WRITE_FLUSH(hw);
1513 * ixgbe_ready_eeprom - Polls for EEPROM ready
1514 * @hw: pointer to hardware structure
1516 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1523 * Read "Status Register" repeatedly until the LSB is cleared. The
1524 * EEPROM will signal that the command has been completed by clearing
1525 * bit 0 of the internal status register. If it's not cleared within
1526 * 5 milliseconds, then error out.
1528 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1529 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1530 IXGBE_EEPROM_OPCODE_BITS);
1531 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1532 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1536 ixgbe_standby_eeprom(hw);
1540 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1541 * devices (and only 0-5mSec on 5V devices)
1543 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1544 hw_dbg(hw, "SPI EEPROM Status error\n");
1545 status = IXGBE_ERR_EEPROM;
1552 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1553 * @hw: pointer to hardware structure
1555 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1559 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1561 /* Toggle CS to flush commands */
1562 eec |= IXGBE_EEC_CS;
1563 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1564 IXGBE_WRITE_FLUSH(hw);
1566 eec &= ~IXGBE_EEC_CS;
1567 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1568 IXGBE_WRITE_FLUSH(hw);
1573 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1574 * @hw: pointer to hardware structure
1575 * @data: data to send to the EEPROM
1576 * @count: number of bits to shift out
1578 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1585 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1588 * Mask is used to shift "count" bits of "data" out to the EEPROM
1589 * one bit at a time. Determine the starting bit based on count
1591 mask = 0x01 << (count - 1);
1593 for (i = 0; i < count; i++) {
1595 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1596 * "1", and then raising and then lowering the clock (the SK
1597 * bit controls the clock input to the EEPROM). A "0" is
1598 * shifted out to the EEPROM by setting "DI" to "0" and then
1599 * raising and then lowering the clock.
1602 eec |= IXGBE_EEC_DI;
1604 eec &= ~IXGBE_EEC_DI;
1606 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1607 IXGBE_WRITE_FLUSH(hw);
1611 ixgbe_raise_eeprom_clk(hw, &eec);
1612 ixgbe_lower_eeprom_clk(hw, &eec);
1615 * Shift mask to signify next bit of data to shift in to the
1621 /* We leave the "DI" bit set to "0" when we leave this routine. */
1622 eec &= ~IXGBE_EEC_DI;
1623 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1624 IXGBE_WRITE_FLUSH(hw);
1628 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1629 * @hw: pointer to hardware structure
1631 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1638 * In order to read a register from the EEPROM, we need to shift
1639 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1640 * the clock input to the EEPROM (setting the SK bit), and then reading
1641 * the value of the "DO" bit. During this "shifting in" process the
1642 * "DI" bit should always be clear.
1644 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1646 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1648 for (i = 0; i < count; i++) {
1650 ixgbe_raise_eeprom_clk(hw, &eec);
1652 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1654 eec &= ~(IXGBE_EEC_DI);
1655 if (eec & IXGBE_EEC_DO)
1658 ixgbe_lower_eeprom_clk(hw, &eec);
1665 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1666 * @hw: pointer to hardware structure
1667 * @eec: EEC register's current value
1669 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1672 * Raise the clock input to the EEPROM
1673 * (setting the SK bit), then delay
1675 *eec = *eec | IXGBE_EEC_SK;
1676 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1677 IXGBE_WRITE_FLUSH(hw);
1682 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1683 * @hw: pointer to hardware structure
1684 * @eecd: EECD's current value
1686 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1689 * Lower the clock input to the EEPROM (clearing the SK bit), then
1692 *eec = *eec & ~IXGBE_EEC_SK;
1693 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1694 IXGBE_WRITE_FLUSH(hw);
1699 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1700 * @hw: pointer to hardware structure
1702 static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1706 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1708 eec |= IXGBE_EEC_CS; /* Pull CS high */
1709 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1711 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1712 IXGBE_WRITE_FLUSH(hw);
1716 /* Stop requesting EEPROM access */
1717 eec &= ~IXGBE_EEC_REQ;
1718 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1720 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1722 /* Delay before attempt to obtain semaphore again to allow FW access */
1723 msleep(hw->eeprom.semaphore_delay);
1727 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
1728 * @hw: pointer to hardware structure
1730 u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
1739 /* Include 0x0-0x3F in the checksum */
1740 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
1741 if (hw->eeprom.ops.read(hw, i, &word) != 0) {
1742 hw_dbg(hw, "EEPROM read failed\n");
1748 /* Include all data from pointers except for the fw pointer */
1749 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
1750 hw->eeprom.ops.read(hw, i, &pointer);
1752 /* Make sure the pointer seems valid */
1753 if (pointer != 0xFFFF && pointer != 0) {
1754 hw->eeprom.ops.read(hw, pointer, &length);
1756 if (length != 0xFFFF && length != 0) {
1757 for (j = pointer+1; j <= pointer+length; j++) {
1758 hw->eeprom.ops.read(hw, j, &word);
1765 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1771 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
1772 * @hw: pointer to hardware structure
1773 * @checksum_val: calculated checksum
1775 * Performs checksum calculation and validates the EEPROM checksum. If the
1776 * caller does not need checksum_val, the value can be NULL.
1778 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1783 u16 read_checksum = 0;
1786 * Read the first word from the EEPROM. If this times out or fails, do
1787 * not continue or we could be in for a very long wait while every
1790 status = hw->eeprom.ops.read(hw, 0, &checksum);
1793 checksum = hw->eeprom.ops.calc_checksum(hw);
1795 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
1798 * Verify read checksum from EEPROM is the same as
1799 * calculated checksum
1801 if (read_checksum != checksum)
1802 status = IXGBE_ERR_EEPROM_CHECKSUM;
1804 /* If the user cares, return the calculated checksum */
1806 *checksum_val = checksum;
1808 hw_dbg(hw, "EEPROM read failed\n");
1815 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1816 * @hw: pointer to hardware structure
1818 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1824 * Read the first word from the EEPROM. If this times out or fails, do
1825 * not continue or we could be in for a very long wait while every
1828 status = hw->eeprom.ops.read(hw, 0, &checksum);
1831 checksum = hw->eeprom.ops.calc_checksum(hw);
1832 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
1835 hw_dbg(hw, "EEPROM read failed\n");
1842 * ixgbe_validate_mac_addr - Validate MAC address
1843 * @mac_addr: pointer to MAC address.
1845 * Tests a MAC address to ensure it is a valid Individual Address
1847 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
1851 /* Make sure it is not a multicast address */
1852 if (IXGBE_IS_MULTICAST(mac_addr)) {
1853 hw_dbg(hw, "MAC address is multicast\n");
1854 status = IXGBE_ERR_INVALID_MAC_ADDR;
1855 /* Not a broadcast address */
1856 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
1857 hw_dbg(hw, "MAC address is broadcast\n");
1858 status = IXGBE_ERR_INVALID_MAC_ADDR;
1859 /* Reject the zero address */
1860 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
1861 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
1862 hw_dbg(hw, "MAC address is all zeros\n");
1863 status = IXGBE_ERR_INVALID_MAC_ADDR;
1869 * ixgbe_set_rar_generic - Set Rx address register
1870 * @hw: pointer to hardware structure
1871 * @index: Receive address register to write
1872 * @addr: Address to put into receive address register
1873 * @vmdq: VMDq "set" or "pool" index
1874 * @enable_addr: set flag that address is active
1876 * Puts an ethernet address into a receive address register.
1878 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1881 u32 rar_low, rar_high;
1882 u32 rar_entries = hw->mac.num_rar_entries;
1884 /* Make sure we are using a valid rar index range */
1885 if (index >= rar_entries) {
1886 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1887 return IXGBE_ERR_INVALID_ARGUMENT;
1890 /* setup VMDq pool selection before this RAR gets enabled */
1891 hw->mac.ops.set_vmdq(hw, index, vmdq);
1894 * HW expects these in little endian so we reverse the byte
1895 * order from network order (big endian) to little endian
1897 rar_low = ((u32)addr[0] |
1898 ((u32)addr[1] << 8) |
1899 ((u32)addr[2] << 16) |
1900 ((u32)addr[3] << 24));
1902 * Some parts put the VMDq setting in the extra RAH bits,
1903 * so save everything except the lower 16 bits that hold part
1904 * of the address and the address valid bit.
1906 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1907 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1908 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
1910 if (enable_addr != 0)
1911 rar_high |= IXGBE_RAH_AV;
1913 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1914 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1920 * ixgbe_clear_rar_generic - Remove Rx address register
1921 * @hw: pointer to hardware structure
1922 * @index: Receive address register to write
1924 * Clears an ethernet address from a receive address register.
1926 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1929 u32 rar_entries = hw->mac.num_rar_entries;
1931 /* Make sure we are using a valid rar index range */
1932 if (index >= rar_entries) {
1933 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1934 return IXGBE_ERR_INVALID_ARGUMENT;
1938 * Some parts put the VMDq setting in the extra RAH bits,
1939 * so save everything except the lower 16 bits that hold part
1940 * of the address and the address valid bit.
1942 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1943 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1945 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1946 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1948 /* clear VMDq pool/queue selection for this RAR */
1949 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
1955 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
1956 * @hw: pointer to hardware structure
1958 * Places the MAC address in receive address register 0 and clears the rest
1959 * of the receive address registers. Clears the multicast table. Assumes
1960 * the receiver is in reset when the routine is called.
1962 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
1965 u32 rar_entries = hw->mac.num_rar_entries;
1968 * If the current mac address is valid, assume it is a software override
1969 * to the permanent address.
1970 * Otherwise, use the permanent address from the eeprom.
1972 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
1973 IXGBE_ERR_INVALID_MAC_ADDR) {
1974 /* Get the MAC address from the RAR0 for later reference */
1975 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
1977 hw_dbg(hw, " Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
1978 hw->mac.addr[0], hw->mac.addr[1],
1980 hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3],
1981 hw->mac.addr[4], hw->mac.addr[5]);
1983 /* Setup the receive address. */
1984 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
1985 hw_dbg(hw, " New MAC Addr =%.2X %.2X %.2X ",
1986 hw->mac.addr[0], hw->mac.addr[1],
1988 hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3],
1989 hw->mac.addr[4], hw->mac.addr[5]);
1991 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1993 /* clear VMDq pool/queue selection for RAR 0 */
1994 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
1996 hw->addr_ctrl.overflow_promisc = 0;
1998 hw->addr_ctrl.rar_used_count = 1;
2000 /* Zero out the other receive addresses. */
2001 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
2002 for (i = 1; i < rar_entries; i++) {
2003 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2004 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2008 hw->addr_ctrl.mta_in_use = 0;
2009 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2011 hw_dbg(hw, " Clearing MTA\n");
2012 for (i = 0; i < hw->mac.mcft_size; i++)
2013 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2015 ixgbe_init_uta_tables(hw);
2021 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2022 * @hw: pointer to hardware structure
2023 * @addr: new address
2025 * Adds it to unused receive address register or goes into promiscuous mode.
2027 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2029 u32 rar_entries = hw->mac.num_rar_entries;
2032 hw_dbg(hw, " UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2033 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2036 * Place this address in the RAR if there is room,
2037 * else put the controller into promiscuous mode
2039 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2040 rar = hw->addr_ctrl.rar_used_count;
2041 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2042 hw_dbg(hw, "Added a secondary address to RAR[%d]\n", rar);
2043 hw->addr_ctrl.rar_used_count++;
2045 hw->addr_ctrl.overflow_promisc++;
2048 hw_dbg(hw, "ixgbe_add_uc_addr Complete\n");
2052 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2053 * @hw: pointer to hardware structure
2054 * @addr_list: the list of new addresses
2055 * @addr_count: number of addresses
2056 * @next: iterator function to walk the address list
2058 * The given list replaces any existing list. Clears the secondary addrs from
2059 * receive address registers. Uses unused receive address registers for the
2060 * first secondary addresses, and falls back to promiscuous mode as needed.
2062 * Drivers using secondary unicast addresses must set user_set_promisc when
2063 * manually putting the device into promiscuous mode.
2065 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2066 u32 addr_count, ixgbe_mc_addr_itr next)
2070 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2076 * Clear accounting of old secondary address list,
2077 * don't count RAR[0]
2079 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2080 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2081 hw->addr_ctrl.overflow_promisc = 0;
2083 /* Zero out the other receive addresses */
2084 hw_dbg(hw, "Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2085 for (i = 0; i < uc_addr_in_use; i++) {
2086 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2087 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2090 /* Add the new addresses */
2091 for (i = 0; i < addr_count; i++) {
2092 hw_dbg(hw, " Adding the secondary addresses:\n");
2093 addr = next(hw, &addr_list, &vmdq);
2094 ixgbe_add_uc_addr(hw, addr, vmdq);
2097 if (hw->addr_ctrl.overflow_promisc) {
2098 /* enable promisc if not already in overflow or set by user */
2099 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2100 hw_dbg(hw, " Entering address overflow promisc mode\n");
2101 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2102 fctrl |= IXGBE_FCTRL_UPE;
2103 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2106 /* only disable if set by overflow, not by user */
2107 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2108 hw_dbg(hw, " Leaving address overflow promisc mode\n");
2109 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2110 fctrl &= ~IXGBE_FCTRL_UPE;
2111 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2115 hw_dbg(hw, "ixgbe_update_uc_addr_list_generic Complete\n");
2120 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2121 * @hw: pointer to hardware structure
2122 * @mc_addr: the multicast address
2124 * Extracts the 12 bits, from a multicast address, to determine which
2125 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2126 * incoming rx multicast addresses, to determine the bit-vector to check in
2127 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2128 * by the MO field of the MCSTCTRL. The MO field is set during initialization
2129 * to mc_filter_type.
2131 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2135 switch (hw->mac.mc_filter_type) {
2136 case 0: /* use bits [47:36] of the address */
2137 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2139 case 1: /* use bits [46:35] of the address */
2140 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2142 case 2: /* use bits [45:34] of the address */
2143 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2145 case 3: /* use bits [43:32] of the address */
2146 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2148 default: /* Invalid mc_filter_type */
2149 hw_dbg(hw, "MC filter type param set incorrectly\n");
2153 /* vector can only be 12-bits or boundary will be exceeded */
2159 * ixgbe_set_mta - Set bit-vector in multicast table
2160 * @hw: pointer to hardware structure
2161 * @hash_value: Multicast address hash value
2163 * Sets the bit-vector in the multicast table.
2165 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2171 hw->addr_ctrl.mta_in_use++;
2173 vector = ixgbe_mta_vector(hw, mc_addr);
2174 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
2177 * The MTA is a register array of 128 32-bit registers. It is treated
2178 * like an array of 4096 bits. We want to set bit
2179 * BitArray[vector_value]. So we figure out what register the bit is
2180 * in, read it, OR in the new bit, then write back the new value. The
2181 * register is determined by the upper 7 bits of the vector value and
2182 * the bit within that register are determined by the lower 5 bits of
2185 vector_reg = (vector >> 5) & 0x7F;
2186 vector_bit = vector & 0x1F;
2187 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2191 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2192 * @hw: pointer to hardware structure
2193 * @mc_addr_list: the list of new multicast addresses
2194 * @mc_addr_count: number of addresses
2195 * @next: iterator function to walk the multicast address list
2196 * @clear: flag, when set clears the table beforehand
2198 * When the clear flag is set, the given list replaces any existing list.
2199 * Hashes the given addresses into the multicast table.
2201 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2202 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2209 * Set the new number of MC addresses that we are being requested to
2212 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2213 hw->addr_ctrl.mta_in_use = 0;
2215 /* Clear mta_shadow */
2217 hw_dbg(hw, " Clearing MTA\n");
2218 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2221 /* Update mta_shadow */
2222 for (i = 0; i < mc_addr_count; i++) {
2223 hw_dbg(hw, " Adding the multicast addresses:\n");
2224 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2228 for (i = 0; i < hw->mac.mcft_size; i++)
2229 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2230 hw->mac.mta_shadow[i]);
2232 if (hw->addr_ctrl.mta_in_use > 0)
2233 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2234 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2236 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
2241 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2242 * @hw: pointer to hardware structure
2244 * Enables multicast address in RAR and the use of the multicast hash table.
2246 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2248 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2250 if (a->mta_in_use > 0)
2251 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2252 hw->mac.mc_filter_type);
2258 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2259 * @hw: pointer to hardware structure
2261 * Disables multicast address in RAR and the use of the multicast hash table.
2263 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2265 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2267 if (a->mta_in_use > 0)
2268 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2274 * ixgbe_fc_enable_generic - Enable flow control
2275 * @hw: pointer to hardware structure
2277 * Enable flow control according to the current settings.
2279 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2282 u32 mflcn_reg, fccfg_reg;
2287 /* Validate the water mark configuration */
2288 if (!hw->fc.pause_time) {
2289 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2293 /* Low water mark of zero causes XOFF floods */
2294 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2295 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2296 hw->fc.high_water[i]) {
2297 if (!hw->fc.low_water[i] ||
2298 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2299 hw_dbg(hw, "Invalid water mark configuration\n");
2300 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2306 /* Negotiate the fc mode to use */
2307 ixgbe_fc_autoneg(hw);
2309 /* Disable any previous flow control settings */
2310 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2311 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2313 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2314 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2317 * The possible values of fc.current_mode are:
2318 * 0: Flow control is completely disabled
2319 * 1: Rx flow control is enabled (we can receive pause frames,
2320 * but not send pause frames).
2321 * 2: Tx flow control is enabled (we can send pause frames but
2322 * we do not support receiving pause frames).
2323 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2326 switch (hw->fc.current_mode) {
2329 * Flow control is disabled by software override or autoneg.
2330 * The code below will actually disable it in the HW.
2333 case ixgbe_fc_rx_pause:
2335 * Rx Flow control is enabled and Tx Flow control is
2336 * disabled by software override. Since there really
2337 * isn't a way to advertise that we are capable of RX
2338 * Pause ONLY, we will advertise that we support both
2339 * symmetric and asymmetric Rx PAUSE. Later, we will
2340 * disable the adapter's ability to send PAUSE frames.
2342 mflcn_reg |= IXGBE_MFLCN_RFCE;
2344 case ixgbe_fc_tx_pause:
2346 * Tx Flow control is enabled, and Rx Flow control is
2347 * disabled by software override.
2349 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2352 /* Flow control (both Rx and Tx) is enabled by SW override. */
2353 mflcn_reg |= IXGBE_MFLCN_RFCE;
2354 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2357 hw_dbg(hw, "Flow control param set incorrectly\n");
2358 ret_val = IXGBE_ERR_CONFIG;
2363 /* Set 802.3x based flow control settings. */
2364 mflcn_reg |= IXGBE_MFLCN_DPF;
2365 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2366 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2369 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2370 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2371 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2372 hw->fc.high_water[i]) {
2373 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2374 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2375 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2377 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2379 * In order to prevent Tx hangs when the internal Tx
2380 * switch is enabled we must set the high water mark
2381 * to the maximum FCRTH value. This allows the Tx
2382 * switch to function even under heavy Rx workloads.
2384 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
2387 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2390 /* Configure pause time (2 TCs per register) */
2391 reg = hw->fc.pause_time * 0x00010001;
2392 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2393 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2395 /* Configure flow control refresh threshold value */
2396 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2403 * ixgbe_negotiate_fc - Negotiate flow control
2404 * @hw: pointer to hardware structure
2405 * @adv_reg: flow control advertised settings
2406 * @lp_reg: link partner's flow control settings
2407 * @adv_sym: symmetric pause bit in advertisement
2408 * @adv_asm: asymmetric pause bit in advertisement
2409 * @lp_sym: symmetric pause bit in link partner advertisement
2410 * @lp_asm: asymmetric pause bit in link partner advertisement
2412 * Find the intersection between advertised settings and link partner's
2413 * advertised settings
2415 static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2416 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2418 if ((!(adv_reg)) || (!(lp_reg)))
2419 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2421 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2423 * Now we need to check if the user selected Rx ONLY
2424 * of pause frames. In this case, we had to advertise
2425 * FULL flow control because we could not advertise RX
2426 * ONLY. Hence, we must now check to see if we need to
2427 * turn OFF the TRANSMISSION of PAUSE frames.
2429 if (hw->fc.requested_mode == ixgbe_fc_full) {
2430 hw->fc.current_mode = ixgbe_fc_full;
2431 hw_dbg(hw, "Flow Control = FULL.\n");
2433 hw->fc.current_mode = ixgbe_fc_rx_pause;
2434 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n");
2436 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2437 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2438 hw->fc.current_mode = ixgbe_fc_tx_pause;
2439 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
2440 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2441 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2442 hw->fc.current_mode = ixgbe_fc_rx_pause;
2443 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
2445 hw->fc.current_mode = ixgbe_fc_none;
2446 hw_dbg(hw, "Flow Control = NONE.\n");
2452 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2453 * @hw: pointer to hardware structure
2455 * Enable flow control according on 1 gig fiber.
2457 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2459 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2460 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2463 * On multispeed fiber at 1g, bail out if
2464 * - link is up but AN did not complete, or if
2465 * - link is up and AN completed but timed out
2468 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2469 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2470 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))
2473 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2474 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2476 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2477 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2478 IXGBE_PCS1GANA_ASM_PAUSE,
2479 IXGBE_PCS1GANA_SYM_PAUSE,
2480 IXGBE_PCS1GANA_ASM_PAUSE);
2487 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2488 * @hw: pointer to hardware structure
2490 * Enable flow control according to IEEE clause 37.
2492 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2494 u32 links2, anlp1_reg, autoc_reg, links;
2495 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2498 * On backplane, bail out if
2499 * - backplane autoneg was not completed, or if
2500 * - we are 82599 and link partner is not AN enabled
2502 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2503 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0)
2506 if (hw->mac.type == ixgbe_mac_82599EB) {
2507 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2508 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)
2512 * Read the 10g AN autoc and LP ability registers and resolve
2513 * local flow control settings accordingly
2515 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2516 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2518 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2519 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2520 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2527 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2528 * @hw: pointer to hardware structure
2530 * Enable flow control according to IEEE clause 37.
2532 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2534 u16 technology_ability_reg = 0;
2535 u16 lp_technology_ability_reg = 0;
2537 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
2538 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2539 &technology_ability_reg);
2540 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
2541 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2542 &lp_technology_ability_reg);
2544 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2545 (u32)lp_technology_ability_reg,
2546 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2547 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2551 * ixgbe_fc_autoneg - Configure flow control
2552 * @hw: pointer to hardware structure
2554 * Compares our advertised flow control capabilities to those advertised by
2555 * our link partner, and determines the proper flow control mode to use.
2557 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
2559 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2560 ixgbe_link_speed speed;
2564 * AN should have completed when the cable was plugged in.
2565 * Look for reasons to bail out. Bail out if:
2566 * - FC autoneg is disabled, or if
2569 if (hw->fc.disable_fc_autoneg)
2572 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2576 switch (hw->phy.media_type) {
2577 /* Autoneg flow control on fiber adapters */
2578 case ixgbe_media_type_fiber:
2579 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2580 ret_val = ixgbe_fc_autoneg_fiber(hw);
2583 /* Autoneg flow control on backplane adapters */
2584 case ixgbe_media_type_backplane:
2585 ret_val = ixgbe_fc_autoneg_backplane(hw);
2588 /* Autoneg flow control on copper adapters */
2589 case ixgbe_media_type_copper:
2590 if (ixgbe_device_supports_autoneg_fc(hw) == 0)
2591 ret_val = ixgbe_fc_autoneg_copper(hw);
2600 hw->fc.fc_was_autonegged = true;
2602 hw->fc.fc_was_autonegged = false;
2603 hw->fc.current_mode = hw->fc.requested_mode;
2608 * ixgbe_disable_pcie_master - Disable PCI-express master access
2609 * @hw: pointer to hardware structure
2611 * Disables PCI-Express master access and verifies there are no pending
2612 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2613 * bit hasn't caused the master requests to be disabled, else 0
2614 * is returned signifying master requests disabled.
2616 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2621 /* Always set this bit to ensure any future transactions are blocked */
2622 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
2624 /* Exit if master requets are blocked */
2625 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2628 /* Poll for master request bit to clear */
2629 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2631 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2636 * Two consecutive resets are required via CTRL.RST per datasheet
2637 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2638 * of this need. The first reset prevents new master requests from
2639 * being issued by our device. We then must wait 1usec or more for any
2640 * remaining completions from the PCIe bus to trickle in, and then reset
2641 * again to clear out any effects they may have had on our device.
2643 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n");
2644 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2647 * Before proceeding, make sure that the PCIe block does not have
2648 * transactions pending.
2650 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2652 if (!(IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS) &
2653 IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
2657 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
2658 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
2665 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
2666 * @hw: pointer to hardware structure
2667 * @mask: Mask to specify which semaphore to acquire
2669 * Acquires the SWFW semaphore through the GSSR register for the specified
2670 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2672 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2676 u32 fwmask = mask << 5;
2681 * SW EEPROM semaphore bit is used for access to all
2682 * SW_FW_SYNC/GSSR bits (not just EEPROM)
2684 if (ixgbe_get_eeprom_semaphore(hw))
2685 return IXGBE_ERR_SWFW_SYNC;
2687 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2688 if (!(gssr & (fwmask | swmask)))
2692 * Firmware currently using resource (fwmask) or other software
2693 * thread currently using resource (swmask)
2695 ixgbe_release_eeprom_semaphore(hw);
2701 hw_dbg(hw, "Driver can't access resource, SW_FW_SYNC timeout.\n");
2702 return IXGBE_ERR_SWFW_SYNC;
2706 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2708 ixgbe_release_eeprom_semaphore(hw);
2713 * ixgbe_release_swfw_sync - Release SWFW semaphore
2714 * @hw: pointer to hardware structure
2715 * @mask: Mask to specify which semaphore to release
2717 * Releases the SWFW semaphore through the GSSR register for the specified
2718 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2720 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2725 ixgbe_get_eeprom_semaphore(hw);
2727 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2729 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2731 ixgbe_release_eeprom_semaphore(hw);
2735 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
2736 * @hw: pointer to hardware structure
2738 * Stops the receive data path and waits for the HW to internally empty
2739 * the Rx security block
2741 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
2743 #define IXGBE_MAX_SECRX_POLL 40
2748 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2749 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2750 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2751 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2752 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2753 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2756 /* Use interrupt-safe sleep just in case */
2760 /* For informational purposes only */
2761 if (i >= IXGBE_MAX_SECRX_POLL)
2762 hw_dbg(hw, "Rx unit being enabled before security "
2763 "path fully disabled. Continuing with init.\n");
2769 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
2770 * @hw: pointer to hardware structure
2772 * Enables the receive data path.
2774 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
2778 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2779 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2780 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2781 IXGBE_WRITE_FLUSH(hw);
2787 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2788 * @hw: pointer to hardware structure
2789 * @regval: register value to write to RXCTRL
2791 * Enables the Rx DMA unit
2793 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2795 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2801 * ixgbe_blink_led_start_generic - Blink LED based on index.
2802 * @hw: pointer to hardware structure
2803 * @index: led number to blink
2805 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2807 ixgbe_link_speed speed = 0;
2809 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2810 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2813 * Link must be up to auto-blink the LEDs;
2814 * Force it if link is down.
2816 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2819 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2820 autoc_reg |= IXGBE_AUTOC_FLU;
2821 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2822 IXGBE_WRITE_FLUSH(hw);
2826 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2827 led_reg |= IXGBE_LED_BLINK(index);
2828 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2829 IXGBE_WRITE_FLUSH(hw);
2835 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2836 * @hw: pointer to hardware structure
2837 * @index: led number to stop blinking
2839 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2841 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2842 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2844 autoc_reg &= ~IXGBE_AUTOC_FLU;
2845 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2846 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2848 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2849 led_reg &= ~IXGBE_LED_BLINK(index);
2850 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2851 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2852 IXGBE_WRITE_FLUSH(hw);
2858 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2859 * @hw: pointer to hardware structure
2860 * @san_mac_offset: SAN MAC address offset
2862 * This function will read the EEPROM location for the SAN MAC address
2863 * pointer, and returns the value at that location. This is used in both
2864 * get and set mac_addr routines.
2866 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
2867 u16 *san_mac_offset)
2870 * First read the EEPROM pointer to see if the MAC addresses are
2873 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2879 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2880 * @hw: pointer to hardware structure
2881 * @san_mac_addr: SAN MAC address
2883 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2884 * per-port, so set_lan_id() must be called before reading the addresses.
2885 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2886 * upon for non-SFP connections, so we must call it here.
2888 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2890 u16 san_mac_data, san_mac_offset;
2894 * First read the EEPROM pointer to see if the MAC addresses are
2895 * available. If they're not, no point in calling set_lan_id() here.
2897 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2899 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2901 * No addresses available in this EEPROM. It's not an
2902 * error though, so just wipe the local address and return.
2904 for (i = 0; i < 6; i++)
2905 san_mac_addr[i] = 0xFF;
2907 goto san_mac_addr_out;
2910 /* make sure we know which port we need to program */
2911 hw->mac.ops.set_lan_id(hw);
2912 /* apply the port offset to the address offset */
2913 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2914 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2915 for (i = 0; i < 3; i++) {
2916 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2917 san_mac_addr[i * 2] = (u8)(san_mac_data);
2918 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2927 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
2928 * @hw: pointer to hardware structure
2929 * @san_mac_addr: SAN MAC address
2931 * Write a SAN MAC address to the EEPROM.
2933 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2936 u16 san_mac_data, san_mac_offset;
2939 /* Look for SAN mac address pointer. If not defined, return */
2940 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2942 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2943 status = IXGBE_ERR_NO_SAN_ADDR_PTR;
2944 goto san_mac_addr_out;
2947 /* Make sure we know which port we need to write */
2948 hw->mac.ops.set_lan_id(hw);
2949 /* Apply the port offset to the address offset */
2950 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2951 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2953 for (i = 0; i < 3; i++) {
2954 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
2955 san_mac_data |= (u16)(san_mac_addr[i * 2]);
2956 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
2965 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2966 * @hw: pointer to hardware structure
2968 * Read PCIe configuration space, and get the MSI-X vector count from
2969 * the capabilities table.
2971 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
2977 switch (hw->mac.type) {
2978 case ixgbe_mac_82598EB:
2979 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
2980 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
2982 case ixgbe_mac_82599EB:
2983 case ixgbe_mac_X540:
2984 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
2985 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
2991 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
2992 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2994 /* MSI-X count is zero-based in HW */
2997 if (msix_count > max_msix_count)
2998 msix_count = max_msix_count;
3004 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3005 * @hw: pointer to hardware structure
3006 * @addr: Address to put into receive address register
3007 * @vmdq: VMDq pool to assign
3009 * Puts an ethernet address into a receive address register, or
3010 * finds the rar that it is aleady in; adds to the pool list
3012 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3014 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3015 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3017 u32 rar_low, rar_high;
3018 u32 addr_low, addr_high;
3020 /* swap bytes for HW little endian */
3021 addr_low = addr[0] | (addr[1] << 8)
3024 addr_high = addr[4] | (addr[5] << 8);
3027 * Either find the mac_id in rar or find the first empty space.
3028 * rar_highwater points to just after the highest currently used
3029 * rar in order to shorten the search. It grows when we add a new
3032 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3033 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3035 if (((IXGBE_RAH_AV & rar_high) == 0)
3036 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3037 first_empty_rar = rar;
3038 } else if ((rar_high & 0xFFFF) == addr_high) {
3039 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3040 if (rar_low == addr_low)
3041 break; /* found it already in the rars */
3045 if (rar < hw->mac.rar_highwater) {
3046 /* already there so just add to the pool bits */
3047 ixgbe_set_vmdq(hw, rar, vmdq);
3048 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3049 /* stick it into first empty RAR slot we found */
3050 rar = first_empty_rar;
3051 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3052 } else if (rar == hw->mac.rar_highwater) {
3053 /* add it to the top of the list and inc the highwater mark */
3054 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3055 hw->mac.rar_highwater++;
3056 } else if (rar >= hw->mac.num_rar_entries) {
3057 return IXGBE_ERR_INVALID_MAC_ADDR;
3061 * If we found rar[0], make sure the default pool bit (we use pool 0)
3062 * remains cleared to be sure default pool packets will get delivered
3065 ixgbe_clear_vmdq(hw, rar, 0);
3071 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3072 * @hw: pointer to hardware struct
3073 * @rar: receive address register index to disassociate
3074 * @vmdq: VMDq pool index to remove from the rar
3076 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3078 u32 mpsar_lo, mpsar_hi;
3079 u32 rar_entries = hw->mac.num_rar_entries;
3081 /* Make sure we are using a valid rar index range */
3082 if (rar >= rar_entries) {
3083 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
3084 return IXGBE_ERR_INVALID_ARGUMENT;
3087 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3088 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3090 if (!mpsar_lo && !mpsar_hi)
3093 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3095 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3099 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3102 } else if (vmdq < 32) {
3103 mpsar_lo &= ~(1 << vmdq);
3104 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3106 mpsar_hi &= ~(1 << (vmdq - 32));
3107 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3110 /* was that the last pool using this rar? */
3111 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
3112 hw->mac.ops.clear_rar(hw, rar);
3118 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3119 * @hw: pointer to hardware struct
3120 * @rar: receive address register index to associate with a VMDq index
3121 * @vmdq: VMDq pool index
3123 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3126 u32 rar_entries = hw->mac.num_rar_entries;
3128 /* Make sure we are using a valid rar index range */
3129 if (rar >= rar_entries) {
3130 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
3131 return IXGBE_ERR_INVALID_ARGUMENT;
3135 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3137 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3139 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3140 mpsar |= 1 << (vmdq - 32);
3141 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3147 * This function should only be involved in the IOV mode.
3148 * In IOV mode, Default pool is next pool after the number of
3149 * VFs advertized and not 0.
3150 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3152 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3153 * @hw: pointer to hardware struct
3154 * @vmdq: VMDq pool index
3156 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3159 u32 rar = hw->mac.san_mac_rar_index;
3162 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3164 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3166 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3167 mpsar |= 1 << (vmdq - 32);
3168 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3175 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3176 * @hw: pointer to hardware structure
3178 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3182 hw_dbg(hw, " Clearing UTA\n");
3184 for (i = 0; i < 128; i++)
3185 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3191 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3192 * @hw: pointer to hardware structure
3193 * @vlan: VLAN id to write to VLAN filter
3195 * return the VLVF index where this VLAN id should be placed
3198 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
3201 u32 first_empty_slot = 0;
3204 /* short cut the special case */
3209 * Search for the vlan id in the VLVF entries. Save off the first empty
3210 * slot found along the way
3212 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
3213 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3214 if (!bits && !(first_empty_slot))
3215 first_empty_slot = regindex;
3216 else if ((bits & 0x0FFF) == vlan)
3221 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
3222 * in the VLVF. Else use the first empty VLVF register for this
3225 if (regindex >= IXGBE_VLVF_ENTRIES) {
3226 if (first_empty_slot)
3227 regindex = first_empty_slot;
3229 hw_dbg(hw, "No space in VLVF.\n");
3230 regindex = IXGBE_ERR_NO_SPACE;
3238 * ixgbe_set_vfta_generic - Set VLAN filter table
3239 * @hw: pointer to hardware structure
3240 * @vlan: VLAN id to write to VLAN filter
3241 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3242 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3244 * Turn on/off specified VLAN in the VLAN filter table.
3246 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3254 bool vfta_changed = false;
3257 return IXGBE_ERR_PARAM;
3260 * this is a 2 part operation - first the VFTA, then the
3261 * VLVF and VLVFB if VT Mode is set
3262 * We don't write the VFTA until we know the VLVF part succeeded.
3266 * The VFTA is a bitstring made up of 128 32-bit registers
3267 * that enable the particular VLAN id, much like the MTA:
3268 * bits[11-5]: which register
3269 * bits[4-0]: which bit in the register
3271 regindex = (vlan >> 5) & 0x7F;
3272 bitindex = vlan & 0x1F;
3273 targetbit = (1 << bitindex);
3274 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
3277 if (!(vfta & targetbit)) {
3279 vfta_changed = true;
3282 if ((vfta & targetbit)) {
3284 vfta_changed = true;
3289 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
3291 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on,
3297 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3303 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
3304 * @hw: pointer to hardware structure
3305 * @vlan: VLAN id to write to VLAN filter
3306 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3307 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3308 * @vfta_changed: pointer to boolean flag which indicates whether VFTA
3311 * Turn on/off specified bit in VLVF table.
3313 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3314 bool vlan_on, bool *vfta_changed)
3319 return IXGBE_ERR_PARAM;
3321 /* If VT Mode is set
3323 * make sure the vlan is in VLVF
3324 * set the vind bit in the matching VLVFB
3326 * clear the pool bit and possibly the vind
3328 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3329 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3333 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3338 /* set the pool bit */
3340 bits = IXGBE_READ_REG(hw,
3341 IXGBE_VLVFB(vlvf_index * 2));
3342 bits |= (1 << vind);
3344 IXGBE_VLVFB(vlvf_index * 2),
3347 bits = IXGBE_READ_REG(hw,
3348 IXGBE_VLVFB((vlvf_index * 2) + 1));
3349 bits |= (1 << (vind - 32));
3351 IXGBE_VLVFB((vlvf_index * 2) + 1),
3355 /* clear the pool bit */
3357 bits = IXGBE_READ_REG(hw,
3358 IXGBE_VLVFB(vlvf_index * 2));
3359 bits &= ~(1 << vind);
3361 IXGBE_VLVFB(vlvf_index * 2),
3363 bits |= IXGBE_READ_REG(hw,
3364 IXGBE_VLVFB((vlvf_index * 2) + 1));
3366 bits = IXGBE_READ_REG(hw,
3367 IXGBE_VLVFB((vlvf_index * 2) + 1));
3368 bits &= ~(1 << (vind - 32));
3370 IXGBE_VLVFB((vlvf_index * 2) + 1),
3372 bits |= IXGBE_READ_REG(hw,
3373 IXGBE_VLVFB(vlvf_index * 2));
3378 * If there are still bits set in the VLVFB registers
3379 * for the VLAN ID indicated we need to see if the
3380 * caller is requesting that we clear the VFTA entry bit.
3381 * If the caller has requested that we clear the VFTA
3382 * entry bit but there are still pools/VFs using this VLAN
3383 * ID entry then ignore the request. We're not worried
3384 * about the case where we're turning the VFTA VLAN ID
3385 * entry bit on, only when requested to turn it off as
3386 * there may be multiple pools and/or VFs using the
3387 * VLAN ID entry. In that case we cannot clear the
3388 * VFTA bit until all pools/VFs using that VLAN ID have also
3389 * been cleared. This will be indicated by "bits" being
3393 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3394 (IXGBE_VLVF_VIEN | vlan));
3395 if ((!vlan_on) && (vfta_changed != NULL)) {
3396 /* someone wants to clear the vfta entry
3397 * but some pools/VFs are still using it.
3399 *vfta_changed = false;
3402 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
3409 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3410 * @hw: pointer to hardware structure
3412 * Clears the VLAN filer table, and the VMDq index associated with the filter
3414 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
3418 for (offset = 0; offset < hw->mac.vft_size; offset++)
3419 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
3421 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
3422 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
3423 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
3424 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
3431 * ixgbe_check_mac_link_generic - Determine link and speed status
3432 * @hw: pointer to hardware structure
3433 * @speed: pointer to link speed
3434 * @link_up: true when link is up
3435 * @link_up_wait_to_complete: bool used to wait for link up or not
3437 * Reads the links register to determine if link is up and the current speed
3439 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3440 bool *link_up, bool link_up_wait_to_complete)
3442 u32 links_reg, links_orig;
3445 /* clear the old state */
3446 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
3448 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3450 if (links_orig != links_reg) {
3451 hw_dbg(hw, "LINKS changed from %08X to %08X\n",
3452 links_orig, links_reg);
3455 if (link_up_wait_to_complete) {
3456 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
3457 if (links_reg & IXGBE_LINKS_UP) {
3464 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3467 if (links_reg & IXGBE_LINKS_UP)
3473 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3474 IXGBE_LINKS_SPEED_10G_82599)
3475 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3476 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3477 IXGBE_LINKS_SPEED_1G_82599)
3478 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3479 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3480 IXGBE_LINKS_SPEED_100_82599)
3481 *speed = IXGBE_LINK_SPEED_100_FULL;
3483 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3489 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
3491 * @hw: pointer to hardware structure
3492 * @wwnn_prefix: the alternative WWNN prefix
3493 * @wwpn_prefix: the alternative WWPN prefix
3495 * This function will read the EEPROM from the alternative SAN MAC address
3496 * block to check the support for the alternative WWNN/WWPN prefix support.
3498 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
3502 u16 alt_san_mac_blk_offset;
3504 /* clear output first */
3505 *wwnn_prefix = 0xFFFF;
3506 *wwpn_prefix = 0xFFFF;
3508 /* check if alternative SAN MAC is supported */
3509 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
3510 &alt_san_mac_blk_offset);
3512 if ((alt_san_mac_blk_offset == 0) ||
3513 (alt_san_mac_blk_offset == 0xFFFF))
3514 goto wwn_prefix_out;
3516 /* check capability in alternative san mac address block */
3517 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
3518 hw->eeprom.ops.read(hw, offset, &caps);
3519 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
3520 goto wwn_prefix_out;
3522 /* get the corresponding prefix for WWNN/WWPN */
3523 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
3524 hw->eeprom.ops.read(hw, offset, wwnn_prefix);
3526 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
3527 hw->eeprom.ops.read(hw, offset, wwpn_prefix);
3534 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
3535 * @hw: pointer to hardware structure
3536 * @bs: the fcoe boot status
3538 * This function will read the FCOE boot status from the iSCSI FCOE block
3540 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
3542 u16 offset, caps, flags;
3545 /* clear output first */
3546 *bs = ixgbe_fcoe_bootstatus_unavailable;
3548 /* check if FCOE IBA block is present */
3549 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
3550 status = hw->eeprom.ops.read(hw, offset, &caps);
3554 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
3557 /* check if iSCSI FCOE block is populated */
3558 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
3562 if ((offset == 0) || (offset == 0xFFFF))
3565 /* read fcoe flags in iSCSI FCOE block */
3566 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
3567 status = hw->eeprom.ops.read(hw, offset, &flags);
3571 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
3572 *bs = ixgbe_fcoe_bootstatus_enabled;
3574 *bs = ixgbe_fcoe_bootstatus_disabled;
3581 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
3582 * @hw: pointer to hardware structure
3583 * @enable: enable or disable switch for anti-spoofing
3584 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
3587 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
3590 int pf_target_reg = pf >> 3;
3591 int pf_target_shift = pf % 8;
3594 if (hw->mac.type == ixgbe_mac_82598EB)
3598 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
3601 * PFVFSPOOF register array is size 8 with 8 bits assigned to
3602 * MAC anti-spoof enables in each register array element.
3604 for (j = 0; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
3605 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3607 /* If not enabling anti-spoofing then done */
3612 * The PF should be allowed to spoof so that it can support
3613 * emulation mode NICs. Reset the bit assigned to the PF
3615 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg));
3616 pfvfspoof ^= (1 << pf_target_shift);
3617 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg), pfvfspoof);
3621 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
3622 * @hw: pointer to hardware structure
3623 * @enable: enable or disable switch for VLAN anti-spoofing
3624 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
3627 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3629 int vf_target_reg = vf >> 3;
3630 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
3633 if (hw->mac.type == ixgbe_mac_82598EB)
3636 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3638 pfvfspoof |= (1 << vf_target_shift);
3640 pfvfspoof &= ~(1 << vf_target_shift);
3641 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3645 * ixgbe_get_device_caps_generic - Get additional device capabilities
3646 * @hw: pointer to hardware structure
3647 * @device_caps: the EEPROM word with the extra device capabilities
3649 * This function will read the EEPROM location for the device capabilities,
3650 * and return the word through device_caps.
3652 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
3654 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
3660 * ixgbe_calculate_checksum - Calculate checksum for buffer
3661 * @buffer: pointer to EEPROM
3662 * @length: size of EEPROM to calculate a checksum for
3663 * Calculates the checksum for some buffer on a specified length. The
3664 * checksum calculated is returned.
3666 static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
3673 for (i = 0; i < length; i++)
3676 return (u8) (0 - sum);
3680 * ixgbe_host_interface_command - Issue command to manageability block
3681 * @hw: pointer to the HW structure
3682 * @buffer: contains the command to write and where the return status will
3684 * @length: length of buffer, must be multiple of 4 bytes
3686 * Communicates with the manageability block. On success return 0
3687 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
3689 static s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
3693 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
3694 u8 buf_len, dword_len;
3698 if (length == 0 || length & 0x3 ||
3699 length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
3700 hw_dbg(hw, "Buffer length failure.\n");
3701 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3705 /* Check that the host interface is enabled. */
3706 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3707 if ((hicr & IXGBE_HICR_EN) == 0) {
3708 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n");
3709 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3713 /* Calculate length in DWORDs */
3714 dword_len = length >> 2;
3717 * The device driver writes the relevant command block
3718 * into the ram area.
3720 for (i = 0; i < dword_len; i++)
3721 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3722 i, IXGBE_CPU_TO_LE32(buffer[i]));
3724 /* Setting this bit tells the ARC that a new command is pending. */
3725 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
3727 for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {
3728 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3729 if (!(hicr & IXGBE_HICR_C))
3734 /* Check command successful completion. */
3735 if (i == IXGBE_HI_COMMAND_TIMEOUT ||
3736 (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
3737 hw_dbg(hw, "Command has failed with no status valid.\n");
3738 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3742 /* Calculate length in DWORDs */
3743 dword_len = hdr_size >> 2;
3745 /* first pull in the header so we know the buffer length */
3746 for (bi = 0; bi < dword_len; bi++) {
3747 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3748 IXGBE_LE32_TO_CPUS(&buffer[bi]);
3751 /* If there is any thing in data position pull it in */
3752 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
3756 if (length < (buf_len + hdr_size)) {
3757 hw_dbg(hw, "Buffer not large enough for reply message.\n");
3758 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3762 /* Calculate length in DWORDs, add 3 for odd lengths */
3763 dword_len = (buf_len + 3) >> 2;
3765 /* Pull in the rest of the buffer (bi is where we left off)*/
3766 for (; bi <= dword_len; bi++) {
3767 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3768 IXGBE_LE32_TO_CPUS(&buffer[bi]);
3776 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
3777 * @hw: pointer to the HW structure
3778 * @maj: driver version major number
3779 * @min: driver version minor number
3780 * @build: driver version build number
3781 * @sub: driver version sub build number
3783 * Sends driver version number to firmware through the manageability
3784 * block. On success return 0
3785 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
3786 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
3788 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
3791 struct ixgbe_hic_drv_info fw_cmd;
3795 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM)
3797 ret_val = IXGBE_ERR_SWFW_SYNC;
3801 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
3802 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
3803 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
3804 fw_cmd.port_num = (u8)hw->bus.func;
3805 fw_cmd.ver_maj = maj;
3806 fw_cmd.ver_min = min;
3807 fw_cmd.ver_build = build;
3808 fw_cmd.ver_sub = sub;
3809 fw_cmd.hdr.checksum = 0;
3810 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
3811 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
3815 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
3816 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3821 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
3822 FW_CEM_RESP_STATUS_SUCCESS)
3825 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3830 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
3836 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
3837 * @hw: pointer to hardware structure
3838 * @num_pb: number of packet buffers to allocate
3839 * @headroom: reserve n KB of headroom
3840 * @strategy: packet buffer allocation strategy
3842 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
3845 u32 pbsize = hw->mac.rx_pb_size;
3847 u32 rxpktsize, txpktsize, txpbthresh;
3849 /* Reserve headroom */
3855 /* Divide remaining packet buffer space amongst the number of packet
3856 * buffers requested using supplied strategy.
3859 case PBA_STRATEGY_WEIGHTED:
3860 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
3861 * buffer with 5/8 of the packet buffer space.
3863 rxpktsize = (pbsize * 5) / (num_pb * 4);
3864 pbsize -= rxpktsize * (num_pb / 2);
3865 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
3866 for (; i < (num_pb / 2); i++)
3867 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3868 /* Fall through to configure remaining packet buffers */
3869 case PBA_STRATEGY_EQUAL:
3870 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
3871 for (; i < num_pb; i++)
3872 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3878 /* Only support an equally distributed Tx packet buffer strategy. */
3879 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
3880 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
3881 for (i = 0; i < num_pb; i++) {
3882 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3883 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3886 /* Clear unused TCs, if any, to zero buffer size*/
3887 for (; i < IXGBE_MAX_PB; i++) {
3888 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3889 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3890 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3895 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
3896 * @hw: pointer to the hardware structure
3898 * The 82599 and x540 MACs can experience issues if TX work is still pending
3899 * when a reset occurs. This function prevents this by flushing the PCIe
3900 * buffers on the system.
3902 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
3904 u32 gcr_ext, hlreg0;
3907 * If double reset is not requested then all transactions should
3908 * already be clear and as such there is no work to do
3910 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
3914 * Set loopback enable to prevent any transmits from being sent
3915 * should the link come up. This assumes that the RXCTRL.RXEN bit
3916 * has already been cleared.
3918 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3919 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
3921 /* initiate cleaning flow for buffers in the PCIe transaction layer */
3922 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3923 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
3924 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
3926 /* Flush all writes and allow 20usec for all transactions to clear */
3927 IXGBE_WRITE_FLUSH(hw);
3930 /* restore previous register values */
3931 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3932 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3935 static const u8 ixgbe_emc_temp_data[4] = {
3936 IXGBE_EMC_INTERNAL_DATA,
3937 IXGBE_EMC_DIODE1_DATA,
3938 IXGBE_EMC_DIODE2_DATA,
3939 IXGBE_EMC_DIODE3_DATA
3941 static const u8 ixgbe_emc_therm_limit[4] = {
3942 IXGBE_EMC_INTERNAL_THERM_LIMIT,
3943 IXGBE_EMC_DIODE1_THERM_LIMIT,
3944 IXGBE_EMC_DIODE2_THERM_LIMIT,
3945 IXGBE_EMC_DIODE3_THERM_LIMIT
3949 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
3950 * @hw: pointer to hardware structure
3951 * @data: pointer to the thermal sensor data structure
3953 * Returns the thermal sensor data structure
3955 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
3965 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3967 /* Only support thermal sensors attached to 82599 physical port 0 */
3968 if ((hw->mac.type != ixgbe_mac_82599EB) ||
3969 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
3970 status = IXGBE_NOT_IMPLEMENTED;
3974 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset);
3978 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) {
3979 status = IXGBE_NOT_IMPLEMENTED;
3983 status = hw->eeprom.ops.read(hw, ets_offset, &ets_cfg);
3987 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
3988 != IXGBE_ETS_TYPE_EMC) {
3989 status = IXGBE_NOT_IMPLEMENTED;
3993 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3994 if (num_sensors > IXGBE_MAX_SENSORS)
3995 num_sensors = IXGBE_MAX_SENSORS;
3997 for (i = 0; i < num_sensors; i++) {
3998 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
4003 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4004 IXGBE_ETS_DATA_INDEX_SHIFT);
4005 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4006 IXGBE_ETS_DATA_LOC_SHIFT);
4008 if (sensor_location != 0) {
4009 status = hw->phy.ops.read_i2c_byte(hw,
4010 ixgbe_emc_temp_data[sensor_index],
4011 IXGBE_I2C_THERMAL_SENSOR_ADDR,
4012 &data->sensor[i].temp);
4022 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
4023 * @hw: pointer to hardware structure
4025 * Inits the thermal sensor thresholds according to the NVM map
4026 * and save off the threshold and location values into mac.thermal_sensor_data
4028 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
4034 u8 low_thresh_delta;
4040 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4042 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
4044 /* Only support thermal sensors attached to 82599 physical port 0 */
4045 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4046 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
4047 return IXGBE_NOT_IMPLEMENTED;
4049 hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset);
4050 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
4051 return IXGBE_NOT_IMPLEMENTED;
4053 hw->eeprom.ops.read(hw, ets_offset, &ets_cfg);
4054 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4055 != IXGBE_ETS_TYPE_EMC)
4056 return IXGBE_NOT_IMPLEMENTED;
4058 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
4059 IXGBE_ETS_LTHRES_DELTA_SHIFT);
4060 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4062 for (i = 0; i < num_sensors; i++) {
4063 hw->eeprom.ops.read(hw, (ets_offset + 1 + i), &ets_sensor);
4064 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4065 IXGBE_ETS_DATA_INDEX_SHIFT);
4066 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4067 IXGBE_ETS_DATA_LOC_SHIFT);
4068 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
4070 hw->phy.ops.write_i2c_byte(hw,
4071 ixgbe_emc_therm_limit[sensor_index],
4072 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
4074 if ((i < IXGBE_MAX_SENSORS) && (sensor_location != 0)) {
4075 data->sensor[i].location = sensor_location;
4076 data->sensor[i].caution_thresh = therm_limit;
4077 data->sensor[i].max_op_thresh = therm_limit -