1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*******************************************************************************
4 Intel 10 Gigabit PCI Express Linux driver
5 Copyright(c) 1999 - 2012 Intel Corporation.
8 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
9 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
11 *******************************************************************************/
14 /* glue for the OS independent part of ixgbe
15 * includes register access macros
18 #ifndef _IXGBE_OSDEP_H_
19 #define _IXGBE_OSDEP_H_
21 #include <linux/pci.h>
22 #include <linux/delay.h>
23 #include <linux/interrupt.h>
24 #include <linux/if_ether.h>
25 #include <linux/sched.h>
30 #define msleep(x) do { if (in_interrupt()) { \
31 /* Don't mdelay in interrupt context! */ \
42 #define hw_dbg(hw, S, A...) printk(KERN_DEBUG S, ## A)
44 #define hw_dbg(hw, S, A...) do {} while (0)
47 #define e_dev_info(format, arg...) \
48 dev_info(pci_dev_to_dev(adapter->pdev), format, ## arg)
49 #define e_dev_warn(format, arg...) \
50 dev_warn(pci_dev_to_dev(adapter->pdev), format, ## arg)
51 #define e_dev_err(format, arg...) \
52 dev_err(pci_dev_to_dev(adapter->pdev), format, ## arg)
53 #define e_dev_notice(format, arg...) \
54 dev_notice(pci_dev_to_dev(adapter->pdev), format, ## arg)
55 #define e_info(msglvl, format, arg...) \
56 netif_info(adapter, msglvl, adapter->netdev, format, ## arg)
57 #define e_err(msglvl, format, arg...) \
58 netif_err(adapter, msglvl, adapter->netdev, format, ## arg)
59 #define e_warn(msglvl, format, arg...) \
60 netif_warn(adapter, msglvl, adapter->netdev, format, ## arg)
61 #define e_crit(msglvl, format, arg...) \
62 netif_crit(adapter, msglvl, adapter->netdev, format, ## arg)
66 #define IXGBE_WRITE_REG(a, reg, value) do {\
74 printk("%s: Reg - 0x%05X, value - 0x%08X\n", __func__, \
79 writel((value), ((a)->hw_addr + (reg))); \
82 #define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
85 #define IXGBE_READ_REG(a, reg) readl((a)->hw_addr + (reg))
87 #define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) ( \
88 writel((value), ((a)->hw_addr + (reg) + ((offset) << 2))))
90 #define IXGBE_READ_REG_ARRAY(a, reg, offset) ( \
91 readl((a)->hw_addr + (reg) + ((offset) << 2)))
94 #define writeq(val, addr) do { writel((u32) (val), addr); \
95 writel((u32) (val >> 32), (addr + 4)); \
99 #define IXGBE_WRITE_REG64(a, reg, value) writeq((value), ((a)->hw_addr + (reg)))
101 #define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS)
103 extern u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg);
104 extern void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value);
105 extern void ewarn(struct ixgbe_hw *hw, const char *str, u32 status);
107 #define IXGBE_READ_PCIE_WORD ixgbe_read_pci_cfg_word
108 #define IXGBE_WRITE_PCIE_WORD ixgbe_write_pci_cfg_word
109 #define IXGBE_EEPROM_GRANT_ATTEMPS 100
110 #define IXGBE_HTONL(_i) htonl(_i)
111 #define IXGBE_NTOHL(_i) ntohl(_i)
112 #define IXGBE_NTOHS(_i) ntohs(_i)
113 #define IXGBE_CPU_TO_LE32(_i) cpu_to_le32(_i)
114 #define IXGBE_LE32_TO_CPUS(_i) le32_to_cpus(_i)
115 #define EWARN(H, W, S) ewarn(H, W, S)
117 #endif /* _IXGBE_OSDEP_H_ */