1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
29 /* glue for the OS independent part of ixgbe
30 * includes register access macros
33 #ifndef _IXGBE_OSDEP_H_
34 #define _IXGBE_OSDEP_H_
36 #include <linux/pci.h>
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/if_ether.h>
40 #include <linux/sched.h>
45 #define msleep(x) do { if (in_interrupt()) { \
46 /* Don't mdelay in interrupt context! */ \
57 #define hw_dbg(hw, S, A...) printk(KERN_DEBUG S, ## A)
59 #define hw_dbg(hw, S, A...) do {} while (0)
62 #define e_dev_info(format, arg...) \
63 dev_info(pci_dev_to_dev(adapter->pdev), format, ## arg)
64 #define e_dev_warn(format, arg...) \
65 dev_warn(pci_dev_to_dev(adapter->pdev), format, ## arg)
66 #define e_dev_err(format, arg...) \
67 dev_err(pci_dev_to_dev(adapter->pdev), format, ## arg)
68 #define e_dev_notice(format, arg...) \
69 dev_notice(pci_dev_to_dev(adapter->pdev), format, ## arg)
70 #define e_info(msglvl, format, arg...) \
71 netif_info(adapter, msglvl, adapter->netdev, format, ## arg)
72 #define e_err(msglvl, format, arg...) \
73 netif_err(adapter, msglvl, adapter->netdev, format, ## arg)
74 #define e_warn(msglvl, format, arg...) \
75 netif_warn(adapter, msglvl, adapter->netdev, format, ## arg)
76 #define e_crit(msglvl, format, arg...) \
77 netif_crit(adapter, msglvl, adapter->netdev, format, ## arg)
81 #define IXGBE_WRITE_REG(a, reg, value) do {\
89 printk("%s: Reg - 0x%05X, value - 0x%08X\n", __func__, \
94 writel((value), ((a)->hw_addr + (reg))); \
97 #define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
100 #define IXGBE_READ_REG(a, reg) readl((a)->hw_addr + (reg))
102 #define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) ( \
103 writel((value), ((a)->hw_addr + (reg) + ((offset) << 2))))
105 #define IXGBE_READ_REG_ARRAY(a, reg, offset) ( \
106 readl((a)->hw_addr + (reg) + ((offset) << 2)))
109 #define writeq(val, addr) do { writel((u32) (val), addr); \
110 writel((u32) (val >> 32), (addr + 4)); \
114 #define IXGBE_WRITE_REG64(a, reg, value) writeq((value), ((a)->hw_addr + (reg)))
116 #define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS)
118 extern u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg);
119 extern void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value);
120 extern void ewarn(struct ixgbe_hw *hw, const char *str, u32 status);
122 #define IXGBE_READ_PCIE_WORD ixgbe_read_pci_cfg_word
123 #define IXGBE_WRITE_PCIE_WORD ixgbe_write_pci_cfg_word
124 #define IXGBE_EEPROM_GRANT_ATTEMPS 100
125 #define IXGBE_HTONL(_i) htonl(_i)
126 #define IXGBE_NTOHL(_i) ntohl(_i)
127 #define IXGBE_NTOHS(_i) ntohs(_i)
128 #define IXGBE_CPU_TO_LE32(_i) cpu_to_le32(_i)
129 #define IXGBE_LE32_TO_CPUS(_i) le32_to_cpus(_i)
130 #define EWARN(H, W, S) ewarn(H, W, S)
132 #endif /* _IXGBE_OSDEP_H_ */