1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "LICENSE.GPL".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include "ixgbe_api.h"
29 #include "ixgbe_common.h"
30 #include "ixgbe_phy.h"
32 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
33 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
34 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
35 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
36 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
37 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
38 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
39 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
40 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
41 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
42 static bool ixgbe_get_i2c_data(u32 *i2cctl);
45 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
46 * @hw: pointer to the hardware structure
48 * Initialize the function pointers.
50 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
52 struct ixgbe_phy_info *phy = &hw->phy;
55 phy->ops.identify = &ixgbe_identify_phy_generic;
56 phy->ops.reset = &ixgbe_reset_phy_generic;
57 phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
58 phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
59 phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
60 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
61 phy->ops.check_link = NULL;
62 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
63 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
64 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
65 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
66 phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
67 phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
68 phy->ops.identify_sfp = &ixgbe_identify_module_generic;
69 phy->sfp_type = ixgbe_sfp_type_unknown;
70 phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
75 * ixgbe_identify_phy_generic - Get physical layer module
76 * @hw: pointer to hardware structure
78 * Determines the physical layer module found on the current adapter.
80 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
82 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
86 if (hw->phy.type == ixgbe_phy_unknown) {
87 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
88 if (ixgbe_validate_phy_addr(hw, phy_addr)) {
89 hw->phy.addr = phy_addr;
92 ixgbe_get_phy_type_from_id(hw->phy.id);
94 if (hw->phy.type == ixgbe_phy_unknown) {
95 hw->phy.ops.read_reg(hw,
96 IXGBE_MDIO_PHY_EXT_ABILITY,
97 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
100 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
101 IXGBE_MDIO_PHY_1000BASET_ABILITY))
103 ixgbe_phy_cu_unknown;
113 /* clear value if nothing found */
124 * ixgbe_validate_phy_addr - Determines phy address is valid
125 * @hw: pointer to hardware structure
128 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
133 hw->phy.addr = phy_addr;
134 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
135 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
137 if (phy_id != 0xFFFF && phy_id != 0x0)
144 * ixgbe_get_phy_id - Get the phy type
145 * @hw: pointer to hardware structure
148 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
154 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
155 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
159 hw->phy.id = (u32)(phy_id_high << 16);
160 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
161 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
163 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
164 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
170 * ixgbe_get_phy_type_from_id - Get the phy type
171 * @hw: pointer to hardware structure
174 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
176 enum ixgbe_phy_type phy_type;
180 phy_type = ixgbe_phy_tn;
183 phy_type = ixgbe_phy_aq;
186 phy_type = ixgbe_phy_qt;
189 phy_type = ixgbe_phy_nl;
192 phy_type = ixgbe_phy_unknown;
196 hw_dbg(hw, "phy type found is %d\n", phy_type);
201 * ixgbe_reset_phy_generic - Performs a PHY reset
202 * @hw: pointer to hardware structure
204 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
210 if (hw->phy.type == ixgbe_phy_unknown)
211 status = ixgbe_identify_phy_generic(hw);
213 if (status != 0 || hw->phy.type == ixgbe_phy_none)
216 /* Don't reset PHY if it's shut down due to overtemp. */
217 if (!hw->phy.reset_if_overtemp &&
218 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
222 * Perform soft PHY reset to the PHY_XS.
223 * This will cause a soft reset to the PHY
225 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
226 IXGBE_MDIO_PHY_XS_DEV_TYPE,
227 IXGBE_MDIO_PHY_XS_RESET);
230 * Poll for reset bit to self-clear indicating reset is complete.
231 * Some PHYs could take up to 3 seconds to complete and need about
232 * 1.7 usec delay after the reset is complete.
234 for (i = 0; i < 30; i++) {
236 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
237 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
238 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
244 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
245 status = IXGBE_ERR_RESET_FAILED;
246 hw_dbg(hw, "PHY reset polling failed to complete.\n");
254 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
255 * @hw: pointer to hardware structure
256 * @reg_addr: 32 bit address of PHY register to read
257 * @phy_data: Pointer to read data from PHY register
259 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
260 u32 device_type, u16 *phy_data)
268 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
269 gssr = IXGBE_GSSR_PHY1_SM;
271 gssr = IXGBE_GSSR_PHY0_SM;
273 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
274 status = IXGBE_ERR_SWFW_SYNC;
277 /* Setup and write the address cycle command */
278 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
279 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
280 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
281 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
283 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
286 * Check every 10 usec to see if the address cycle completed.
287 * The MDI Command bit will clear when the operation is
290 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
293 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
295 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
299 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
300 hw_dbg(hw, "PHY address command did not complete.\n");
301 status = IXGBE_ERR_PHY;
306 * Address cycle complete, setup and write the read
309 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
310 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
311 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
312 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
314 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
317 * Check every 10 usec to see if the address cycle
318 * completed. The MDI Command bit will clear when the
319 * operation is complete
321 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
324 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
326 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
330 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
331 hw_dbg(hw, "PHY read command didn't complete\n");
332 status = IXGBE_ERR_PHY;
335 * Read operation is complete. Get the data
338 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
339 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
340 *phy_data = (u16)(data);
344 hw->mac.ops.release_swfw_sync(hw, gssr);
351 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
352 * @hw: pointer to hardware structure
353 * @reg_addr: 32 bit PHY register to write
354 * @device_type: 5 bit device type
355 * @phy_data: Data to write to the PHY register
357 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
358 u32 device_type, u16 phy_data)
365 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
366 gssr = IXGBE_GSSR_PHY1_SM;
368 gssr = IXGBE_GSSR_PHY0_SM;
370 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
371 status = IXGBE_ERR_SWFW_SYNC;
374 /* Put the data in the MDI single read and write data register*/
375 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
377 /* Setup and write the address cycle command */
378 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
379 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
380 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
381 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
383 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
386 * Check every 10 usec to see if the address cycle completed.
387 * The MDI Command bit will clear when the operation is
390 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
393 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
395 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
399 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
400 hw_dbg(hw, "PHY address cmd didn't complete\n");
401 status = IXGBE_ERR_PHY;
406 * Address cycle complete, setup and write the write
409 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
410 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
411 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
412 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
414 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
417 * Check every 10 usec to see if the address cycle
418 * completed. The MDI Command bit will clear when the
419 * operation is complete
421 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
424 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
426 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
430 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
431 hw_dbg(hw, "PHY address cmd didn't complete\n");
432 status = IXGBE_ERR_PHY;
436 hw->mac.ops.release_swfw_sync(hw, gssr);
443 * ixgbe_setup_phy_link_generic - Set and restart autoneg
444 * @hw: pointer to hardware structure
446 * Restart autonegotiation and PHY and waits for completion.
448 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
452 u32 max_time_out = 10;
453 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
454 bool autoneg = false;
455 ixgbe_link_speed speed;
457 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
459 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
460 /* Set or unset auto-negotiation 10G advertisement */
461 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
462 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
465 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
466 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
467 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
469 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
470 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
474 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
475 /* Set or unset auto-negotiation 1G advertisement */
476 hw->phy.ops.read_reg(hw,
477 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
478 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
481 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
482 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
483 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
485 hw->phy.ops.write_reg(hw,
486 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
487 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
491 if (speed & IXGBE_LINK_SPEED_100_FULL) {
492 /* Set or unset auto-negotiation 100M advertisement */
493 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
494 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
497 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
498 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
499 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
500 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
502 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
503 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
507 /* Restart PHY autonegotiation and wait for completion */
508 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
509 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
511 autoneg_reg |= IXGBE_MII_RESTART;
513 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
514 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
516 /* Wait for autonegotiation to finish */
517 for (time_out = 0; time_out < max_time_out; time_out++) {
519 /* Restart PHY autonegotiation and wait for completion */
520 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
521 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
524 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
525 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
529 if (time_out == max_time_out) {
530 status = IXGBE_ERR_LINK_SETUP;
531 hw_dbg(hw, "ixgbe_setup_phy_link_generic: time out");
538 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
539 * @hw: pointer to hardware structure
540 * @speed: new link speed
541 * @autoneg: true if autonegotiation enabled
543 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
544 ixgbe_link_speed speed,
546 bool autoneg_wait_to_complete)
550 * Clear autoneg_advertised and set new values based on input link
553 hw->phy.autoneg_advertised = 0;
555 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
556 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
558 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
559 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
561 if (speed & IXGBE_LINK_SPEED_100_FULL)
562 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
564 /* Setup link based on the new speed settings */
565 hw->phy.ops.setup_link(hw);
571 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
572 * @hw: pointer to hardware structure
573 * @speed: pointer to link speed
574 * @autoneg: boolean auto-negotiation value
576 * Determines the link capabilities by reading the AUTOC register.
578 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
579 ixgbe_link_speed *speed,
582 s32 status = IXGBE_ERR_LINK_SETUP;
588 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
589 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
593 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
594 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
595 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
596 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
597 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
598 *speed |= IXGBE_LINK_SPEED_100_FULL;
605 * ixgbe_check_phy_link_tnx - Determine link and speed status
606 * @hw: pointer to hardware structure
608 * Reads the VS1 register to determine if link is up and the current speed for
611 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
616 u32 max_time_out = 10;
621 /* Initialize speed and link to default case */
623 *speed = IXGBE_LINK_SPEED_10GB_FULL;
626 * Check current speed and link status of the PHY register.
627 * This is a vendor specific register and may have to
628 * be changed for other copper PHYs.
630 for (time_out = 0; time_out < max_time_out; time_out++) {
632 status = hw->phy.ops.read_reg(hw,
633 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
634 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
636 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
637 phy_speed = phy_data &
638 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
639 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
642 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
643 *speed = IXGBE_LINK_SPEED_1GB_FULL;
652 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
653 * @hw: pointer to hardware structure
655 * Restart autonegotiation and PHY and waits for completion.
657 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
661 u32 max_time_out = 10;
662 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
663 bool autoneg = false;
664 ixgbe_link_speed speed;
666 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
668 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
669 /* Set or unset auto-negotiation 10G advertisement */
670 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
671 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
674 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
675 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
676 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
678 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
679 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
683 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
684 /* Set or unset auto-negotiation 1G advertisement */
685 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
686 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
689 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
690 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
691 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
693 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
694 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
698 if (speed & IXGBE_LINK_SPEED_100_FULL) {
699 /* Set or unset auto-negotiation 100M advertisement */
700 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
701 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
704 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
705 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
706 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
708 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
709 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
713 /* Restart PHY autonegotiation and wait for completion */
714 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
715 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
717 autoneg_reg |= IXGBE_MII_RESTART;
719 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
720 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
722 /* Wait for autonegotiation to finish */
723 for (time_out = 0; time_out < max_time_out; time_out++) {
725 /* Restart PHY autonegotiation and wait for completion */
726 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
727 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
730 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
731 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
735 if (time_out == max_time_out) {
736 status = IXGBE_ERR_LINK_SETUP;
737 hw_dbg(hw, "ixgbe_setup_phy_link_tnx: time out");
744 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
745 * @hw: pointer to hardware structure
746 * @firmware_version: pointer to the PHY Firmware Version
748 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
749 u16 *firmware_version)
753 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
754 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
761 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
762 * @hw: pointer to hardware structure
763 * @firmware_version: pointer to the PHY Firmware Version
765 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
766 u16 *firmware_version)
770 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
771 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
778 * ixgbe_reset_phy_nl - Performs a PHY reset
779 * @hw: pointer to hardware structure
781 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
783 u16 phy_offset, control, eword, edata, block_crc;
784 bool end_data = false;
785 u16 list_offset, data_offset;
790 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
791 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
793 /* reset the PHY and poll for completion */
794 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
795 IXGBE_MDIO_PHY_XS_DEV_TYPE,
796 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
798 for (i = 0; i < 100; i++) {
799 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
800 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
801 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
806 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
807 hw_dbg(hw, "PHY reset did not complete.\n");
808 ret_val = IXGBE_ERR_PHY;
812 /* Get init offsets */
813 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
818 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
822 * Read control word from PHY init contents offset
824 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
825 control = (eword & IXGBE_CONTROL_MASK_NL) >>
826 IXGBE_CONTROL_SHIFT_NL;
827 edata = eword & IXGBE_DATA_MASK_NL;
831 hw_dbg(hw, "DELAY: %d MS\n", edata);
835 hw_dbg(hw, "DATA:\n");
837 hw->eeprom.ops.read(hw, data_offset++,
839 for (i = 0; i < edata; i++) {
840 hw->eeprom.ops.read(hw, data_offset, &eword);
841 hw->phy.ops.write_reg(hw, phy_offset,
842 IXGBE_TWINAX_DEV, eword);
843 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
849 case IXGBE_CONTROL_NL:
851 hw_dbg(hw, "CONTROL:\n");
852 if (edata == IXGBE_CONTROL_EOL_NL) {
855 } else if (edata == IXGBE_CONTROL_SOL_NL) {
858 hw_dbg(hw, "Bad control value\n");
859 ret_val = IXGBE_ERR_PHY;
864 hw_dbg(hw, "Bad control type\n");
865 ret_val = IXGBE_ERR_PHY;
875 * ixgbe_identify_module_generic - Identifies module type
876 * @hw: pointer to hardware structure
878 * Determines HW type and calls appropriate function.
880 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
882 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
884 switch (hw->mac.ops.get_media_type(hw)) {
885 case ixgbe_media_type_fiber:
886 status = ixgbe_identify_sfp_module_generic(hw);
889 case ixgbe_media_type_fiber_qsfp:
890 status = ixgbe_identify_qsfp_module_generic(hw);
894 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
895 status = IXGBE_ERR_SFP_NOT_PRESENT;
903 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
904 * @hw: pointer to hardware structure
906 * Searches for and identifies the SFP module and assigns appropriate PHY type.
908 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
910 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
912 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
914 u8 comp_codes_1g = 0;
915 u8 comp_codes_10g = 0;
916 u8 oui_bytes[3] = {0, 0, 0};
921 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
922 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
923 status = IXGBE_ERR_SFP_NOT_PRESENT;
927 status = hw->phy.ops.read_i2c_eeprom(hw,
928 IXGBE_SFF_IDENTIFIER,
931 if (status == IXGBE_ERR_SWFW_SYNC ||
932 status == IXGBE_ERR_I2C ||
933 status == IXGBE_ERR_SFP_NOT_PRESENT)
934 goto err_read_i2c_eeprom;
936 /* LAN ID is needed for sfp_type determination */
937 hw->mac.ops.set_lan_id(hw);
939 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
940 hw->phy.type = ixgbe_phy_sfp_unsupported;
941 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
943 status = hw->phy.ops.read_i2c_eeprom(hw,
944 IXGBE_SFF_1GBE_COMP_CODES,
947 if (status == IXGBE_ERR_SWFW_SYNC ||
948 status == IXGBE_ERR_I2C ||
949 status == IXGBE_ERR_SFP_NOT_PRESENT)
950 goto err_read_i2c_eeprom;
952 status = hw->phy.ops.read_i2c_eeprom(hw,
953 IXGBE_SFF_10GBE_COMP_CODES,
956 if (status == IXGBE_ERR_SWFW_SYNC ||
957 status == IXGBE_ERR_I2C ||
958 status == IXGBE_ERR_SFP_NOT_PRESENT)
959 goto err_read_i2c_eeprom;
960 status = hw->phy.ops.read_i2c_eeprom(hw,
961 IXGBE_SFF_CABLE_TECHNOLOGY,
964 if (status == IXGBE_ERR_SWFW_SYNC ||
965 status == IXGBE_ERR_I2C ||
966 status == IXGBE_ERR_SFP_NOT_PRESENT)
967 goto err_read_i2c_eeprom;
974 * 3 SFP_DA_CORE0 - 82599-specific
975 * 4 SFP_DA_CORE1 - 82599-specific
976 * 5 SFP_SR/LR_CORE0 - 82599-specific
977 * 6 SFP_SR/LR_CORE1 - 82599-specific
978 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
979 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
980 * 9 SFP_1g_cu_CORE0 - 82599-specific
981 * 10 SFP_1g_cu_CORE1 - 82599-specific
982 * 11 SFP_1g_sx_CORE0 - 82599-specific
983 * 12 SFP_1g_sx_CORE1 - 82599-specific
985 if (hw->mac.type == ixgbe_mac_82598EB) {
986 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
987 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
988 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
989 hw->phy.sfp_type = ixgbe_sfp_type_sr;
990 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
991 hw->phy.sfp_type = ixgbe_sfp_type_lr;
993 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
994 } else if (hw->mac.type == ixgbe_mac_82599EB) {
995 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
996 if (hw->bus.lan_id == 0)
998 ixgbe_sfp_type_da_cu_core0;
1001 ixgbe_sfp_type_da_cu_core1;
1002 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1003 hw->phy.ops.read_i2c_eeprom(
1004 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1007 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1008 if (hw->bus.lan_id == 0)
1010 ixgbe_sfp_type_da_act_lmt_core0;
1013 ixgbe_sfp_type_da_act_lmt_core1;
1016 ixgbe_sfp_type_unknown;
1018 } else if (comp_codes_10g &
1019 (IXGBE_SFF_10GBASESR_CAPABLE |
1020 IXGBE_SFF_10GBASELR_CAPABLE)) {
1021 if (hw->bus.lan_id == 0)
1023 ixgbe_sfp_type_srlr_core0;
1026 ixgbe_sfp_type_srlr_core1;
1027 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1028 if (hw->bus.lan_id == 0)
1030 ixgbe_sfp_type_1g_cu_core0;
1033 ixgbe_sfp_type_1g_cu_core1;
1034 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1035 if (hw->bus.lan_id == 0)
1037 ixgbe_sfp_type_1g_sx_core0;
1040 ixgbe_sfp_type_1g_sx_core1;
1042 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1046 if (hw->phy.sfp_type != stored_sfp_type)
1047 hw->phy.sfp_setup_needed = true;
1049 /* Determine if the SFP+ PHY is dual speed or not. */
1050 hw->phy.multispeed_fiber = false;
1051 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1052 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1053 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1054 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1055 hw->phy.multispeed_fiber = true;
1057 /* Determine PHY vendor */
1058 if (hw->phy.type != ixgbe_phy_nl) {
1059 hw->phy.id = identifier;
1060 status = hw->phy.ops.read_i2c_eeprom(hw,
1061 IXGBE_SFF_VENDOR_OUI_BYTE0,
1064 if (status == IXGBE_ERR_SWFW_SYNC ||
1065 status == IXGBE_ERR_I2C ||
1066 status == IXGBE_ERR_SFP_NOT_PRESENT)
1067 goto err_read_i2c_eeprom;
1069 status = hw->phy.ops.read_i2c_eeprom(hw,
1070 IXGBE_SFF_VENDOR_OUI_BYTE1,
1073 if (status == IXGBE_ERR_SWFW_SYNC ||
1074 status == IXGBE_ERR_I2C ||
1075 status == IXGBE_ERR_SFP_NOT_PRESENT)
1076 goto err_read_i2c_eeprom;
1078 status = hw->phy.ops.read_i2c_eeprom(hw,
1079 IXGBE_SFF_VENDOR_OUI_BYTE2,
1082 if (status == IXGBE_ERR_SWFW_SYNC ||
1083 status == IXGBE_ERR_I2C ||
1084 status == IXGBE_ERR_SFP_NOT_PRESENT)
1085 goto err_read_i2c_eeprom;
1088 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1089 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1090 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1092 switch (vendor_oui) {
1093 case IXGBE_SFF_VENDOR_OUI_TYCO:
1094 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1096 ixgbe_phy_sfp_passive_tyco;
1098 case IXGBE_SFF_VENDOR_OUI_FTL:
1099 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1100 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1102 hw->phy.type = ixgbe_phy_sfp_ftl;
1104 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1105 hw->phy.type = ixgbe_phy_sfp_avago;
1107 case IXGBE_SFF_VENDOR_OUI_INTEL:
1108 hw->phy.type = ixgbe_phy_sfp_intel;
1111 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1113 ixgbe_phy_sfp_passive_unknown;
1114 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1116 ixgbe_phy_sfp_active_unknown;
1118 hw->phy.type = ixgbe_phy_sfp_unknown;
1123 /* Allow any DA cable vendor */
1124 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1125 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1130 /* Verify supported 1G SFP modules */
1131 if (comp_codes_10g == 0 &&
1132 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1133 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1134 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1135 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1136 hw->phy.type = ixgbe_phy_sfp_unsupported;
1137 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1141 /* Anything else 82598-based is supported */
1142 if (hw->mac.type == ixgbe_mac_82598EB) {
1147 ixgbe_get_device_caps(hw, &enforce_sfp);
1148 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1149 !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
1150 (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) ||
1151 (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0) ||
1152 (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1))) {
1153 /* Make sure we're a supported PHY type */
1154 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1157 if (hw->allow_unsupported_sfp == true) {
1158 EWARN(hw, "WARNING: Intel (R) Network "
1159 "Connections are quality tested "
1160 "using Intel (R) Ethernet Optics."
1161 " Using untested modules is not "
1162 "supported and may cause unstable"
1163 " operation or damage to the "
1164 "module or the adapter. Intel "
1165 "Corporation is not responsible "
1166 "for any harm caused by using "
1167 "untested modules.\n", status);
1170 hw_dbg(hw, "SFP+ module not supported\n");
1172 ixgbe_phy_sfp_unsupported;
1173 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1184 err_read_i2c_eeprom:
1185 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1186 if (hw->phy.type != ixgbe_phy_nl) {
1188 hw->phy.type = ixgbe_phy_unknown;
1190 return IXGBE_ERR_SFP_NOT_PRESENT;
1194 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1195 * @hw: pointer to hardware structure
1197 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1199 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1203 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1204 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1205 status = IXGBE_ERR_SFP_NOT_PRESENT;
1213 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1214 * @hw: pointer to hardware structure
1215 * @list_offset: offset to the SFP ID list
1216 * @data_offset: offset to the SFP data block
1218 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1219 * so it returns the offsets to the phy init sequence block.
1221 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1226 u16 sfp_type = hw->phy.sfp_type;
1228 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1229 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1231 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1232 return IXGBE_ERR_SFP_NOT_PRESENT;
1234 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1235 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1236 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1239 * Limiting active cables and 1G Phys must be initialized as
1242 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1243 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1244 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1245 sfp_type = ixgbe_sfp_type_srlr_core0;
1246 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1247 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1248 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1249 sfp_type = ixgbe_sfp_type_srlr_core1;
1251 /* Read offset to PHY init contents */
1252 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
1254 if ((!*list_offset) || (*list_offset == 0xFFFF))
1255 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1257 /* Shift offset to first ID word */
1261 * Find the matching SFP ID in the EEPROM
1262 * and program the init sequence
1264 hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
1266 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1267 if (sfp_id == sfp_type) {
1269 hw->eeprom.ops.read(hw, *list_offset, data_offset);
1270 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1271 hw_dbg(hw, "SFP+ module not supported\n");
1272 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1277 (*list_offset) += 2;
1278 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1279 return IXGBE_ERR_PHY;
1283 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1284 hw_dbg(hw, "No matching SFP+ module found\n");
1285 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1292 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1293 * @hw: pointer to hardware structure
1294 * @byte_offset: EEPROM byte offset to read
1295 * @eeprom_data: value read
1297 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1299 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1302 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1303 IXGBE_I2C_EEPROM_DEV_ADDR,
1308 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1309 * @hw: pointer to hardware structure
1310 * @byte_offset: EEPROM byte offset to write
1311 * @eeprom_data: value to write
1313 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1315 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1318 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1319 IXGBE_I2C_EEPROM_DEV_ADDR,
1324 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1325 * @hw: pointer to hardware structure
1326 * @byte_offset: byte offset to read
1329 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1330 * a specified device address.
1332 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1333 u8 dev_addr, u8 *data)
1342 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1343 swfw_mask = IXGBE_GSSR_PHY1_SM;
1345 swfw_mask = IXGBE_GSSR_PHY0_SM;
1348 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
1350 status = IXGBE_ERR_SWFW_SYNC;
1354 ixgbe_i2c_start(hw);
1356 /* Device Address and write indication */
1357 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1361 status = ixgbe_get_i2c_ack(hw);
1365 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1369 status = ixgbe_get_i2c_ack(hw);
1373 ixgbe_i2c_start(hw);
1375 /* Device Address and read indication */
1376 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1380 status = ixgbe_get_i2c_ack(hw);
1384 status = ixgbe_clock_in_i2c_byte(hw, data);
1388 status = ixgbe_clock_out_i2c_bit(hw, nack);
1396 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1398 ixgbe_i2c_bus_clear(hw);
1400 if (retry < max_retry)
1401 hw_dbg(hw, "I2C byte read error - Retrying.\n");
1403 hw_dbg(hw, "I2C byte read error.\n");
1405 } while (retry < max_retry);
1407 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1414 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1415 * @hw: pointer to hardware structure
1416 * @byte_offset: byte offset to write
1417 * @data: value to write
1419 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1420 * a specified device address.
1422 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1423 u8 dev_addr, u8 data)
1430 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1431 swfw_mask = IXGBE_GSSR_PHY1_SM;
1433 swfw_mask = IXGBE_GSSR_PHY0_SM;
1435 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) {
1436 status = IXGBE_ERR_SWFW_SYNC;
1437 goto write_byte_out;
1441 ixgbe_i2c_start(hw);
1443 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1447 status = ixgbe_get_i2c_ack(hw);
1451 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1455 status = ixgbe_get_i2c_ack(hw);
1459 status = ixgbe_clock_out_i2c_byte(hw, data);
1463 status = ixgbe_get_i2c_ack(hw);
1471 ixgbe_i2c_bus_clear(hw);
1473 if (retry < max_retry)
1474 hw_dbg(hw, "I2C byte write error - Retrying.\n");
1476 hw_dbg(hw, "I2C byte write error.\n");
1477 } while (retry < max_retry);
1479 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1486 * ixgbe_i2c_start - Sets I2C start condition
1487 * @hw: pointer to hardware structure
1489 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1491 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1493 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1495 /* Start condition must begin with data and clock high */
1496 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1497 ixgbe_raise_i2c_clk(hw, &i2cctl);
1499 /* Setup time for start condition (4.7us) */
1500 udelay(IXGBE_I2C_T_SU_STA);
1502 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1504 /* Hold time for start condition (4us) */
1505 udelay(IXGBE_I2C_T_HD_STA);
1507 ixgbe_lower_i2c_clk(hw, &i2cctl);
1509 /* Minimum low period of clock is 4.7 us */
1510 udelay(IXGBE_I2C_T_LOW);
1515 * ixgbe_i2c_stop - Sets I2C stop condition
1516 * @hw: pointer to hardware structure
1518 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1520 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1522 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1524 /* Stop condition must begin with data low and clock high */
1525 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1526 ixgbe_raise_i2c_clk(hw, &i2cctl);
1528 /* Setup time for stop condition (4us) */
1529 udelay(IXGBE_I2C_T_SU_STO);
1531 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1533 /* bus free time between stop and start (4.7us)*/
1534 udelay(IXGBE_I2C_T_BUF);
1538 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1539 * @hw: pointer to hardware structure
1540 * @data: data byte to clock in
1542 * Clocks in one byte data via I2C data/clock
1544 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1549 for (i = 7; i >= 0; i--) {
1550 ixgbe_clock_in_i2c_bit(hw, &bit);
1558 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1559 * @hw: pointer to hardware structure
1560 * @data: data byte clocked out
1562 * Clocks out one byte data via I2C data/clock
1564 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1571 for (i = 7; i >= 0; i--) {
1572 bit = (data >> i) & 0x1;
1573 status = ixgbe_clock_out_i2c_bit(hw, bit);
1579 /* Release SDA line (set high) */
1580 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1581 i2cctl |= IXGBE_I2C_DATA_OUT;
1582 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1583 IXGBE_WRITE_FLUSH(hw);
1589 * ixgbe_get_i2c_ack - Polls for I2C ACK
1590 * @hw: pointer to hardware structure
1592 * Clocks in/out one bit via I2C data/clock
1594 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1598 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1602 ixgbe_raise_i2c_clk(hw, &i2cctl);
1605 /* Minimum high period of clock is 4us */
1606 udelay(IXGBE_I2C_T_HIGH);
1608 /* Poll for ACK. Note that ACK in I2C spec is
1609 * transition from 1 to 0 */
1610 for (i = 0; i < timeout; i++) {
1611 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1612 ack = ixgbe_get_i2c_data(&i2cctl);
1620 hw_dbg(hw, "I2C ack was not received.\n");
1621 status = IXGBE_ERR_I2C;
1624 ixgbe_lower_i2c_clk(hw, &i2cctl);
1626 /* Minimum low period of clock is 4.7 us */
1627 udelay(IXGBE_I2C_T_LOW);
1633 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1634 * @hw: pointer to hardware structure
1635 * @data: read data value
1637 * Clocks in one bit via I2C data/clock
1639 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1641 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1643 ixgbe_raise_i2c_clk(hw, &i2cctl);
1645 /* Minimum high period of clock is 4us */
1646 udelay(IXGBE_I2C_T_HIGH);
1648 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1649 *data = ixgbe_get_i2c_data(&i2cctl);
1651 ixgbe_lower_i2c_clk(hw, &i2cctl);
1653 /* Minimum low period of clock is 4.7 us */
1654 udelay(IXGBE_I2C_T_LOW);
1660 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1661 * @hw: pointer to hardware structure
1662 * @data: data value to write
1664 * Clocks out one bit via I2C data/clock
1666 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1669 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1671 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1673 ixgbe_raise_i2c_clk(hw, &i2cctl);
1675 /* Minimum high period of clock is 4us */
1676 udelay(IXGBE_I2C_T_HIGH);
1678 ixgbe_lower_i2c_clk(hw, &i2cctl);
1680 /* Minimum low period of clock is 4.7 us.
1681 * This also takes care of the data hold time.
1683 udelay(IXGBE_I2C_T_LOW);
1685 status = IXGBE_ERR_I2C;
1686 hw_dbg(hw, "I2C data was not set to %X\n", data);
1692 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1693 * @hw: pointer to hardware structure
1694 * @i2cctl: Current value of I2CCTL register
1696 * Raises the I2C clock line '0'->'1'
1698 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1701 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1704 for (i = 0; i < timeout; i++) {
1705 *i2cctl |= IXGBE_I2C_CLK_OUT;
1707 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1708 IXGBE_WRITE_FLUSH(hw);
1709 /* SCL rise time (1000ns) */
1710 udelay(IXGBE_I2C_T_RISE);
1712 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1713 if (i2cctl_r & IXGBE_I2C_CLK_IN)
1719 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1720 * @hw: pointer to hardware structure
1721 * @i2cctl: Current value of I2CCTL register
1723 * Lowers the I2C clock line '1'->'0'
1725 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1728 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1730 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1731 IXGBE_WRITE_FLUSH(hw);
1733 /* SCL fall time (300ns) */
1734 udelay(IXGBE_I2C_T_FALL);
1738 * ixgbe_set_i2c_data - Sets the I2C data bit
1739 * @hw: pointer to hardware structure
1740 * @i2cctl: Current value of I2CCTL register
1741 * @data: I2C data value (0 or 1) to set
1743 * Sets the I2C data bit
1745 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1750 *i2cctl |= IXGBE_I2C_DATA_OUT;
1752 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1754 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1755 IXGBE_WRITE_FLUSH(hw);
1757 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1758 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1760 /* Verify data was set correctly */
1761 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1762 if (data != ixgbe_get_i2c_data(i2cctl)) {
1763 status = IXGBE_ERR_I2C;
1764 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1771 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1772 * @hw: pointer to hardware structure
1773 * @i2cctl: Current value of I2CCTL register
1775 * Returns the I2C data bit value
1777 static bool ixgbe_get_i2c_data(u32 *i2cctl)
1781 if (*i2cctl & IXGBE_I2C_DATA_IN)
1790 * ixgbe_i2c_bus_clear - Clears the I2C bus
1791 * @hw: pointer to hardware structure
1793 * Clears the I2C bus by sending nine clock pulses.
1794 * Used when data line is stuck low.
1796 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1798 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1801 ixgbe_i2c_start(hw);
1803 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1805 for (i = 0; i < 9; i++) {
1806 ixgbe_raise_i2c_clk(hw, &i2cctl);
1808 /* Min high period of clock is 4us */
1809 udelay(IXGBE_I2C_T_HIGH);
1811 ixgbe_lower_i2c_clk(hw, &i2cctl);
1813 /* Min low period of clock is 4.7us*/
1814 udelay(IXGBE_I2C_T_LOW);
1817 ixgbe_i2c_start(hw);
1819 /* Put the i2c bus back to default state */
1824 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
1825 * @hw: pointer to hardware structure
1827 * Checks if the LASI temp alarm status was triggered due to overtemp
1829 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1834 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1837 /* Check that the LASI temp alarm status was triggered */
1838 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1839 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
1841 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1844 status = IXGBE_ERR_OVERTEMP;