1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include "ixgbe_x540.h"
29 #include "ixgbe_type.h"
30 #include "ixgbe_api.h"
31 #include "ixgbe_common.h"
32 #include "ixgbe_phy.h"
34 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
35 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
36 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
37 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
40 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type
41 * @hw: pointer to hardware structure
43 * Initialize the function pointers and assign the MAC type for X540.
44 * Does not touch the hardware.
46 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
48 struct ixgbe_mac_info *mac = &hw->mac;
49 struct ixgbe_phy_info *phy = &hw->phy;
50 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
53 ret_val = ixgbe_init_phy_ops_generic(hw);
54 ret_val = ixgbe_init_ops_generic(hw);
58 eeprom->ops.init_params = &ixgbe_init_eeprom_params_X540;
59 eeprom->ops.read = &ixgbe_read_eerd_X540;
60 eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_X540;
61 eeprom->ops.write = &ixgbe_write_eewr_X540;
62 eeprom->ops.write_buffer = &ixgbe_write_eewr_buffer_X540;
63 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X540;
64 eeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X540;
65 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X540;
68 phy->ops.init = &ixgbe_init_phy_ops_generic;
69 phy->ops.reset = NULL;
72 mac->ops.reset_hw = &ixgbe_reset_hw_X540;
73 mac->ops.get_media_type = &ixgbe_get_media_type_X540;
74 mac->ops.get_supported_physical_layer =
75 &ixgbe_get_supported_physical_layer_X540;
76 mac->ops.read_analog_reg8 = NULL;
77 mac->ops.write_analog_reg8 = NULL;
78 mac->ops.start_hw = &ixgbe_start_hw_X540;
79 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
80 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
81 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
82 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
83 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
84 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540;
85 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync_X540;
86 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
87 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
89 /* RAR, Multicast, VLAN */
90 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
91 mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
92 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
93 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
94 mac->rar_highwater = 1;
95 mac->ops.set_vfta = &ixgbe_set_vfta_generic;
96 mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
97 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
98 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
99 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
100 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
103 mac->ops.get_link_capabilities =
104 &ixgbe_get_copper_link_capabilities_generic;
105 mac->ops.setup_link = &ixgbe_setup_mac_link_X540;
106 mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
107 mac->ops.check_link = &ixgbe_check_mac_link_generic;
109 mac->mcft_size = 128;
111 mac->num_rar_entries = 128;
112 mac->rx_pb_size = 384;
113 mac->max_tx_queues = 128;
114 mac->max_rx_queues = 128;
115 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
119 * ARC supported; valid only if manageability features are
122 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
123 IXGBE_FWSM_MODE_MASK) ? true : false;
125 //hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
128 mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
129 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
131 /* Manageability interface */
132 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
138 * ixgbe_get_link_capabilities_X540 - Determines link capabilities
139 * @hw: pointer to hardware structure
140 * @speed: pointer to link speed
141 * @autoneg: true when autoneg or autotry is enabled
143 * Determines the link capabilities by reading the AUTOC register.
145 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
146 ixgbe_link_speed *speed,
149 ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
155 * ixgbe_get_media_type_X540 - Get media type
156 * @hw: pointer to hardware structure
158 * Returns the media type (fiber, copper, backplane)
160 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
162 return ixgbe_media_type_copper;
166 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
167 * @hw: pointer to hardware structure
168 * @speed: new link speed
169 * @autoneg: true if autonegotiation enabled
170 * @autoneg_wait_to_complete: true when waiting for completion is needed
172 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
173 ixgbe_link_speed speed, bool autoneg,
174 bool autoneg_wait_to_complete)
176 return hw->phy.ops.setup_link_speed(hw, speed, autoneg,
177 autoneg_wait_to_complete);
181 * ixgbe_reset_hw_X540 - Perform hardware reset
182 * @hw: pointer to hardware structure
184 * Resets the hardware by resetting the transmit and receive units, masks
185 * and clears all interrupts, and perform a reset.
187 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
192 /* Call adapter stop to disable tx/rx and clear interrupts */
193 status = hw->mac.ops.stop_adapter(hw);
197 /* flush pending Tx transactions */
198 ixgbe_clear_tx_pending(hw);
201 ctrl = IXGBE_CTRL_RST;
202 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
203 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
204 IXGBE_WRITE_FLUSH(hw);
206 /* Poll for reset bit to self-clear indicating reset is complete */
207 for (i = 0; i < 10; i++) {
209 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
210 if (!(ctrl & IXGBE_CTRL_RST_MASK))
214 if (ctrl & IXGBE_CTRL_RST_MASK) {
215 status = IXGBE_ERR_RESET_FAILED;
216 hw_dbg(hw, "Reset polling failed to complete.\n");
221 * Double resets are required for recovery from certain error
222 * conditions. Between resets, it is necessary to stall to allow time
223 * for any pending HW events to complete.
225 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
226 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
230 /* Set the Rx packet buffer size. */
231 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
233 /* Store the permanent mac address */
234 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
237 * Store MAC address from RAR0, clear receive address registers, and
238 * clear the multicast table. Also reset num_rar_entries to 128,
239 * since we modify this value when programming the SAN MAC address.
241 hw->mac.num_rar_entries = 128;
242 hw->mac.ops.init_rx_addrs(hw);
244 /* Store the permanent SAN mac address */
245 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
247 /* Add the SAN MAC address to the RAR only if it's a valid address */
248 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
249 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
250 hw->mac.san_addr, 0, IXGBE_RAH_AV);
252 /* Save the SAN MAC RAR index */
253 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
255 /* Reserve the last RAR for the SAN MAC address */
256 hw->mac.num_rar_entries--;
259 /* Store the alternative WWNN/WWPN prefix */
260 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
261 &hw->mac.wwpn_prefix);
268 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
269 * @hw: pointer to hardware structure
271 * Starts the hardware using the generic start_hw function
272 * and the generation start_hw function.
273 * Then performs revision-specific operations, if any.
275 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
279 ret_val = ixgbe_start_hw_generic(hw);
283 ret_val = ixgbe_start_hw_gen2(hw);
290 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
291 * @hw: pointer to hardware structure
293 * Determines physical layer capabilities of the current configuration.
295 u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
297 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
300 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
301 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
302 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
303 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
304 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
305 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
306 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
307 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
309 return physical_layer;
313 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
314 * @hw: pointer to hardware structure
316 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
317 * ixgbe_hw struct in order to set up EEPROM access.
319 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
321 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
325 if (eeprom->type == ixgbe_eeprom_uninitialized) {
326 eeprom->semaphore_delay = 10;
327 eeprom->type = ixgbe_flash;
329 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
330 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
331 IXGBE_EEC_SIZE_SHIFT);
332 eeprom->word_size = 1 << (eeprom_size +
333 IXGBE_EEPROM_WORD_SIZE_SHIFT);
335 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
336 eeprom->type, eeprom->word_size);
343 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
344 * @hw: pointer to hardware structure
345 * @offset: offset of word in the EEPROM to read
346 * @data: word read from the EEPROM
348 * Reads a 16 bit word from the EEPROM using the EERD register.
350 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
354 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
356 status = ixgbe_read_eerd_generic(hw, offset, data);
358 status = IXGBE_ERR_SWFW_SYNC;
360 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
365 * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
366 * @hw: pointer to hardware structure
367 * @offset: offset of word in the EEPROM to read
368 * @words: number of words
369 * @data: word(s) read from the EEPROM
371 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
373 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
374 u16 offset, u16 words, u16 *data)
378 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
380 status = ixgbe_read_eerd_buffer_generic(hw, offset,
383 status = IXGBE_ERR_SWFW_SYNC;
385 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
390 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
391 * @hw: pointer to hardware structure
392 * @offset: offset of word in the EEPROM to write
393 * @data: word write to the EEPROM
395 * Write a 16 bit word to the EEPROM using the EEWR register.
397 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
401 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
403 status = ixgbe_write_eewr_generic(hw, offset, data);
405 status = IXGBE_ERR_SWFW_SYNC;
407 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
412 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
413 * @hw: pointer to hardware structure
414 * @offset: offset of word in the EEPROM to write
415 * @words: number of words
416 * @data: word(s) write to the EEPROM
418 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
420 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
421 u16 offset, u16 words, u16 *data)
425 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
427 status = ixgbe_write_eewr_buffer_generic(hw, offset,
430 status = IXGBE_ERR_SWFW_SYNC;
432 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
437 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
439 * This function does not use synchronization for EERD and EEWR. It can
440 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
442 * @hw: pointer to hardware structure
444 u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
454 * Do not use hw->eeprom.ops.read because we do not want to take
455 * the synchronization semaphores here. Instead use
456 * ixgbe_read_eerd_generic
459 /* Include 0x0-0x3F in the checksum */
460 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
461 if (ixgbe_read_eerd_generic(hw, i, &word) != 0) {
462 hw_dbg(hw, "EEPROM read failed\n");
469 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
470 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
472 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
473 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
476 if (ixgbe_read_eerd_generic(hw, i, &pointer) != 0) {
477 hw_dbg(hw, "EEPROM read failed\n");
481 /* Skip pointer section if the pointer is invalid. */
482 if (pointer == 0xFFFF || pointer == 0 ||
483 pointer >= hw->eeprom.word_size)
486 if (ixgbe_read_eerd_generic(hw, pointer, &length) !=
488 hw_dbg(hw, "EEPROM read failed\n");
492 /* Skip pointer section if length is invalid. */
493 if (length == 0xFFFF || length == 0 ||
494 (pointer + length) >= hw->eeprom.word_size)
497 for (j = pointer+1; j <= pointer+length; j++) {
498 if (ixgbe_read_eerd_generic(hw, j, &word) !=
500 hw_dbg(hw, "EEPROM read failed\n");
507 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
513 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
514 * @hw: pointer to hardware structure
515 * @checksum_val: calculated checksum
517 * Performs checksum calculation and validates the EEPROM checksum. If the
518 * caller does not need checksum_val, the value can be NULL.
520 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
525 u16 read_checksum = 0;
528 * Read the first word from the EEPROM. If this times out or fails, do
529 * not continue or we could be in for a very long wait while every
532 status = hw->eeprom.ops.read(hw, 0, &checksum);
535 hw_dbg(hw, "EEPROM read failed\n");
539 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
541 checksum = hw->eeprom.ops.calc_checksum(hw);
544 * Do not use hw->eeprom.ops.read because we do not want to take
545 * the synchronization semaphores twice here.
547 ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
551 * Verify read checksum from EEPROM is the same as
552 * calculated checksum
554 if (read_checksum != checksum)
555 status = IXGBE_ERR_EEPROM_CHECKSUM;
557 /* If the user cares, return the calculated checksum */
559 *checksum_val = checksum;
561 status = IXGBE_ERR_SWFW_SYNC;
564 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
570 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
571 * @hw: pointer to hardware structure
573 * After writing EEPROM to shadow RAM using EEWR register, software calculates
574 * checksum and updates the EEPROM and instructs the hardware to update
577 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
583 * Read the first word from the EEPROM. If this times out or fails, do
584 * not continue or we could be in for a very long wait while every
587 status = hw->eeprom.ops.read(hw, 0, &checksum);
590 hw_dbg(hw, "EEPROM read failed\n");
592 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
594 checksum = hw->eeprom.ops.calc_checksum(hw);
597 * Do not use hw->eeprom.ops.write because we do not want to
598 * take the synchronization semaphores twice here.
600 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM,
604 status = ixgbe_update_flash_X540(hw);
606 status = IXGBE_ERR_SWFW_SYNC;
609 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
615 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
616 * @hw: pointer to hardware structure
618 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
619 * EEPROM from shadow RAM to the flash device.
621 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
624 s32 status = IXGBE_ERR_EEPROM;
626 status = ixgbe_poll_flash_update_done_X540(hw);
627 if (status == IXGBE_ERR_EEPROM) {
628 hw_dbg(hw, "Flash update time out\n");
632 flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
633 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
635 status = ixgbe_poll_flash_update_done_X540(hw);
637 hw_dbg(hw, "Flash update complete\n");
639 hw_dbg(hw, "Flash update time out\n");
641 if (hw->revision_id == 0) {
642 flup = IXGBE_READ_REG(hw, IXGBE_EEC);
644 if (flup & IXGBE_EEC_SEC1VAL) {
645 flup |= IXGBE_EEC_FLUP;
646 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
649 status = ixgbe_poll_flash_update_done_X540(hw);
651 hw_dbg(hw, "Flash update complete\n");
653 hw_dbg(hw, "Flash update time out\n");
660 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
661 * @hw: pointer to hardware structure
663 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
664 * flash update is done.
666 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
670 s32 status = IXGBE_ERR_EEPROM;
672 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
673 reg = IXGBE_READ_REG(hw, IXGBE_EEC);
674 if (reg & IXGBE_EEC_FLUDONE) {
684 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
685 * @hw: pointer to hardware structure
686 * @mask: Mask to specify which semaphore to acquire
688 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
689 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
691 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
695 u32 fwmask = mask << 5;
701 if (swmask == IXGBE_GSSR_EEP_SM)
702 hwmask = IXGBE_GSSR_FLASH_SM;
704 /* SW only mask doesn't have FW bit pair */
705 if (swmask == IXGBE_GSSR_SW_MNG_SM)
708 for (i = 0; i < timeout; i++) {
710 * SW NVM semaphore bit is used for access to all
711 * SW_FW_SYNC bits (not just NVM)
713 if (ixgbe_get_swfw_sync_semaphore(hw)) {
714 ret_val = IXGBE_ERR_SWFW_SYNC;
718 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
719 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
721 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
722 ixgbe_release_swfw_sync_semaphore(hw);
727 * Firmware currently using resource (fwmask), hardware
728 * currently using resource (hwmask), or other software
729 * thread currently using resource (swmask)
731 ixgbe_release_swfw_sync_semaphore(hw);
736 /* Failed to get SW only semaphore */
737 if (swmask == IXGBE_GSSR_SW_MNG_SM) {
738 ret_val = IXGBE_ERR_SWFW_SYNC;
742 /* If the resource is not released by the FW/HW the SW can assume that
743 * the FW/HW malfunctions. In that case the SW should sets the SW bit(s)
744 * of the requested resource(s) while ignoring the corresponding FW/HW
745 * bits in the SW_FW_SYNC register.
747 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
748 if (swfw_sync & (fwmask | hwmask)) {
749 if (ixgbe_get_swfw_sync_semaphore(hw)) {
750 ret_val = IXGBE_ERR_SWFW_SYNC;
755 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
756 ixgbe_release_swfw_sync_semaphore(hw);
765 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
766 * @hw: pointer to hardware structure
767 * @mask: Mask to specify which semaphore to release
769 * Releases the SWFW semaphore through the SW_FW_SYNC register
770 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
772 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
777 ixgbe_get_swfw_sync_semaphore(hw);
779 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
780 swfw_sync &= ~swmask;
781 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
783 ixgbe_release_swfw_sync_semaphore(hw);
788 * ixgbe_get_nvm_semaphore - Get hardware semaphore
789 * @hw: pointer to hardware structure
791 * Sets the hardware semaphores so SW/FW can gain control of shared resources
793 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
795 s32 status = IXGBE_ERR_EEPROM;
800 /* Get SMBI software semaphore between device drivers first */
801 for (i = 0; i < timeout; i++) {
803 * If the SMBI bit is 0 when we read it, then the bit will be
804 * set and we have the semaphore
806 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
807 if (!(swsm & IXGBE_SWSM_SMBI)) {
814 /* Now get the semaphore between SW/FW through the REGSMP bit */
816 for (i = 0; i < timeout; i++) {
817 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
818 if (!(swsm & IXGBE_SWFW_REGSMP))
825 * Release semaphores and return error if SW NVM semaphore
826 * was not granted because we don't have access to the EEPROM
829 hw_dbg(hw, "REGSMP Software NVM semaphore not "
831 ixgbe_release_swfw_sync_semaphore(hw);
832 status = IXGBE_ERR_EEPROM;
835 hw_dbg(hw, "Software semaphore SMBI between device drivers "
843 * ixgbe_release_nvm_semaphore - Release hardware semaphore
844 * @hw: pointer to hardware structure
846 * This function clears hardware semaphore bits.
848 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
852 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
854 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
855 swsm &= ~IXGBE_SWSM_SMBI;
856 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
858 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
859 swsm &= ~IXGBE_SWFW_REGSMP;
860 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
862 IXGBE_WRITE_FLUSH(hw);
866 * ixgbe_blink_led_start_X540 - Blink LED based on index.
867 * @hw: pointer to hardware structure
868 * @index: led number to blink
870 * Devices that implement the version 2 interface:
873 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
877 ixgbe_link_speed speed;
881 * Link should be up in order for the blink bit in the LED control
882 * register to work. Force link and speed in the MAC if link is down.
883 * This will be reversed when we stop the blinking.
885 hw->mac.ops.check_link(hw, &speed, &link_up, false);
886 if (link_up == false) {
887 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
888 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
889 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
891 /* Set the LED to LINK_UP + BLINK. */
892 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
893 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
894 ledctl_reg |= IXGBE_LED_BLINK(index);
895 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
896 IXGBE_WRITE_FLUSH(hw);
902 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
903 * @hw: pointer to hardware structure
904 * @index: led number to stop blinking
906 * Devices that implement the version 2 interface:
909 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
914 /* Restore the LED to its default value. */
915 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
916 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
917 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
918 ledctl_reg &= ~IXGBE_LED_BLINK(index);
919 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
921 /* Unforce link and speed in the MAC. */
922 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
923 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
924 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
925 IXGBE_WRITE_FLUSH(hw);