2 * SPDX-License-Identifier: BSD-3-Clause
3 * Inspired from FreeBSD src/sys/powerpc/include/atomic.h
4 * Copyright (c) 2008 Marcel Moolenaar
5 * Copyright (c) 2001 Benno Rice
6 * Copyright (c) 2001 David E. O'Brien
7 * Copyright (c) 1998 Doug Rabson
11 #ifndef _RTE_ATOMIC_PPC_64_H_
12 #define _RTE_ATOMIC_PPC_64_H_
19 #include "generic/rte_atomic.h"
21 #define rte_mb() asm volatile("sync" : : : "memory")
23 #define rte_wmb() asm volatile("sync" : : : "memory")
25 #define rte_rmb() asm volatile("sync" : : : "memory")
27 #define rte_smp_mb() rte_mb()
29 #define rte_smp_wmb() rte_wmb()
31 #define rte_smp_rmb() rte_rmb()
33 #define rte_io_mb() rte_mb()
35 #define rte_io_wmb() rte_wmb()
37 #define rte_io_rmb() rte_rmb()
39 static __rte_always_inline void
40 rte_atomic_thread_fence(int memorder)
42 __atomic_thread_fence(memorder);
45 /*------------------------- 16 bit atomic operations -------------------------*/
46 /* To be compatible with Power7, use GCC built-in functions for 16 bit
49 #ifndef RTE_FORCE_INTRINSICS
51 rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)
53 return __atomic_compare_exchange(dst, &exp, &src, 0, __ATOMIC_ACQUIRE,
54 __ATOMIC_ACQUIRE) ? 1 : 0;
57 static inline int rte_atomic16_test_and_set(rte_atomic16_t *v)
59 return rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1);
63 rte_atomic16_inc(rte_atomic16_t *v)
65 __atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE);
69 rte_atomic16_dec(rte_atomic16_t *v)
71 __atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE);
74 static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)
76 return __atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0;
79 static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)
81 return __atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0;
84 static inline uint16_t
85 rte_atomic16_exchange(volatile uint16_t *dst, uint16_t val)
87 return __atomic_exchange_2(dst, val, __ATOMIC_SEQ_CST);
90 /*------------------------- 32 bit atomic operations -------------------------*/
93 rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)
99 "1:\tlwarx %[ret], 0, %[dst]\n"
100 "cmplw %[exp], %[ret]\n"
102 "stwcx. %[src], 0, %[dst]\n"
107 "stwcx. %[ret], 0, %[dst]\n"
111 : [ret] "=&r" (ret), "=m" (*dst)
121 static inline int rte_atomic32_test_and_set(rte_atomic32_t *v)
123 return rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1);
127 rte_atomic32_inc(rte_atomic32_t *v)
132 "1: lwarx %[t],0,%[cnt]\n"
133 "addic %[t],%[t],1\n"
134 "stwcx. %[t],0,%[cnt]\n"
136 : [t] "=&r" (t), "=m" (v->cnt)
137 : [cnt] "r" (&v->cnt), "m" (v->cnt)
138 : "cc", "xer", "memory");
142 rte_atomic32_dec(rte_atomic32_t *v)
147 "1: lwarx %[t],0,%[cnt]\n"
148 "addic %[t],%[t],-1\n"
149 "stwcx. %[t],0,%[cnt]\n"
151 : [t] "=&r" (t), "=m" (v->cnt)
152 : [cnt] "r" (&v->cnt), "m" (v->cnt)
153 : "cc", "xer", "memory");
156 static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)
162 "1: lwarx %[ret],0,%[cnt]\n"
163 "addic %[ret],%[ret],1\n"
164 "stwcx. %[ret],0,%[cnt]\n"
168 : [cnt] "r" (&v->cnt)
169 : "cc", "xer", "memory");
174 static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)
180 "1: lwarx %[ret],0,%[cnt]\n"
181 "addic %[ret],%[ret],-1\n"
182 "stwcx. %[ret],0,%[cnt]\n"
186 : [cnt] "r" (&v->cnt)
187 : "cc", "xer", "memory");
192 static inline uint32_t
193 rte_atomic32_exchange(volatile uint32_t *dst, uint32_t val)
195 return __atomic_exchange_4(dst, val, __ATOMIC_SEQ_CST);
198 /*------------------------- 64 bit atomic operations -------------------------*/
201 rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)
203 unsigned int ret = 0;
207 "1: ldarx %[ret], 0, %[dst]\n"
208 "cmpld %[exp], %[ret]\n"
210 "stdcx. %[src], 0, %[dst]\n"
215 "stdcx. %[ret], 0, %[dst]\n"
219 : [ret] "=&r" (ret), "=m" (*dst)
229 rte_atomic64_init(rte_atomic64_t *v)
234 static inline int64_t
235 rte_atomic64_read(rte_atomic64_t *v)
239 asm volatile("ld%U1%X1 %[ret],%[cnt]"
241 : [cnt] "m"(v->cnt));
247 rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
249 asm volatile("std%U0%X0 %[new_value],%[cnt]"
251 : [new_value] "r"(new_value));
255 rte_atomic64_add(rte_atomic64_t *v, int64_t inc)
260 "1: ldarx %[t],0,%[cnt]\n"
261 "add %[t],%[inc],%[t]\n"
262 "stdcx. %[t],0,%[cnt]\n"
264 : [t] "=&r" (t), "=m" (v->cnt)
265 : [cnt] "r" (&v->cnt), [inc] "r" (inc), "m" (v->cnt)
270 rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)
275 "1: ldarx %[t],0,%[cnt]\n"
276 "subf %[t],%[dec],%[t]\n"
277 "stdcx. %[t],0,%[cnt]\n"
279 : [t] "=&r" (t), "+m" (v->cnt)
280 : [cnt] "r" (&v->cnt), [dec] "r" (dec), "m" (v->cnt)
285 rte_atomic64_inc(rte_atomic64_t *v)
290 "1: ldarx %[t],0,%[cnt]\n"
291 "addic %[t],%[t],1\n"
292 "stdcx. %[t],0,%[cnt]\n"
294 : [t] "=&r" (t), "+m" (v->cnt)
295 : [cnt] "r" (&v->cnt), "m" (v->cnt)
296 : "cc", "xer", "memory");
300 rte_atomic64_dec(rte_atomic64_t *v)
305 "1: ldarx %[t],0,%[cnt]\n"
306 "addic %[t],%[t],-1\n"
307 "stdcx. %[t],0,%[cnt]\n"
309 : [t] "=&r" (t), "+m" (v->cnt)
310 : [cnt] "r" (&v->cnt), "m" (v->cnt)
311 : "cc", "xer", "memory");
314 static inline int64_t
315 rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)
321 "1: ldarx %[ret],0,%[cnt]\n"
322 "add %[ret],%[inc],%[ret]\n"
323 "stdcx. %[ret],0,%[cnt]\n"
327 : [inc] "r" (inc), [cnt] "r" (&v->cnt)
333 static inline int64_t
334 rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)
340 "1: ldarx %[ret],0,%[cnt]\n"
341 "subf %[ret],%[dec],%[ret]\n"
342 "stdcx. %[ret],0,%[cnt]\n"
346 : [dec] "r" (dec), [cnt] "r" (&v->cnt)
352 static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)
358 "1: ldarx %[ret],0,%[cnt]\n"
359 "addic %[ret],%[ret],1\n"
360 "stdcx. %[ret],0,%[cnt]\n"
364 : [cnt] "r" (&v->cnt)
365 : "cc", "xer", "memory");
370 static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
376 "1: ldarx %[ret],0,%[cnt]\n"
377 "addic %[ret],%[ret],-1\n"
378 "stdcx. %[ret],0,%[cnt]\n"
382 : [cnt] "r" (&v->cnt)
383 : "cc", "xer", "memory");
388 static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
390 return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);
393 * Atomically set a 64-bit counter to 0.
396 * A pointer to the atomic counter.
398 static inline void rte_atomic64_clear(rte_atomic64_t *v)
403 static inline uint64_t
404 rte_atomic64_exchange(volatile uint64_t *dst, uint64_t val)
406 return __atomic_exchange_8(dst, val, __ATOMIC_SEQ_CST);
415 #endif /* _RTE_ATOMIC_PPC_64_H_ */