1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
10 * Contains crypto specific functions/structures/macros used internally
15 * AES-GCM devices have some specific requirements for IV and AAD formats.
16 * Ideally that to be done by the driver itself.
23 } __attribute__((packed));
28 * RFC 4106, section 5:
29 * Two formats of the AAD are defined:
30 * one for 32-bit sequence numbers, and one for 64-bit ESN.
36 uint32_t align0; /* align to 16B boundary */
37 } __attribute__((packed));
42 } __attribute__((packed));
46 aead_gcm_iv_fill(struct aead_gcm_iv *gcm, uint64_t iv, uint32_t salt)
50 gcm->cnt = rte_cpu_to_be_32(1);
54 * RFC 4106, 5 AAD Construction
55 * spi and sqn should already be converted into network byte order.
56 * Make sure that not used bytes are zeroed.
59 aead_gcm_aad_fill(struct aead_gcm_aad *aad, rte_be32_t spi, rte_be64_t sqn,
66 aad->sqn.u32[0] = sqn_low32(sqn);
73 gen_iv(uint64_t iv[IPSEC_MAX_IV_QWORD], rte_be64_t sqn)
80 * from RFC 4303 3.3.2.1.4:
81 * If the ESN option is enabled for the SA, the high-order 32
82 * bits of the sequence number are appended after the Next Header field
83 * for purposes of this computation, but are not transmitted.
87 * Helper function that moves ICV by 4B below, and inserts SQN.hibits.
88 * icv parameter points to the new start of ICV.
91 insert_sqh(uint32_t sqh, void *picv, uint32_t icv_len)
96 RTE_ASSERT(icv_len % sizeof(uint32_t) == 0);
99 icv_len = icv_len / sizeof(uint32_t);
100 for (i = icv_len; i-- != 0; icv[i] = icv[i - 1])
107 * Helper function that moves ICV by 4B up, and removes SQN.hibits.
108 * icv parameter points to the new start of ICV.
111 remove_sqh(void *picv, uint32_t icv_len)
115 RTE_ASSERT(icv_len % sizeof(uint32_t) == 0);
118 icv_len = icv_len / sizeof(uint32_t);
119 for (i = 0; i != icv_len; i++)
123 #endif /* _CRYPTO_H_ */