4 * Copyright(c) 2017 Intel Corporation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include <rte_cpuflags.h>
39 #include <rte_common.h>
40 #include <rte_net_crc.h>
42 #if defined(RTE_ARCH_X86_64) && defined(RTE_MACHINE_CPUFLAG_PCLMULQDQ)
43 #define X86_64_SSE42_PCLMULQDQ 1
44 #elif defined(RTE_ARCH_ARM64) && defined(RTE_MACHINE_CPUFLAG_PMULL)
45 #define ARM64_NEON_PMULL 1
48 #ifdef X86_64_SSE42_PCLMULQDQ
49 #include <net_crc_sse.h>
50 #elif defined ARM64_NEON_PMULL
51 #include <net_crc_neon.h>
55 static uint32_t crc32_eth_lut[CRC_LUT_SIZE];
56 static uint32_t crc16_ccitt_lut[CRC_LUT_SIZE];
59 rte_crc16_ccitt_handler(const uint8_t *data, uint32_t data_len);
62 rte_crc32_eth_handler(const uint8_t *data, uint32_t data_len);
65 (*rte_net_crc_handler)(const uint8_t *data, uint32_t data_len);
67 static rte_net_crc_handler *handlers;
69 static rte_net_crc_handler handlers_scalar[] = {
70 [RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_handler,
71 [RTE_NET_CRC32_ETH] = rte_crc32_eth_handler,
74 #ifdef X86_64_SSE42_PCLMULQDQ
75 static rte_net_crc_handler handlers_sse42[] = {
76 [RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_sse42_handler,
77 [RTE_NET_CRC32_ETH] = rte_crc32_eth_sse42_handler,
79 #elif defined ARM64_NEON_PMULL
80 static rte_net_crc_handler handlers_neon[] = {
81 [RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_neon_handler,
82 [RTE_NET_CRC32_ETH] = rte_crc32_eth_neon_handler,
87 * Reflect the bits about the middle
90 * value to be reflected
96 reflect_32bits(uint32_t val)
100 for (i = 0; i < 32; i++)
101 if ((val & (1 << i)) != 0)
102 res |= (uint32_t)(1 << (31 - i));
108 crc32_eth_init_lut(uint32_t poly,
113 for (i = 0; i < CRC_LUT_SIZE; i++) {
114 uint32_t crc = reflect_32bits(i);
116 for (j = 0; j < 8; j++) {
117 if (crc & 0x80000000L)
118 crc = (crc << 1) ^ poly;
122 lut[i] = reflect_32bits(crc);
126 static __rte_always_inline uint32_t
127 crc32_eth_calc_lut(const uint8_t *data,
133 crc = lut[(crc ^ *data++) & 0xffL] ^ (crc >> 8);
139 rte_net_crc_scalar_init(void)
141 /* 32-bit crc init */
142 crc32_eth_init_lut(CRC32_ETH_POLYNOMIAL, crc32_eth_lut);
144 /* 16-bit CRC init */
145 crc32_eth_init_lut(CRC16_CCITT_POLYNOMIAL << 16, crc16_ccitt_lut);
148 static inline uint32_t
149 rte_crc16_ccitt_handler(const uint8_t *data, uint32_t data_len)
151 /* return 16-bit CRC value */
152 return (uint16_t)~crc32_eth_calc_lut(data,
158 static inline uint32_t
159 rte_crc32_eth_handler(const uint8_t *data, uint32_t data_len)
161 /* return 32-bit CRC value */
162 return ~crc32_eth_calc_lut(data,
169 rte_net_crc_set_alg(enum rte_net_crc_alg alg)
172 #ifdef X86_64_SSE42_PCLMULQDQ
173 case RTE_NET_CRC_SSE42:
174 handlers = handlers_sse42;
176 #elif defined ARM64_NEON_PMULL
178 case RTE_NET_CRC_NEON:
179 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL)) {
180 handlers = handlers_neon;
185 case RTE_NET_CRC_SCALAR:
188 handlers = handlers_scalar;
194 rte_net_crc_calc(const void *data,
196 enum rte_net_crc_type type)
199 rte_net_crc_handler f_handle;
201 f_handle = handlers[type];
202 ret = f_handle(data, data_len);
207 /* Select highest available crc algorithm as default one */
208 RTE_INIT(rte_net_crc_init)
210 enum rte_net_crc_alg alg = RTE_NET_CRC_SCALAR;
212 rte_net_crc_scalar_init();
214 #ifdef X86_64_SSE42_PCLMULQDQ
215 alg = RTE_NET_CRC_SSE42;
216 rte_net_crc_sse42_init();
217 #elif defined ARM64_NEON_PMULL
218 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL)) {
219 alg = RTE_NET_CRC_NEON;
220 rte_net_crc_neon_init();
224 rte_net_crc_set_alg(alg);