lib/librte_net/rte_net_crc.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017-2020 Intel Corporation
   3  */
   4
   5 #include <stddef.h>
   6 #include <string.h>
   7 #include <stdint.h>
   8
   9 #include <rte_cpuflags.h>
  10 #include <rte_common.h>
  11 #include <rte_net_crc.h>
  12
  13 #include "net_crc.h"
  14
  15 /** CRC polynomials */
  16 #define CRC32_ETH_POLYNOMIAL 0x04c11db7UL
  17 #define CRC16_CCITT_POLYNOMIAL 0x1021U
  18
  19 #define CRC_LUT_SIZE 256
  20
  21 /* crc tables */
  22 static uint32_t crc32_eth_lut[CRC_LUT_SIZE];
  23 static uint32_t crc16_ccitt_lut[CRC_LUT_SIZE];
  24
  25 static uint32_t
  26 rte_crc16_ccitt_handler(const uint8_t *data, uint32_t data_len);
  27
  28 static uint32_t
  29 rte_crc32_eth_handler(const uint8_t *data, uint32_t data_len);
  30
  31 typedef uint32_t
  32 (*rte_net_crc_handler)(const uint8_t *data, uint32_t data_len);
  33
  34 static const rte_net_crc_handler *handlers;
  35
  36 static const rte_net_crc_handler handlers_scalar[] = {
  37         [RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_handler,
  38         [RTE_NET_CRC32_ETH] = rte_crc32_eth_handler,
  39 };
  40 #ifdef CC_X86_64_AVX512_VPCLMULQDQ_SUPPORT
  41 static const rte_net_crc_handler handlers_avx512[] = {
  42         [RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_avx512_handler,
  43         [RTE_NET_CRC32_ETH] = rte_crc32_eth_avx512_handler,
  44 };
  45 #endif
  46 #ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT
  47 static const rte_net_crc_handler handlers_sse42[] = {
  48         [RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_sse42_handler,
  49         [RTE_NET_CRC32_ETH] = rte_crc32_eth_sse42_handler,
  50 };
  51 #endif
  52 #ifdef CC_ARM64_NEON_PMULL_SUPPORT
  53 static const rte_net_crc_handler handlers_neon[] = {
  54         [RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_neon_handler,
  55         [RTE_NET_CRC32_ETH] = rte_crc32_eth_neon_handler,
  56 };
  57 #endif
  58
  59 /* Scalar handling */
  60
  61 /**
  62  * Reflect the bits about the middle
  63  *
  64  * @param val
  65  *   value to be reflected
  66  *
  67  * @return
  68  *   reflected value
  69  */
  70 static uint32_t
  71 reflect_32bits(uint32_t val)
  72 {
  73         uint32_t i, res = 0;
  74
  75         for (i = 0; i < 32; i++)
  76                 if ((val & (1U << i)) != 0)
  77                         res |= (uint32_t)(1U << (31 - i));
  78
  79         return res;
  80 }
  81
  82 static void
  83 crc32_eth_init_lut(uint32_t poly,
  84         uint32_t *lut)
  85 {
  86         uint32_t i, j;
  87
  88         for (i = 0; i < CRC_LUT_SIZE; i++) {
  89                 uint32_t crc = reflect_32bits(i);
  90
  91                 for (j = 0; j < 8; j++) {
  92                         if (crc & 0x80000000L)
  93                                 crc = (crc << 1) ^ poly;
  94                         else
  95                                 crc <<= 1;
  96                 }
  97                 lut[i] = reflect_32bits(crc);
  98         }
  99 }
 100
 101 static __rte_always_inline uint32_t
 102 crc32_eth_calc_lut(const uint8_t *data,
 103         uint32_t data_len,
 104         uint32_t crc,
 105         const uint32_t *lut)
 106 {
 107         while (data_len--)
 108                 crc = lut[(crc ^ *data++) & 0xffL] ^ (crc >> 8);
 109
 110         return crc;
 111 }
 112
 113 static void
 114 rte_net_crc_scalar_init(void)
 115 {
 116         /* 32-bit crc init */
 117         crc32_eth_init_lut(CRC32_ETH_POLYNOMIAL, crc32_eth_lut);
 118
 119         /* 16-bit CRC init */
 120         crc32_eth_init_lut(CRC16_CCITT_POLYNOMIAL << 16, crc16_ccitt_lut);
 121 }
 122
 123 static inline uint32_t
 124 rte_crc16_ccitt_handler(const uint8_t *data, uint32_t data_len)
 125 {
 126         /* return 16-bit CRC value */
 127         return (uint16_t)~crc32_eth_calc_lut(data,
 128                 data_len,
 129                 0xffff,
 130                 crc16_ccitt_lut);
 131 }
 132
 133 static inline uint32_t
 134 rte_crc32_eth_handler(const uint8_t *data, uint32_t data_len)
 135 {
 136         /* return 32-bit CRC value */
 137         return ~crc32_eth_calc_lut(data,
 138                 data_len,
 139                 0xffffffffUL,
 140                 crc32_eth_lut);
 141 }
 142
 143 /* AVX512/VPCLMULQDQ handling */
 144
 145 #define AVX512_VPCLMULQDQ_CPU_SUPPORTED ( \
 146         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) && \
 147         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) && \
 148         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512DQ) && \
 149         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512VL) && \
 150         rte_cpu_get_flag_enabled(RTE_CPUFLAG_PCLMULQDQ) && \
 151         rte_cpu_get_flag_enabled(RTE_CPUFLAG_VPCLMULQDQ) \
 152 )
 153
 154 static const rte_net_crc_handler *
 155 avx512_vpclmulqdq_get_handlers(void)
 156 {
 157 #ifdef CC_X86_64_AVX512_VPCLMULQDQ_SUPPORT
 158         if (AVX512_VPCLMULQDQ_CPU_SUPPORTED)
 159                 return handlers_avx512;
 160 #endif
 161         return NULL;
 162 }
 163
 164 static uint8_t
 165 avx512_vpclmulqdq_init(void)
 166 {
 167 #ifdef CC_X86_64_AVX512_VPCLMULQDQ_SUPPORT
 168         if (AVX512_VPCLMULQDQ_CPU_SUPPORTED) {
 169                 rte_net_crc_avx512_init();
 170                 return 1;
 171         }
 172 #endif
 173         return 0;
 174 }
 175
 176 /* SSE4.2/PCLMULQDQ handling */
 177
 178 #define SSE42_PCLMULQDQ_CPU_SUPPORTED \
 179         rte_cpu_get_flag_enabled(RTE_CPUFLAG_PCLMULQDQ)
 180
 181 static const rte_net_crc_handler *
 182 sse42_pclmulqdq_get_handlers(void)
 183 {
 184 #ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT
 185         if (SSE42_PCLMULQDQ_CPU_SUPPORTED)
 186                 return handlers_sse42;
 187 #endif
 188         return NULL;
 189 }
 190
 191 static uint8_t
 192 sse42_pclmulqdq_init(void)
 193 {
 194 #ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT
 195         if (SSE42_PCLMULQDQ_CPU_SUPPORTED) {
 196                 rte_net_crc_sse42_init();
 197                 return 1;
 198         }
 199 #endif
 200         return 0;
 201 }
 202
 203 /* NEON/PMULL handling */
 204
 205 #define NEON_PMULL_CPU_SUPPORTED \
 206         rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL)
 207
 208 static const rte_net_crc_handler *
 209 neon_pmull_get_handlers(void)
 210 {
 211 #ifdef CC_ARM64_NEON_PMULL_SUPPORT
 212         if (NEON_PMULL_CPU_SUPPORTED)
 213                 return handlers_neon;
 214 #endif
 215         return NULL;
 216 }
 217
 218 static uint8_t
 219 neon_pmull_init(void)
 220 {
 221 #ifdef CC_ARM64_NEON_PMULL_SUPPORT
 222         if (NEON_PMULL_CPU_SUPPORTED) {
 223                 rte_net_crc_neon_init();
 224                 return 1;
 225         }
 226 #endif
 227         return 0;
 228 }
 229
 230 /* Public API */
 231
 232 void
 233 rte_net_crc_set_alg(enum rte_net_crc_alg alg)
 234 {
 235         handlers = NULL;
 236
 237         switch (alg) {
 238         case RTE_NET_CRC_AVX512:
 239                 handlers = avx512_vpclmulqdq_get_handlers();
 240                 if (handlers != NULL)
 241                         break;
 242                 /* fall-through */
 243         case RTE_NET_CRC_SSE42:
 244                 handlers = sse42_pclmulqdq_get_handlers();
 245                 break; /* for x86, always break here */
 246         case RTE_NET_CRC_NEON:
 247                 handlers = neon_pmull_get_handlers();
 248                 /* fall-through */
 249         case RTE_NET_CRC_SCALAR:
 250                 /* fall-through */
 251         default:
 252                 break;
 253         }
 254
 255         if (handlers == NULL)
 256                 handlers = handlers_scalar;
 257 }
 258
 259 uint32_t
 260 rte_net_crc_calc(const void *data,
 261         uint32_t data_len,
 262         enum rte_net_crc_type type)
 263 {
 264         uint32_t ret;
 265         rte_net_crc_handler f_handle;
 266
 267         f_handle = handlers[type];
 268         ret = f_handle(data, data_len);
 269
 270         return ret;
 271 }
 272
 273 /* Select highest available crc algorithm as default one */
 274 RTE_INIT(rte_net_crc_init)
 275 {
 276         enum rte_net_crc_alg alg = RTE_NET_CRC_SCALAR;
 277
 278         rte_net_crc_scalar_init();
 279
 280         if (sse42_pclmulqdq_init())
 281                 alg = RTE_NET_CRC_SSE42;
 282         if (avx512_vpclmulqdq_init())
 283                 alg = RTE_NET_CRC_AVX512;
 284         if (neon_pmull_init())
 285                 alg = RTE_NET_CRC_NEON;
 286
 287         rte_net_crc_set_alg(alg);
 288 }