1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017-2020 Intel Corporation
9 #include <rte_cpuflags.h>
10 #include <rte_common.h>
11 #include <rte_net_crc.h>
15 /** CRC polynomials */
16 #define CRC32_ETH_POLYNOMIAL 0x04c11db7UL
17 #define CRC16_CCITT_POLYNOMIAL 0x1021U
19 #define CRC_LUT_SIZE 256
22 static uint32_t crc32_eth_lut[CRC_LUT_SIZE];
23 static uint32_t crc16_ccitt_lut[CRC_LUT_SIZE];
26 rte_crc16_ccitt_handler(const uint8_t *data, uint32_t data_len);
29 rte_crc32_eth_handler(const uint8_t *data, uint32_t data_len);
32 (*rte_net_crc_handler)(const uint8_t *data, uint32_t data_len);
34 static const rte_net_crc_handler *handlers;
36 static const rte_net_crc_handler handlers_scalar[] = {
37 [RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_handler,
38 [RTE_NET_CRC32_ETH] = rte_crc32_eth_handler,
40 #ifdef CC_X86_64_AVX512_VPCLMULQDQ_SUPPORT
41 static const rte_net_crc_handler handlers_avx512[] = {
42 [RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_avx512_handler,
43 [RTE_NET_CRC32_ETH] = rte_crc32_eth_avx512_handler,
46 #ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT
47 static const rte_net_crc_handler handlers_sse42[] = {
48 [RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_sse42_handler,
49 [RTE_NET_CRC32_ETH] = rte_crc32_eth_sse42_handler,
52 #ifdef CC_ARM64_NEON_PMULL_SUPPORT
53 static const rte_net_crc_handler handlers_neon[] = {
54 [RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_neon_handler,
55 [RTE_NET_CRC32_ETH] = rte_crc32_eth_neon_handler,
62 * Reflect the bits about the middle
65 * value to be reflected
71 reflect_32bits(uint32_t val)
75 for (i = 0; i < 32; i++)
76 if ((val & (1U << i)) != 0)
77 res |= (uint32_t)(1U << (31 - i));
83 crc32_eth_init_lut(uint32_t poly,
88 for (i = 0; i < CRC_LUT_SIZE; i++) {
89 uint32_t crc = reflect_32bits(i);
91 for (j = 0; j < 8; j++) {
92 if (crc & 0x80000000L)
93 crc = (crc << 1) ^ poly;
97 lut[i] = reflect_32bits(crc);
101 static __rte_always_inline uint32_t
102 crc32_eth_calc_lut(const uint8_t *data,
108 crc = lut[(crc ^ *data++) & 0xffL] ^ (crc >> 8);
114 rte_net_crc_scalar_init(void)
116 /* 32-bit crc init */
117 crc32_eth_init_lut(CRC32_ETH_POLYNOMIAL, crc32_eth_lut);
119 /* 16-bit CRC init */
120 crc32_eth_init_lut(CRC16_CCITT_POLYNOMIAL << 16, crc16_ccitt_lut);
123 static inline uint32_t
124 rte_crc16_ccitt_handler(const uint8_t *data, uint32_t data_len)
126 /* return 16-bit CRC value */
127 return (uint16_t)~crc32_eth_calc_lut(data,
133 static inline uint32_t
134 rte_crc32_eth_handler(const uint8_t *data, uint32_t data_len)
136 /* return 32-bit CRC value */
137 return ~crc32_eth_calc_lut(data,
143 /* AVX512/VPCLMULQDQ handling */
145 #define AVX512_VPCLMULQDQ_CPU_SUPPORTED ( \
146 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) && \
147 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) && \
148 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512DQ) && \
149 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512VL) && \
150 rte_cpu_get_flag_enabled(RTE_CPUFLAG_PCLMULQDQ) && \
151 rte_cpu_get_flag_enabled(RTE_CPUFLAG_VPCLMULQDQ) \
154 static const rte_net_crc_handler *
155 avx512_vpclmulqdq_get_handlers(void)
157 #ifdef CC_X86_64_AVX512_VPCLMULQDQ_SUPPORT
158 if (AVX512_VPCLMULQDQ_CPU_SUPPORTED)
159 return handlers_avx512;
165 avx512_vpclmulqdq_init(void)
167 #ifdef CC_X86_64_AVX512_VPCLMULQDQ_SUPPORT
168 if (AVX512_VPCLMULQDQ_CPU_SUPPORTED) {
169 rte_net_crc_avx512_init();
176 /* SSE4.2/PCLMULQDQ handling */
178 #define SSE42_PCLMULQDQ_CPU_SUPPORTED \
179 rte_cpu_get_flag_enabled(RTE_CPUFLAG_PCLMULQDQ)
181 static const rte_net_crc_handler *
182 sse42_pclmulqdq_get_handlers(void)
184 #ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT
185 if (SSE42_PCLMULQDQ_CPU_SUPPORTED)
186 return handlers_sse42;
192 sse42_pclmulqdq_init(void)
194 #ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT
195 if (SSE42_PCLMULQDQ_CPU_SUPPORTED) {
196 rte_net_crc_sse42_init();
203 /* NEON/PMULL handling */
205 #define NEON_PMULL_CPU_SUPPORTED \
206 rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL)
208 static const rte_net_crc_handler *
209 neon_pmull_get_handlers(void)
211 #ifdef CC_ARM64_NEON_PMULL_SUPPORT
212 if (NEON_PMULL_CPU_SUPPORTED)
213 return handlers_neon;
219 neon_pmull_init(void)
221 #ifdef CC_ARM64_NEON_PMULL_SUPPORT
222 if (NEON_PMULL_CPU_SUPPORTED) {
223 rte_net_crc_neon_init();
233 rte_net_crc_set_alg(enum rte_net_crc_alg alg)
238 case RTE_NET_CRC_AVX512:
239 handlers = avx512_vpclmulqdq_get_handlers();
240 if (handlers != NULL)
243 case RTE_NET_CRC_SSE42:
244 handlers = sse42_pclmulqdq_get_handlers();
245 break; /* for x86, always break here */
246 case RTE_NET_CRC_NEON:
247 handlers = neon_pmull_get_handlers();
249 case RTE_NET_CRC_SCALAR:
255 if (handlers == NULL)
256 handlers = handlers_scalar;
260 rte_net_crc_calc(const void *data,
262 enum rte_net_crc_type type)
265 rte_net_crc_handler f_handle;
267 f_handle = handlers[type];
268 ret = f_handle(data, data_len);
273 /* Select highest available crc algorithm as default one */
274 RTE_INIT(rte_net_crc_init)
276 enum rte_net_crc_alg alg = RTE_NET_CRC_SCALAR;
278 rte_net_crc_scalar_init();
280 if (sse42_pclmulqdq_init())
281 alg = RTE_NET_CRC_SSE42;
282 if (avx512_vpclmulqdq_init())
283 alg = RTE_NET_CRC_AVX512;
284 if (neon_pmull_init())
285 alg = RTE_NET_CRC_NEON;
287 rte_net_crc_set_alg(alg);