1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Intel Corporation
9 #include <rte_cpuflags.h>
10 #include <rte_common.h>
11 #include <rte_net_crc.h>
13 #if defined(RTE_ARCH_X86_64) && defined(RTE_MACHINE_CPUFLAG_PCLMULQDQ)
14 #define X86_64_SSE42_PCLMULQDQ 1
15 #elif defined(RTE_ARCH_ARM64) && defined(RTE_MACHINE_CPUFLAG_PMULL)
16 #define ARM64_NEON_PMULL 1
19 #ifdef X86_64_SSE42_PCLMULQDQ
20 #include <net_crc_sse.h>
21 #elif defined ARM64_NEON_PMULL
22 #include <net_crc_neon.h>
25 /** CRC polynomials */
26 #define CRC32_ETH_POLYNOMIAL 0x04c11db7UL
27 #define CRC16_CCITT_POLYNOMIAL 0x1021U
29 #define CRC_LUT_SIZE 256
32 static uint32_t crc32_eth_lut[CRC_LUT_SIZE];
33 static uint32_t crc16_ccitt_lut[CRC_LUT_SIZE];
36 rte_crc16_ccitt_handler(const uint8_t *data, uint32_t data_len);
39 rte_crc32_eth_handler(const uint8_t *data, uint32_t data_len);
42 (*rte_net_crc_handler)(const uint8_t *data, uint32_t data_len);
44 static rte_net_crc_handler *handlers;
46 static rte_net_crc_handler handlers_scalar[] = {
47 [RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_handler,
48 [RTE_NET_CRC32_ETH] = rte_crc32_eth_handler,
51 #ifdef X86_64_SSE42_PCLMULQDQ
52 static rte_net_crc_handler handlers_sse42[] = {
53 [RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_sse42_handler,
54 [RTE_NET_CRC32_ETH] = rte_crc32_eth_sse42_handler,
56 #elif defined ARM64_NEON_PMULL
57 static rte_net_crc_handler handlers_neon[] = {
58 [RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_neon_handler,
59 [RTE_NET_CRC32_ETH] = rte_crc32_eth_neon_handler,
64 * Reflect the bits about the middle
67 * value to be reflected
73 reflect_32bits(uint32_t val)
77 for (i = 0; i < 32; i++)
78 if ((val & (1U << i)) != 0)
79 res |= (uint32_t)(1U << (31 - i));
85 crc32_eth_init_lut(uint32_t poly,
90 for (i = 0; i < CRC_LUT_SIZE; i++) {
91 uint32_t crc = reflect_32bits(i);
93 for (j = 0; j < 8; j++) {
94 if (crc & 0x80000000L)
95 crc = (crc << 1) ^ poly;
99 lut[i] = reflect_32bits(crc);
103 static __rte_always_inline uint32_t
104 crc32_eth_calc_lut(const uint8_t *data,
110 crc = lut[(crc ^ *data++) & 0xffL] ^ (crc >> 8);
116 rte_net_crc_scalar_init(void)
118 /* 32-bit crc init */
119 crc32_eth_init_lut(CRC32_ETH_POLYNOMIAL, crc32_eth_lut);
121 /* 16-bit CRC init */
122 crc32_eth_init_lut(CRC16_CCITT_POLYNOMIAL << 16, crc16_ccitt_lut);
125 static inline uint32_t
126 rte_crc16_ccitt_handler(const uint8_t *data, uint32_t data_len)
128 /* return 16-bit CRC value */
129 return (uint16_t)~crc32_eth_calc_lut(data,
135 static inline uint32_t
136 rte_crc32_eth_handler(const uint8_t *data, uint32_t data_len)
138 /* return 32-bit CRC value */
139 return ~crc32_eth_calc_lut(data,
146 rte_net_crc_set_alg(enum rte_net_crc_alg alg)
149 #ifdef X86_64_SSE42_PCLMULQDQ
150 case RTE_NET_CRC_SSE42:
151 handlers = handlers_sse42;
153 #elif defined ARM64_NEON_PMULL
155 case RTE_NET_CRC_NEON:
156 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL)) {
157 handlers = handlers_neon;
162 case RTE_NET_CRC_SCALAR:
165 handlers = handlers_scalar;
171 rte_net_crc_calc(const void *data,
173 enum rte_net_crc_type type)
176 rte_net_crc_handler f_handle;
178 f_handle = handlers[type];
179 ret = f_handle(data, data_len);
184 /* Select highest available crc algorithm as default one */
185 RTE_INIT(rte_net_crc_init)
187 enum rte_net_crc_alg alg = RTE_NET_CRC_SCALAR;
189 rte_net_crc_scalar_init();
191 #ifdef X86_64_SSE42_PCLMULQDQ
192 alg = RTE_NET_CRC_SSE42;
193 rte_net_crc_sse42_init();
194 #elif defined ARM64_NEON_PMULL
195 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL)) {
196 alg = RTE_NET_CRC_NEON;
197 rte_net_crc_neon_init();
201 rte_net_crc_set_alg(alg);