net/ixgbe: fix statistics in flow control mode
[dpdk.git] / lib / librte_net / rte_net_crc.c
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2017 Intel Corporation
3  */
4
5 #include <stddef.h>
6 #include <string.h>
7 #include <stdint.h>
8
9 #include <rte_cpuflags.h>
10 #include <rte_common.h>
11 #include <rte_net_crc.h>
12
13 #if defined(RTE_ARCH_X86_64) && defined(RTE_MACHINE_CPUFLAG_PCLMULQDQ)
14 #define X86_64_SSE42_PCLMULQDQ     1
15 #elif defined(RTE_ARCH_ARM64) && defined(RTE_MACHINE_CPUFLAG_PMULL)
16 #define ARM64_NEON_PMULL           1
17 #endif
18
19 #ifdef X86_64_SSE42_PCLMULQDQ
20 #include <net_crc_sse.h>
21 #elif defined ARM64_NEON_PMULL
22 #include <net_crc_neon.h>
23 #endif
24
25 /** CRC polynomials */
26 #define CRC32_ETH_POLYNOMIAL 0x04c11db7UL
27 #define CRC16_CCITT_POLYNOMIAL 0x1021U
28
29 #define CRC_LUT_SIZE 256
30
31 /* crc tables */
32 static uint32_t crc32_eth_lut[CRC_LUT_SIZE];
33 static uint32_t crc16_ccitt_lut[CRC_LUT_SIZE];
34
35 static uint32_t
36 rte_crc16_ccitt_handler(const uint8_t *data, uint32_t data_len);
37
38 static uint32_t
39 rte_crc32_eth_handler(const uint8_t *data, uint32_t data_len);
40
41 typedef uint32_t
42 (*rte_net_crc_handler)(const uint8_t *data, uint32_t data_len);
43
44 static rte_net_crc_handler *handlers;
45
46 static rte_net_crc_handler handlers_scalar[] = {
47         [RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_handler,
48         [RTE_NET_CRC32_ETH] = rte_crc32_eth_handler,
49 };
50
51 #ifdef X86_64_SSE42_PCLMULQDQ
52 static rte_net_crc_handler handlers_sse42[] = {
53         [RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_sse42_handler,
54         [RTE_NET_CRC32_ETH] = rte_crc32_eth_sse42_handler,
55 };
56 #elif defined ARM64_NEON_PMULL
57 static rte_net_crc_handler handlers_neon[] = {
58         [RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_neon_handler,
59         [RTE_NET_CRC32_ETH] = rte_crc32_eth_neon_handler,
60 };
61 #endif
62
63 /**
64  * Reflect the bits about the middle
65  *
66  * @param val
67  *   value to be reflected
68  *
69  * @return
70  *   reflected value
71  */
72 static uint32_t
73 reflect_32bits(uint32_t val)
74 {
75         uint32_t i, res = 0;
76
77         for (i = 0; i < 32; i++)
78                 if ((val & (1U << i)) != 0)
79                         res |= (uint32_t)(1U << (31 - i));
80
81         return res;
82 }
83
84 static void
85 crc32_eth_init_lut(uint32_t poly,
86         uint32_t *lut)
87 {
88         uint32_t i, j;
89
90         for (i = 0; i < CRC_LUT_SIZE; i++) {
91                 uint32_t crc = reflect_32bits(i);
92
93                 for (j = 0; j < 8; j++) {
94                         if (crc & 0x80000000L)
95                                 crc = (crc << 1) ^ poly;
96                         else
97                                 crc <<= 1;
98                 }
99                 lut[i] = reflect_32bits(crc);
100         }
101 }
102
103 static __rte_always_inline uint32_t
104 crc32_eth_calc_lut(const uint8_t *data,
105         uint32_t data_len,
106         uint32_t crc,
107         const uint32_t *lut)
108 {
109         while (data_len--)
110                 crc = lut[(crc ^ *data++) & 0xffL] ^ (crc >> 8);
111
112         return crc;
113 }
114
115 static void
116 rte_net_crc_scalar_init(void)
117 {
118         /* 32-bit crc init */
119         crc32_eth_init_lut(CRC32_ETH_POLYNOMIAL, crc32_eth_lut);
120
121         /* 16-bit CRC init */
122         crc32_eth_init_lut(CRC16_CCITT_POLYNOMIAL << 16, crc16_ccitt_lut);
123 }
124
125 static inline uint32_t
126 rte_crc16_ccitt_handler(const uint8_t *data, uint32_t data_len)
127 {
128         /* return 16-bit CRC value */
129         return (uint16_t)~crc32_eth_calc_lut(data,
130                 data_len,
131                 0xffff,
132                 crc16_ccitt_lut);
133 }
134
135 static inline uint32_t
136 rte_crc32_eth_handler(const uint8_t *data, uint32_t data_len)
137 {
138         /* return 32-bit CRC value */
139         return ~crc32_eth_calc_lut(data,
140                 data_len,
141                 0xffffffffUL,
142                 crc32_eth_lut);
143 }
144
145 void
146 rte_net_crc_set_alg(enum rte_net_crc_alg alg)
147 {
148         switch (alg) {
149 #ifdef X86_64_SSE42_PCLMULQDQ
150         case RTE_NET_CRC_SSE42:
151                 handlers = handlers_sse42;
152                 break;
153 #elif defined ARM64_NEON_PMULL
154                 /* fall-through */
155         case RTE_NET_CRC_NEON:
156                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL)) {
157                         handlers = handlers_neon;
158                         break;
159                 }
160 #endif
161                 /* fall-through */
162         case RTE_NET_CRC_SCALAR:
163                 /* fall-through */
164         default:
165                 handlers = handlers_scalar;
166                 break;
167         }
168 }
169
170 uint32_t
171 rte_net_crc_calc(const void *data,
172         uint32_t data_len,
173         enum rte_net_crc_type type)
174 {
175         uint32_t ret;
176         rte_net_crc_handler f_handle;
177
178         f_handle = handlers[type];
179         ret = f_handle(data, data_len);
180
181         return ret;
182 }
183
184 /* Select highest available crc algorithm as default one */
185 RTE_INIT(rte_net_crc_init)
186 {
187         enum rte_net_crc_alg alg = RTE_NET_CRC_SCALAR;
188
189         rte_net_crc_scalar_init();
190
191 #ifdef X86_64_SSE42_PCLMULQDQ
192         alg = RTE_NET_CRC_SSE42;
193         rte_net_crc_sse42_init();
194 #elif defined ARM64_NEON_PMULL
195         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL)) {
196                 alg = RTE_NET_CRC_NEON;
197                 rte_net_crc_neon_init();
198         }
199 #endif
200
201         rte_net_crc_set_alg(alg);
202 }