1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2015 Intel Corporation.
3 * Copyright 2013-2014 6WIND S.A.
21 #include <sys/queue.h>
23 #include <sys/types.h>
26 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
27 * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
28 * configuration space.
30 #define RTE_PCI_CFG_SPACE_SIZE 256
31 #define RTE_PCI_CFG_SPACE_EXP_SIZE 4096
33 #define RTE_PCI_VENDOR_ID 0x00 /* 16 bits */
34 #define RTE_PCI_DEVICE_ID 0x02 /* 16 bits */
36 /* PCI Express capability registers */
37 #define RTE_PCI_EXP_DEVCTL 8 /* Device Control */
39 /* Extended Capabilities (PCI-X 2.0 and Express) */
40 #define RTE_PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
41 #define RTE_PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
43 #define RTE_PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
44 #define RTE_PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
45 #define RTE_PCI_EXT_CAP_ID_SRIOV 0x10 /* SR-IOV*/
47 /* Single Root I/O Virtualization */
48 #define RTE_PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
49 #define RTE_PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */
50 #define RTE_PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */
51 #define RTE_PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */
52 #define RTE_PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */
53 #define RTE_PCI_SRIOV_FUNC_LINK 0x12 /* Function Dependency Link */
54 #define RTE_PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */
55 #define RTE_PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */
56 #define RTE_PCI_SRIOV_VF_DID 0x1a /* VF Device ID */
57 #define RTE_PCI_SRIOV_SUP_PGSIZE 0x1c /* Supported Page Sizes */
59 /** Formatting string for PCI device identifier: Ex: 0000:00:01.0 */
60 #define PCI_PRI_FMT "%.4" PRIx32 ":%.2" PRIx8 ":%.2" PRIx8 ".%" PRIx8
61 #define PCI_PRI_STR_SIZE sizeof("XXXXXXXX:XX:XX.X")
63 /** Short formatting string, without domain, for PCI device: Ex: 00:01.0 */
64 #define PCI_SHORT_PRI_FMT "%.2" PRIx8 ":%.2" PRIx8 ".%" PRIx8
66 /** Nb. of values in PCI device identifier format string. */
67 #define PCI_FMT_NVAL 4
69 /** Nb. of values in PCI resource format. */
70 #define PCI_RESOURCE_FMT_NVAL 3
72 /** Maximum number of PCI resources. */
73 #define PCI_MAX_RESOURCE 6
76 * A structure describing an ID for a PCI driver. Each driver provides a
77 * table of these IDs for each device that it supports.
80 uint32_t class_id; /**< Class ID or RTE_CLASS_ANY_ID. */
81 uint16_t vendor_id; /**< Vendor ID or PCI_ANY_ID. */
82 uint16_t device_id; /**< Device ID or PCI_ANY_ID. */
83 uint16_t subsystem_vendor_id; /**< Subsystem vendor ID or PCI_ANY_ID. */
84 uint16_t subsystem_device_id; /**< Subsystem device ID or PCI_ANY_ID. */
88 * A structure describing the location of a PCI device.
91 uint32_t domain; /**< Device domain */
92 uint8_t bus; /**< Device bus */
93 uint8_t devid; /**< Device ID */
94 uint8_t function; /**< Device function. */
97 /** Any PCI device identifier (vendor, device, ...) */
98 #define PCI_ANY_ID (0xffff)
99 #define RTE_CLASS_ANY_ID (0xffffff)
102 * Utility function to write a pci device name, this device name can later be
103 * used to retrieve the corresponding rte_pci_addr using eal_parse_pci_*
107 * The PCI Bus-Device-Function address
109 * The output buffer string
111 * The output buffer size
113 void rte_pci_device_name(const struct rte_pci_addr *addr,
114 char *output, size_t size);
117 * Utility function to compare two PCI device addresses.
120 * The PCI Bus-Device-Function address to compare
122 * The PCI Bus-Device-Function address to compare
124 * 0 on equal PCI address.
125 * Positive on addr is greater than addr2.
126 * Negative on addr is less than addr2, or error.
128 int rte_pci_addr_cmp(const struct rte_pci_addr *addr,
129 const struct rte_pci_addr *addr2);
133 * Utility function to parse a string into a PCI location.
136 * The string to parse
138 * The reference to the structure where the location
144 int rte_pci_addr_parse(const char *str, struct rte_pci_addr *addr);
150 #endif /* _RTE_PCI_H_ */