1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 /* 80003ES2LAN Gigabit Ethernet Controller (Copper)
35 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
38 #include "e1000_api.h"
40 STATIC s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw);
41 STATIC void e1000_release_phy_80003es2lan(struct e1000_hw *hw);
42 STATIC s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw);
43 STATIC void e1000_release_nvm_80003es2lan(struct e1000_hw *hw);
44 STATIC s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
47 STATIC s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
50 STATIC s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
51 u16 words, u16 *data);
52 STATIC s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw);
53 STATIC s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw);
54 STATIC s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw);
55 STATIC s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
57 STATIC s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw);
58 STATIC s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw);
59 STATIC s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
60 STATIC void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
61 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
62 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
63 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
64 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
65 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
67 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
69 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
70 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
71 STATIC s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw);
72 STATIC void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
74 /* A table for the GG82563 cable length where the range is defined
75 * with a lower bound at "index" and the upper bound at
78 static const u16 e1000_gg82563_cable_length_table[] = {
79 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
80 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
81 (sizeof(e1000_gg82563_cable_length_table) / \
82 sizeof(e1000_gg82563_cable_length_table[0]))
85 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
86 * @hw: pointer to the HW structure
88 STATIC s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
90 struct e1000_phy_info *phy = &hw->phy;
93 DEBUGFUNC("e1000_init_phy_params_80003es2lan");
95 if (hw->phy.media_type != e1000_media_type_copper) {
96 phy->type = e1000_phy_none;
99 phy->ops.power_up = e1000_power_up_phy_copper;
100 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
104 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
105 phy->reset_delay_us = 100;
106 phy->type = e1000_phy_gg82563;
108 phy->ops.acquire = e1000_acquire_phy_80003es2lan;
109 phy->ops.check_polarity = e1000_check_polarity_m88;
110 phy->ops.check_reset_block = e1000_check_reset_block_generic;
111 phy->ops.commit = e1000_phy_sw_reset_generic;
112 phy->ops.get_cfg_done = e1000_get_cfg_done_80003es2lan;
113 phy->ops.get_info = e1000_get_phy_info_m88;
114 phy->ops.release = e1000_release_phy_80003es2lan;
115 phy->ops.reset = e1000_phy_hw_reset_generic;
116 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
118 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan;
119 phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan;
120 phy->ops.read_reg = e1000_read_phy_reg_gg82563_80003es2lan;
121 phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan;
123 phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan;
125 /* This can only be done after all function pointers are setup. */
126 ret_val = e1000_get_phy_id(hw);
129 if (phy->id != GG82563_E_PHY_ID)
130 return -E1000_ERR_PHY;
136 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
137 * @hw: pointer to the HW structure
139 STATIC s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
141 struct e1000_nvm_info *nvm = &hw->nvm;
142 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
145 DEBUGFUNC("e1000_init_nvm_params_80003es2lan");
147 nvm->opcode_bits = 8;
149 switch (nvm->override) {
150 case e1000_nvm_override_spi_large:
152 nvm->address_bits = 16;
154 case e1000_nvm_override_spi_small:
156 nvm->address_bits = 8;
159 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
160 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
164 nvm->type = e1000_nvm_eeprom_spi;
166 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
167 E1000_EECD_SIZE_EX_SHIFT);
169 /* Added to a constant, "size" becomes the left-shift value
170 * for setting word_size.
172 size += NVM_WORD_SIZE_BASE_SHIFT;
174 /* EEPROM access above 16k is unsupported */
177 nvm->word_size = 1 << size;
179 /* Function Pointers */
180 nvm->ops.acquire = e1000_acquire_nvm_80003es2lan;
181 nvm->ops.read = e1000_read_nvm_eerd;
182 nvm->ops.release = e1000_release_nvm_80003es2lan;
183 nvm->ops.update = e1000_update_nvm_checksum_generic;
184 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
185 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
186 nvm->ops.write = e1000_write_nvm_80003es2lan;
188 return E1000_SUCCESS;
192 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
193 * @hw: pointer to the HW structure
195 STATIC s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
197 struct e1000_mac_info *mac = &hw->mac;
199 DEBUGFUNC("e1000_init_mac_params_80003es2lan");
201 /* Set media type and media-dependent function pointers */
202 switch (hw->device_id) {
203 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
204 hw->phy.media_type = e1000_media_type_internal_serdes;
205 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
206 mac->ops.setup_physical_interface =
207 e1000_setup_fiber_serdes_link_generic;
210 hw->phy.media_type = e1000_media_type_copper;
211 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
212 mac->ops.setup_physical_interface =
213 e1000_setup_copper_link_80003es2lan;
217 /* Set mta register count */
218 mac->mta_reg_count = 128;
219 /* Set rar entry count */
220 mac->rar_entry_count = E1000_RAR_ENTRIES;
221 /* Set if part includes ASF firmware */
222 mac->asf_firmware_present = true;
224 mac->has_fwsm = true;
225 /* ARC supported; valid only if manageability features are enabled. */
226 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) &
227 E1000_FWSM_MODE_MASK);
228 /* Adaptive IFS not supported */
229 mac->adaptive_ifs = false;
231 /* Function pointers */
233 /* bus type/speed/width */
234 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
236 mac->ops.reset_hw = e1000_reset_hw_80003es2lan;
237 /* hw initialization */
238 mac->ops.init_hw = e1000_init_hw_80003es2lan;
240 mac->ops.setup_link = e1000_setup_link_generic;
241 /* check management mode */
242 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
243 /* multicast address update */
244 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
246 mac->ops.write_vfta = e1000_write_vfta_generic;
248 mac->ops.clear_vfta = e1000_clear_vfta_generic;
249 /* read mac address */
250 mac->ops.read_mac_addr = e1000_read_mac_addr_80003es2lan;
252 mac->ops.id_led_init = e1000_id_led_init_generic;
254 mac->ops.blink_led = e1000_blink_led_generic;
256 mac->ops.setup_led = e1000_setup_led_generic;
258 mac->ops.cleanup_led = e1000_cleanup_led_generic;
259 /* turn on/off LED */
260 mac->ops.led_on = e1000_led_on_generic;
261 mac->ops.led_off = e1000_led_off_generic;
262 /* clear hardware counters */
263 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan;
265 mac->ops.get_link_up_info = e1000_get_link_up_info_80003es2lan;
267 /* set lan id for port to determine which phy lock to use */
268 hw->mac.ops.set_lan_id(hw);
270 return E1000_SUCCESS;
274 * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs.
275 * @hw: pointer to the HW structure
277 * Called to initialize all function pointers and parameters.
279 void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw)
281 DEBUGFUNC("e1000_init_function_pointers_80003es2lan");
283 hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan;
284 hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan;
285 hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan;
289 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
290 * @hw: pointer to the HW structure
292 * A wrapper to acquire access rights to the correct PHY.
294 STATIC s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
298 DEBUGFUNC("e1000_acquire_phy_80003es2lan");
300 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
301 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
305 * e1000_release_phy_80003es2lan - Release rights to access PHY
306 * @hw: pointer to the HW structure
308 * A wrapper to release access rights to the correct PHY.
310 STATIC void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
314 DEBUGFUNC("e1000_release_phy_80003es2lan");
316 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
317 e1000_release_swfw_sync_80003es2lan(hw, mask);
321 * e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register
322 * @hw: pointer to the HW structure
324 * Acquire the semaphore to access the Kumeran interface.
327 STATIC s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
331 DEBUGFUNC("e1000_acquire_mac_csr_80003es2lan");
333 mask = E1000_SWFW_CSR_SM;
335 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
339 * e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register
340 * @hw: pointer to the HW structure
342 * Release the semaphore used to access the Kumeran interface
344 STATIC void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
348 DEBUGFUNC("e1000_release_mac_csr_80003es2lan");
350 mask = E1000_SWFW_CSR_SM;
352 e1000_release_swfw_sync_80003es2lan(hw, mask);
356 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
357 * @hw: pointer to the HW structure
359 * Acquire the semaphore to access the EEPROM.
361 STATIC s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
365 DEBUGFUNC("e1000_acquire_nvm_80003es2lan");
367 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
371 ret_val = e1000_acquire_nvm_generic(hw);
374 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
380 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
381 * @hw: pointer to the HW structure
383 * Release the semaphore used to access the EEPROM.
385 STATIC void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
387 DEBUGFUNC("e1000_release_nvm_80003es2lan");
389 e1000_release_nvm_generic(hw);
390 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
394 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
395 * @hw: pointer to the HW structure
396 * @mask: specifies which semaphore to acquire
398 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
399 * will also specify which port we're acquiring the lock for.
401 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
405 u32 fwmask = mask << 16;
409 DEBUGFUNC("e1000_acquire_swfw_sync_80003es2lan");
411 while (i < timeout) {
412 if (e1000_get_hw_semaphore_generic(hw))
413 return -E1000_ERR_SWFW_SYNC;
415 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
416 if (!(swfw_sync & (fwmask | swmask)))
419 /* Firmware currently using resource (fwmask)
420 * or other software thread using resource (swmask)
422 e1000_put_hw_semaphore_generic(hw);
428 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
429 return -E1000_ERR_SWFW_SYNC;
433 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
435 e1000_put_hw_semaphore_generic(hw);
437 return E1000_SUCCESS;
441 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
442 * @hw: pointer to the HW structure
443 * @mask: specifies which semaphore to acquire
445 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
446 * will also specify which port we're releasing the lock for.
448 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
452 DEBUGFUNC("e1000_release_swfw_sync_80003es2lan");
454 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
457 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
459 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
461 e1000_put_hw_semaphore_generic(hw);
465 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
466 * @hw: pointer to the HW structure
467 * @offset: offset of the register to read
468 * @data: pointer to the data returned from the operation
470 * Read the GG82563 PHY register.
472 STATIC s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
473 u32 offset, u16 *data)
479 DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan");
481 ret_val = e1000_acquire_phy_80003es2lan(hw);
485 /* Select Configuration Page */
486 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
487 page_select = GG82563_PHY_PAGE_SELECT;
489 /* Use Alternative Page Select register to access
490 * registers 30 and 31
492 page_select = GG82563_PHY_PAGE_SELECT_ALT;
495 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
496 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
498 e1000_release_phy_80003es2lan(hw);
502 if (hw->dev_spec._80003es2lan.mdic_wa_enable) {
503 /* The "ready" bit in the MDIC register may be incorrectly set
504 * before the device has completed the "Page Select" MDI
505 * transaction. So we wait 200us after each MDI command...
509 /* ...and verify the command was successful. */
510 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
512 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
513 e1000_release_phy_80003es2lan(hw);
514 return -E1000_ERR_PHY;
519 ret_val = e1000_read_phy_reg_mdic(hw,
520 MAX_PHY_REG_ADDRESS & offset,
525 ret_val = e1000_read_phy_reg_mdic(hw,
526 MAX_PHY_REG_ADDRESS & offset,
530 e1000_release_phy_80003es2lan(hw);
536 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
537 * @hw: pointer to the HW structure
538 * @offset: offset of the register to read
539 * @data: value to write to the register
541 * Write to the GG82563 PHY register.
543 STATIC s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
544 u32 offset, u16 data)
550 DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan");
552 ret_val = e1000_acquire_phy_80003es2lan(hw);
556 /* Select Configuration Page */
557 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
558 page_select = GG82563_PHY_PAGE_SELECT;
560 /* Use Alternative Page Select register to access
561 * registers 30 and 31
563 page_select = GG82563_PHY_PAGE_SELECT_ALT;
566 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
567 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
569 e1000_release_phy_80003es2lan(hw);
573 if (hw->dev_spec._80003es2lan.mdic_wa_enable) {
574 /* The "ready" bit in the MDIC register may be incorrectly set
575 * before the device has completed the "Page Select" MDI
576 * transaction. So we wait 200us after each MDI command...
580 /* ...and verify the command was successful. */
581 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
583 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
584 e1000_release_phy_80003es2lan(hw);
585 return -E1000_ERR_PHY;
590 ret_val = e1000_write_phy_reg_mdic(hw,
591 MAX_PHY_REG_ADDRESS & offset,
596 ret_val = e1000_write_phy_reg_mdic(hw,
597 MAX_PHY_REG_ADDRESS & offset,
601 e1000_release_phy_80003es2lan(hw);
607 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM
608 * @hw: pointer to the HW structure
609 * @offset: offset of the register to read
610 * @words: number of words to write
611 * @data: buffer of data to write to the NVM
613 * Write "words" of data to the ESB2 NVM.
615 STATIC s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
616 u16 words, u16 *data)
618 DEBUGFUNC("e1000_write_nvm_80003es2lan");
620 return e1000_write_nvm_spi(hw, offset, words, data);
624 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
625 * @hw: pointer to the HW structure
627 * Wait a specific amount of time for manageability processes to complete.
628 * This is a function pointer entry point called by the phy module.
630 STATIC s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
632 s32 timeout = PHY_CFG_TIMEOUT;
633 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
635 DEBUGFUNC("e1000_get_cfg_done_80003es2lan");
637 if (hw->bus.func == 1)
638 mask = E1000_NVM_CFG_DONE_PORT_1;
641 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
647 DEBUGOUT("MNG configuration cycle has not completed.\n");
648 return -E1000_ERR_RESET;
651 return E1000_SUCCESS;
655 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
656 * @hw: pointer to the HW structure
658 * Force the speed and duplex settings onto the PHY. This is a
659 * function pointer entry point called by the phy module.
661 STATIC s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
667 DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan");
669 if (!(hw->phy.ops.read_reg))
670 return E1000_SUCCESS;
672 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
673 * forced whenever speed and duplex are forced.
675 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
679 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
680 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
684 DEBUGOUT1("GG82563 PSCR: %X\n", phy_data);
686 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data);
690 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
692 /* Reset the phy to commit changes. */
693 phy_data |= MII_CR_RESET;
695 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data);
701 if (hw->phy.autoneg_wait_to_complete) {
702 DEBUGOUT("Waiting for forced speed/duplex link on GG82563 phy.\n");
704 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
710 /* We didn't get link.
711 * Reset the DSP and cross our fingers.
713 ret_val = e1000_phy_reset_dsp_generic(hw);
719 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
725 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
730 /* Resetting the phy means we need to verify the TX_CLK corresponds
731 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
733 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
734 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
735 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
737 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
739 /* In addition, we must re-enable CRS on Tx for both half and full
742 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
743 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
750 * e1000_get_cable_length_80003es2lan - Set approximate cable length
751 * @hw: pointer to the HW structure
753 * Find the approximate cable length as measured by the GG82563 PHY.
754 * This is a function pointer entry point called by the phy module.
756 STATIC s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
758 struct e1000_phy_info *phy = &hw->phy;
762 DEBUGFUNC("e1000_get_cable_length_80003es2lan");
764 if (!(hw->phy.ops.read_reg))
765 return E1000_SUCCESS;
767 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
771 index = phy_data & GG82563_DSPD_CABLE_LENGTH;
773 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5)
774 return -E1000_ERR_PHY;
776 phy->min_cable_length = e1000_gg82563_cable_length_table[index];
777 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
779 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
781 return E1000_SUCCESS;
785 * e1000_get_link_up_info_80003es2lan - Report speed and duplex
786 * @hw: pointer to the HW structure
787 * @speed: pointer to speed buffer
788 * @duplex: pointer to duplex buffer
790 * Retrieve the current speed and duplex configuration.
792 STATIC s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
797 DEBUGFUNC("e1000_get_link_up_info_80003es2lan");
799 if (hw->phy.media_type == e1000_media_type_copper) {
800 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
802 hw->phy.ops.cfg_on_link_up(hw);
804 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw,
813 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
814 * @hw: pointer to the HW structure
816 * Perform a global reset to the ESB2 controller.
818 STATIC s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
824 DEBUGFUNC("e1000_reset_hw_80003es2lan");
826 /* Prevent the PCI-E bus from sticking if there is no TLP connection
827 * on the last TLP read/write transaction when MAC is reset.
829 ret_val = e1000_disable_pcie_master_generic(hw);
831 DEBUGOUT("PCI-E Master disable polling has failed.\n");
833 DEBUGOUT("Masking off all interrupts\n");
834 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
836 E1000_WRITE_REG(hw, E1000_RCTL, 0);
837 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
838 E1000_WRITE_FLUSH(hw);
842 ctrl = E1000_READ_REG(hw, E1000_CTRL);
844 ret_val = e1000_acquire_phy_80003es2lan(hw);
845 DEBUGOUT("Issuing a global reset to MAC\n");
846 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
847 e1000_release_phy_80003es2lan(hw);
849 /* Disable IBIST slave mode (far-end loopback) */
850 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
852 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
853 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
856 ret_val = e1000_get_auto_rd_done_generic(hw);
858 /* We don't want to continue accessing MAC registers. */
861 /* Clear any pending interrupt events. */
862 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
863 E1000_READ_REG(hw, E1000_ICR);
865 return e1000_check_alt_mac_addr_generic(hw);
869 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
870 * @hw: pointer to the HW structure
872 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
874 STATIC s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
876 struct e1000_mac_info *mac = &hw->mac;
882 DEBUGFUNC("e1000_init_hw_80003es2lan");
884 e1000_initialize_hw_bits_80003es2lan(hw);
886 /* Initialize identification LED */
887 ret_val = mac->ops.id_led_init(hw);
888 /* An error is not fatal and we should not stop init due to this */
890 DEBUGOUT("Error initializing identification LED\n");
892 /* Disabling VLAN filtering */
893 DEBUGOUT("Initializing the IEEE VLAN\n");
894 mac->ops.clear_vfta(hw);
896 /* Setup the receive address. */
897 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
899 /* Zero out the Multicast HASH table */
900 DEBUGOUT("Zeroing the MTA\n");
901 for (i = 0; i < mac->mta_reg_count; i++)
902 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
904 /* Setup link and flow control */
905 ret_val = mac->ops.setup_link(hw);
907 /* Disable IBIST slave mode (far-end loopback) */
908 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
910 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
911 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
914 /* Set the transmit descriptor write-back policy */
915 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
916 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
917 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
918 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
920 /* ...for both queues. */
921 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
922 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
923 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
924 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
926 /* Enable retransmit on late collisions */
927 reg_data = E1000_READ_REG(hw, E1000_TCTL);
928 reg_data |= E1000_TCTL_RTLC;
929 E1000_WRITE_REG(hw, E1000_TCTL, reg_data);
931 /* Configure Gigabit Carry Extend Padding */
932 reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT);
933 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
934 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
935 E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data);
937 /* Configure Transmit Inter-Packet Gap */
938 reg_data = E1000_READ_REG(hw, E1000_TIPG);
939 reg_data &= ~E1000_TIPG_IPGT_MASK;
940 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
941 E1000_WRITE_REG(hw, E1000_TIPG, reg_data);
943 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
944 reg_data &= ~0x00100000;
945 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
947 /* default to true to enable the MDIC W/A */
948 hw->dev_spec._80003es2lan.mdic_wa_enable = true;
951 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >>
952 E1000_KMRNCTRLSTA_OFFSET_SHIFT, &i);
954 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
955 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
956 hw->dev_spec._80003es2lan.mdic_wa_enable = false;
959 /* Clear all of the statistics registers (clear on read). It is
960 * important that we do this after we have tried to establish link
961 * because the symbol error count will increment wildly if there
964 e1000_clear_hw_cntrs_80003es2lan(hw);
970 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
971 * @hw: pointer to the HW structure
973 * Initializes required hardware-dependent bits needed for normal operation.
975 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
979 DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan");
981 /* Transmit Descriptor Control 0 */
982 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
984 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
986 /* Transmit Descriptor Control 1 */
987 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
989 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
991 /* Transmit Arbitration Control 0 */
992 reg = E1000_READ_REG(hw, E1000_TARC(0));
993 reg &= ~(0xF << 27); /* 30:27 */
994 if (hw->phy.media_type != e1000_media_type_copper)
996 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
998 /* Transmit Arbitration Control 1 */
999 reg = E1000_READ_REG(hw, E1000_TARC(1));
1000 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1004 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1006 /* Disable IPv6 extension header parsing because some malformed
1007 * IPv6 headers can hang the Rx.
1009 reg = E1000_READ_REG(hw, E1000_RFCTL);
1010 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1011 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
1017 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
1018 * @hw: pointer to the HW structure
1020 * Setup some GG82563 PHY registers for obtaining link
1022 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
1024 struct e1000_phy_info *phy = &hw->phy;
1029 DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan");
1031 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
1035 data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1036 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
1037 data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
1039 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
1044 * MDI/MDI-X = 0 (default)
1045 * 0 - Auto for all speeds
1048 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1050 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data);
1054 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1056 switch (phy->mdix) {
1058 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1061 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1065 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1070 * disable_polarity_correction = 0 (default)
1071 * Automatic Correction for Reversed Cable Polarity
1075 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1076 if (phy->disable_polarity_correction)
1077 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1079 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data);
1083 /* SW Reset the PHY so all changes take effect */
1084 ret_val = hw->phy.ops.commit(hw);
1086 DEBUGOUT("Error Resetting the PHY\n");
1090 /* Bypass Rx and Tx FIFO's */
1091 reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL;
1092 data = (E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1093 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1094 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
1098 reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE;
1099 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data);
1102 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1103 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
1107 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1111 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1112 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data);
1116 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1117 reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1118 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1120 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1124 /* Do not init these registers when the HW is in IAMT mode, since the
1125 * firmware will have already initialized them. We only initialize
1126 * them if the HW is not in IAMT mode.
1128 if (!hw->mac.ops.check_mng_mode(hw)) {
1129 /* Enable Electrical Idle on the PHY */
1130 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1131 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1136 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1141 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1142 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1148 /* Workaround: Disable padding in Kumeran interface in the MAC
1149 * and in the PHY to avoid CRC errors.
1151 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data);
1155 data |= GG82563_ICR_DIS_PADDING;
1156 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data);
1160 return E1000_SUCCESS;
1164 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1165 * @hw: pointer to the HW structure
1167 * Essentially a wrapper for setting up all things "copper" related.
1168 * This is a function pointer entry point called by the mac module.
1170 STATIC s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1176 DEBUGFUNC("e1000_setup_copper_link_80003es2lan");
1178 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1179 ctrl |= E1000_CTRL_SLU;
1180 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1181 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1183 /* Set the mac to wait the maximum time between each
1184 * iteration and increase the max iterations when
1185 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1187 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1191 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1196 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1201 e1000_read_kmrn_reg_80003es2lan(hw,
1202 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1206 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1208 e1000_write_kmrn_reg_80003es2lan(hw,
1209 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1214 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1218 return e1000_setup_copper_link_generic(hw);
1222 * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1223 * @hw: pointer to the HW structure
1224 * @duplex: current duplex setting
1226 * Configure the KMRN interface by applying last minute quirks for
1229 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1231 s32 ret_val = E1000_SUCCESS;
1235 DEBUGFUNC("e1000_configure_on_link_up");
1237 if (hw->phy.media_type == e1000_media_type_copper) {
1238 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, &speed,
1243 if (speed == SPEED_1000)
1244 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1246 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1253 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1254 * @hw: pointer to the HW structure
1255 * @duplex: current duplex setting
1257 * Configure the KMRN interface by applying last minute quirks for
1260 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1265 u16 reg_data, reg_data2;
1267 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
1269 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1271 e1000_write_kmrn_reg_80003es2lan(hw,
1272 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1277 /* Configure Transmit Inter-Packet Gap */
1278 tipg = E1000_READ_REG(hw, E1000_TIPG);
1279 tipg &= ~E1000_TIPG_IPGT_MASK;
1280 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1281 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1284 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1289 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1294 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1296 if (duplex == HALF_DUPLEX)
1297 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1299 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1301 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1305 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1306 * @hw: pointer to the HW structure
1308 * Configure the KMRN interface by applying last minute quirks for
1309 * gigabit operation.
1311 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1314 u16 reg_data, reg_data2;
1318 DEBUGFUNC("e1000_configure_kmrn_for_1000");
1320 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1322 e1000_write_kmrn_reg_80003es2lan(hw,
1323 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1328 /* Configure Transmit Inter-Packet Gap */
1329 tipg = E1000_READ_REG(hw, E1000_TIPG);
1330 tipg &= ~E1000_TIPG_IPGT_MASK;
1331 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1332 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1335 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1340 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1345 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1347 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1349 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1353 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1354 * @hw: pointer to the HW structure
1355 * @offset: register offset to be read
1356 * @data: pointer to the read data
1358 * Acquire semaphore, then read the PHY register at offset
1359 * using the kumeran interface. The information retrieved is stored in data.
1360 * Release the semaphore before exiting.
1362 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1368 DEBUGFUNC("e1000_read_kmrn_reg_80003es2lan");
1370 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1374 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1375 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1376 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1377 E1000_WRITE_FLUSH(hw);
1381 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
1382 *data = (u16)kmrnctrlsta;
1384 e1000_release_mac_csr_80003es2lan(hw);
1390 * e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1391 * @hw: pointer to the HW structure
1392 * @offset: register offset to write to
1393 * @data: data to write at register offset
1395 * Acquire semaphore, then write the data to PHY register
1396 * at the offset using the kumeran interface. Release semaphore
1399 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1405 DEBUGFUNC("e1000_write_kmrn_reg_80003es2lan");
1407 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1411 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1412 E1000_KMRNCTRLSTA_OFFSET) | data;
1413 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1414 E1000_WRITE_FLUSH(hw);
1418 e1000_release_mac_csr_80003es2lan(hw);
1424 * e1000_read_mac_addr_80003es2lan - Read device MAC address
1425 * @hw: pointer to the HW structure
1427 STATIC s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1431 DEBUGFUNC("e1000_read_mac_addr_80003es2lan");
1433 /* If there's an alternate MAC address place it in RAR0
1434 * so that it will override the Si installed default perm
1437 ret_val = e1000_check_alt_mac_addr_generic(hw);
1441 return e1000_read_mac_addr_generic(hw);
1445 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1446 * @hw: pointer to the HW structure
1448 * In the case of a PHY power down to save power, or to turn off link during a
1449 * driver unload, or wake on lan is not enabled, remove the link.
1451 STATIC void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1453 /* If the management interface is not enabled, then power down */
1454 if (!(hw->mac.ops.check_mng_mode(hw) ||
1455 hw->phy.ops.check_reset_block(hw)))
1456 e1000_power_down_phy_copper(hw);
1462 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1463 * @hw: pointer to the HW structure
1465 * Clears the hardware counters by reading the counter registers.
1467 STATIC void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1469 DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan");
1471 e1000_clear_hw_cntrs_base_generic(hw);
1473 E1000_READ_REG(hw, E1000_PRC64);
1474 E1000_READ_REG(hw, E1000_PRC127);
1475 E1000_READ_REG(hw, E1000_PRC255);
1476 E1000_READ_REG(hw, E1000_PRC511);
1477 E1000_READ_REG(hw, E1000_PRC1023);
1478 E1000_READ_REG(hw, E1000_PRC1522);
1479 E1000_READ_REG(hw, E1000_PTC64);
1480 E1000_READ_REG(hw, E1000_PTC127);
1481 E1000_READ_REG(hw, E1000_PTC255);
1482 E1000_READ_REG(hw, E1000_PTC511);
1483 E1000_READ_REG(hw, E1000_PTC1023);
1484 E1000_READ_REG(hw, E1000_PTC1522);
1486 E1000_READ_REG(hw, E1000_ALGNERRC);
1487 E1000_READ_REG(hw, E1000_RXERRC);
1488 E1000_READ_REG(hw, E1000_TNCRS);
1489 E1000_READ_REG(hw, E1000_CEXTERR);
1490 E1000_READ_REG(hw, E1000_TSCTC);
1491 E1000_READ_REG(hw, E1000_TSCTFC);
1493 E1000_READ_REG(hw, E1000_MGTPRC);
1494 E1000_READ_REG(hw, E1000_MGTPDC);
1495 E1000_READ_REG(hw, E1000_MGTPTC);
1497 E1000_READ_REG(hw, E1000_IAC);
1498 E1000_READ_REG(hw, E1000_ICRXOC);
1500 E1000_READ_REG(hw, E1000_ICRXPTC);
1501 E1000_READ_REG(hw, E1000_ICRXATC);
1502 E1000_READ_REG(hw, E1000_ICTXPTC);
1503 E1000_READ_REG(hw, E1000_ICTXATC);
1504 E1000_READ_REG(hw, E1000_ICTXQEC);
1505 E1000_READ_REG(hw, E1000_ICTXQMTC);
1506 E1000_READ_REG(hw, E1000_ICRXDMTC);