lib/librte_pmd_e1000/e1000/e1000_80003es2lan.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2012, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 /* 80003ES2LAN Gigabit Ethernet Controller (Copper)
  35  * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
  36  */
  37
  38 #include "e1000_api.h"
  39
  40 STATIC s32  e1000_acquire_phy_80003es2lan(struct e1000_hw *hw);
  41 STATIC void e1000_release_phy_80003es2lan(struct e1000_hw *hw);
  42 STATIC s32  e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw);
  43 STATIC void e1000_release_nvm_80003es2lan(struct e1000_hw *hw);
  44 STATIC s32  e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
  45                                                    u32 offset,
  46                                                    u16 *data);
  47 STATIC s32  e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
  48                                                     u32 offset,
  49                                                     u16 data);
  50 STATIC s32  e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
  51                                         u16 words, u16 *data);
  52 STATIC s32  e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw);
  53 STATIC s32  e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw);
  54 STATIC s32  e1000_get_cable_length_80003es2lan(struct e1000_hw *hw);
  55 STATIC s32  e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
  56                                                u16 *duplex);
  57 STATIC s32  e1000_reset_hw_80003es2lan(struct e1000_hw *hw);
  58 STATIC s32  e1000_init_hw_80003es2lan(struct e1000_hw *hw);
  59 STATIC s32  e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
  60 STATIC void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
  61 STATIC s32  e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
  62 STATIC s32  e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
  63 STATIC s32  e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
  64 STATIC s32  e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
  65 STATIC s32  e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
  66                                             u16 *data);
  67 STATIC s32  e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
  68                                              u16 data);
  69 STATIC void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
  70 STATIC void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
  71 STATIC s32  e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw);
  72 STATIC void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
  73
  74 /* A table for the GG82563 cable length where the range is defined
  75  * with a lower bound at "index" and the upper bound at
  76  * "index + 5".
  77  */
  78 STATIC const u16 e1000_gg82563_cable_length_table[] = {
  79         0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
  80 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
  81                 (sizeof(e1000_gg82563_cable_length_table) / \
  82                  sizeof(e1000_gg82563_cable_length_table[0]))
  83
  84 /**
  85  *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
  86  *  @hw: pointer to the HW structure
  87  **/
  88 STATIC s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
  89 {
  90         struct e1000_phy_info *phy = &hw->phy;
  91         s32 ret_val;
  92
  93         DEBUGFUNC("e1000_init_phy_params_80003es2lan");
  94
  95         if (hw->phy.media_type != e1000_media_type_copper) {
  96                 phy->type = e1000_phy_none;
  97                 return E1000_SUCCESS;
  98         } else {
  99                 phy->ops.power_up = e1000_power_up_phy_copper;
 100                 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
 101         }
 102
 103         phy->addr               = 1;
 104         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 105         phy->reset_delay_us     = 100;
 106         phy->type               = e1000_phy_gg82563;
 107
 108         phy->ops.acquire        = e1000_acquire_phy_80003es2lan;
 109         phy->ops.check_polarity = e1000_check_polarity_m88;
 110         phy->ops.check_reset_block = e1000_check_reset_block_generic;
 111         phy->ops.commit         = e1000_phy_sw_reset_generic;
 112         phy->ops.get_cfg_done   = e1000_get_cfg_done_80003es2lan;
 113         phy->ops.get_info       = e1000_get_phy_info_m88;
 114         phy->ops.release        = e1000_release_phy_80003es2lan;
 115         phy->ops.reset          = e1000_phy_hw_reset_generic;
 116         phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
 117
 118         phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan;
 119         phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan;
 120         phy->ops.read_reg       = e1000_read_phy_reg_gg82563_80003es2lan;
 121         phy->ops.write_reg      = e1000_write_phy_reg_gg82563_80003es2lan;
 122
 123         phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan;
 124
 125         /* This can only be done after all function pointers are setup. */
 126         ret_val = e1000_get_phy_id(hw);
 127
 128         /* Verify phy id */
 129         if (phy->id != GG82563_E_PHY_ID)
 130                 return -E1000_ERR_PHY;
 131
 132         return ret_val;
 133 }
 134
 135 /**
 136  *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
 137  *  @hw: pointer to the HW structure
 138  **/
 139 STATIC s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
 140 {
 141         struct e1000_nvm_info *nvm = &hw->nvm;
 142         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 143         u16 size;
 144
 145         DEBUGFUNC("e1000_init_nvm_params_80003es2lan");
 146
 147         nvm->opcode_bits = 8;
 148         nvm->delay_usec = 1;
 149         switch (nvm->override) {
 150         case e1000_nvm_override_spi_large:
 151                 nvm->page_size = 32;
 152                 nvm->address_bits = 16;
 153                 break;
 154         case e1000_nvm_override_spi_small:
 155                 nvm->page_size = 8;
 156                 nvm->address_bits = 8;
 157                 break;
 158         default:
 159                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 160                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 161                 break;
 162         }
 163
 164         nvm->type = e1000_nvm_eeprom_spi;
 165
 166         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 167                      E1000_EECD_SIZE_EX_SHIFT);
 168
 169         /* Added to a constant, "size" becomes the left-shift value
 170          * for setting word_size.
 171          */
 172         size += NVM_WORD_SIZE_BASE_SHIFT;
 173
 174         /* EEPROM access above 16k is unsupported */
 175         if (size > 14)
 176                 size = 14;
 177         nvm->word_size = 1 << size;
 178
 179         /* Function Pointers */
 180         nvm->ops.acquire        = e1000_acquire_nvm_80003es2lan;
 181         nvm->ops.read           = e1000_read_nvm_eerd;
 182         nvm->ops.release        = e1000_release_nvm_80003es2lan;
 183         nvm->ops.update         = e1000_update_nvm_checksum_generic;
 184         nvm->ops.valid_led_default = e1000_valid_led_default_generic;
 185         nvm->ops.validate       = e1000_validate_nvm_checksum_generic;
 186         nvm->ops.write          = e1000_write_nvm_80003es2lan;
 187
 188         return E1000_SUCCESS;
 189 }
 190
 191 /**
 192  *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
 193  *  @hw: pointer to the HW structure
 194  **/
 195 STATIC s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
 196 {
 197         struct e1000_mac_info *mac = &hw->mac;
 198
 199         DEBUGFUNC("e1000_init_mac_params_80003es2lan");
 200
 201         /* Set media type and media-dependent function pointers */
 202         switch (hw->device_id) {
 203         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
 204                 hw->phy.media_type = e1000_media_type_internal_serdes;
 205                 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
 206                 mac->ops.setup_physical_interface =
 207                                         e1000_setup_fiber_serdes_link_generic;
 208                 break;
 209         default:
 210                 hw->phy.media_type = e1000_media_type_copper;
 211                 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
 212                 mac->ops.setup_physical_interface =
 213                                         e1000_setup_copper_link_80003es2lan;
 214                 break;
 215         }
 216
 217         /* Set mta register count */
 218         mac->mta_reg_count = 128;
 219         /* Set rar entry count */
 220         mac->rar_entry_count = E1000_RAR_ENTRIES;
 221         /* Set if part includes ASF firmware */
 222         mac->asf_firmware_present = true;
 223         /* FWSM register */
 224         mac->has_fwsm = true;
 225         /* ARC supported; valid only if manageability features are enabled. */
 226         mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) &
 227                                       E1000_FWSM_MODE_MASK);
 228         /* Adaptive IFS not supported */
 229         mac->adaptive_ifs = false;
 230
 231         /* Function pointers */
 232
 233         /* bus type/speed/width */
 234         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 235         /* reset */
 236         mac->ops.reset_hw = e1000_reset_hw_80003es2lan;
 237         /* hw initialization */
 238         mac->ops.init_hw = e1000_init_hw_80003es2lan;
 239         /* link setup */
 240         mac->ops.setup_link = e1000_setup_link_generic;
 241         /* check management mode */
 242         mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 243         /* multicast address update */
 244         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 245         /* writing VFTA */
 246         mac->ops.write_vfta = e1000_write_vfta_generic;
 247         /* clearing VFTA */
 248         mac->ops.clear_vfta = e1000_clear_vfta_generic;
 249         /* read mac address */
 250         mac->ops.read_mac_addr = e1000_read_mac_addr_80003es2lan;
 251         /* ID LED init */
 252         mac->ops.id_led_init = e1000_id_led_init_generic;
 253         /* blink LED */
 254         mac->ops.blink_led = e1000_blink_led_generic;
 255         /* setup LED */
 256         mac->ops.setup_led = e1000_setup_led_generic;
 257         /* cleanup LED */
 258         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 259         /* turn on/off LED */
 260         mac->ops.led_on = e1000_led_on_generic;
 261         mac->ops.led_off = e1000_led_off_generic;
 262         /* clear hardware counters */
 263         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan;
 264         /* link info */
 265         mac->ops.get_link_up_info = e1000_get_link_up_info_80003es2lan;
 266
 267         /* set lan id for port to determine which phy lock to use */
 268         hw->mac.ops.set_lan_id(hw);
 269
 270         return E1000_SUCCESS;
 271 }
 272
 273 /**
 274  *  e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs.
 275  *  @hw: pointer to the HW structure
 276  *
 277  *  Called to initialize all function pointers and parameters.
 278  **/
 279 void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw)
 280 {
 281         DEBUGFUNC("e1000_init_function_pointers_80003es2lan");
 282
 283         hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan;
 284         hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan;
 285         hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan;
 286 }
 287
 288 /**
 289  *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
 290  *  @hw: pointer to the HW structure
 291  *
 292  *  A wrapper to acquire access rights to the correct PHY.
 293  **/
 294 STATIC s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
 295 {
 296         u16 mask;
 297
 298         DEBUGFUNC("e1000_acquire_phy_80003es2lan");
 299
 300         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 301         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 302 }
 303
 304 /**
 305  *  e1000_release_phy_80003es2lan - Release rights to access PHY
 306  *  @hw: pointer to the HW structure
 307  *
 308  *  A wrapper to release access rights to the correct PHY.
 309  **/
 310 STATIC void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
 311 {
 312         u16 mask;
 313
 314         DEBUGFUNC("e1000_release_phy_80003es2lan");
 315
 316         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 317         e1000_release_swfw_sync_80003es2lan(hw, mask);
 318 }
 319
 320 /**
 321  *  e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register
 322  *  @hw: pointer to the HW structure
 323  *
 324  *  Acquire the semaphore to access the Kumeran interface.
 325  *
 326  **/
 327 STATIC s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
 328 {
 329         u16 mask;
 330
 331         DEBUGFUNC("e1000_acquire_mac_csr_80003es2lan");
 332
 333         mask = E1000_SWFW_CSR_SM;
 334
 335         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 336 }
 337
 338 /**
 339  *  e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register
 340  *  @hw: pointer to the HW structure
 341  *
 342  *  Release the semaphore used to access the Kumeran interface
 343  **/
 344 STATIC void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
 345 {
 346         u16 mask;
 347
 348         DEBUGFUNC("e1000_release_mac_csr_80003es2lan");
 349
 350         mask = E1000_SWFW_CSR_SM;
 351
 352         e1000_release_swfw_sync_80003es2lan(hw, mask);
 353 }
 354
 355 /**
 356  *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
 357  *  @hw: pointer to the HW structure
 358  *
 359  *  Acquire the semaphore to access the EEPROM.
 360  **/
 361 STATIC s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
 362 {
 363         s32 ret_val;
 364
 365         DEBUGFUNC("e1000_acquire_nvm_80003es2lan");
 366
 367         ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 368         if (ret_val)
 369                 return ret_val;
 370
 371         ret_val = e1000_acquire_nvm_generic(hw);
 372
 373         if (ret_val)
 374                 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 375
 376         return ret_val;
 377 }
 378
 379 /**
 380  *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
 381  *  @hw: pointer to the HW structure
 382  *
 383  *  Release the semaphore used to access the EEPROM.
 384  **/
 385 STATIC void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
 386 {
 387         DEBUGFUNC("e1000_release_nvm_80003es2lan");
 388
 389         e1000_release_nvm_generic(hw);
 390         e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 391 }
 392
 393 /**
 394  *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
 395  *  @hw: pointer to the HW structure
 396  *  @mask: specifies which semaphore to acquire
 397  *
 398  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
 399  *  will also specify which port we're acquiring the lock for.
 400  **/
 401 STATIC s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 402 {
 403         u32 swfw_sync;
 404         u32 swmask = mask;
 405         u32 fwmask = mask << 16;
 406         s32 i = 0;
 407         s32 timeout = 50;
 408
 409         DEBUGFUNC("e1000_acquire_swfw_sync_80003es2lan");
 410
 411         while (i < timeout) {
 412                 if (e1000_get_hw_semaphore_generic(hw))
 413                         return -E1000_ERR_SWFW_SYNC;
 414
 415                 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
 416                 if (!(swfw_sync & (fwmask | swmask)))
 417                         break;
 418
 419                 /* Firmware currently using resource (fwmask)
 420                  * or other software thread using resource (swmask)
 421                  */
 422                 e1000_put_hw_semaphore_generic(hw);
 423                 msec_delay_irq(5);
 424                 i++;
 425         }
 426
 427         if (i == timeout) {
 428                 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
 429                 return -E1000_ERR_SWFW_SYNC;
 430         }
 431
 432         swfw_sync |= swmask;
 433         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
 434
 435         e1000_put_hw_semaphore_generic(hw);
 436
 437         return E1000_SUCCESS;
 438 }
 439
 440 /**
 441  *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
 442  *  @hw: pointer to the HW structure
 443  *  @mask: specifies which semaphore to acquire
 444  *
 445  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
 446  *  will also specify which port we're releasing the lock for.
 447  **/
 448 STATIC void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 449 {
 450         u32 swfw_sync;
 451
 452         DEBUGFUNC("e1000_release_swfw_sync_80003es2lan");
 453
 454         while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
 455                 ; /* Empty */
 456
 457         swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
 458         swfw_sync &= ~mask;
 459         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
 460
 461         e1000_put_hw_semaphore_generic(hw);
 462 }
 463
 464 /**
 465  *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
 466  *  @hw: pointer to the HW structure
 467  *  @offset: offset of the register to read
 468  *  @data: pointer to the data returned from the operation
 469  *
 470  *  Read the GG82563 PHY register.
 471  **/
 472 STATIC s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 473                                                   u32 offset, u16 *data)
 474 {
 475         s32 ret_val;
 476         u32 page_select;
 477         u16 temp;
 478
 479         DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan");
 480
 481         ret_val = e1000_acquire_phy_80003es2lan(hw);
 482         if (ret_val)
 483                 return ret_val;
 484
 485         /* Select Configuration Page */
 486         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 487                 page_select = GG82563_PHY_PAGE_SELECT;
 488         } else {
 489                 /* Use Alternative Page Select register to access
 490                  * registers 30 and 31
 491                  */
 492                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 493         }
 494
 495         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 496         ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
 497         if (ret_val) {
 498                 e1000_release_phy_80003es2lan(hw);
 499                 return ret_val;
 500         }
 501
 502         if (hw->dev_spec._80003es2lan.mdic_wa_enable) {
 503                 /* The "ready" bit in the MDIC register may be incorrectly set
 504                  * before the device has completed the "Page Select" MDI
 505                  * transaction.  So we wait 200us after each MDI command...
 506                  */
 507                 usec_delay(200);
 508
 509                 /* ...and verify the command was successful. */
 510                 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
 511
 512                 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 513                         e1000_release_phy_80003es2lan(hw);
 514                         return -E1000_ERR_PHY;
 515                 }
 516
 517                 usec_delay(200);
 518
 519                 ret_val = e1000_read_phy_reg_mdic(hw,
 520                                                   MAX_PHY_REG_ADDRESS & offset,
 521                                                   data);
 522
 523                 usec_delay(200);
 524         } else {
 525                 ret_val = e1000_read_phy_reg_mdic(hw,
 526                                                   MAX_PHY_REG_ADDRESS & offset,
 527                                                   data);
 528         }
 529
 530         e1000_release_phy_80003es2lan(hw);
 531
 532         return ret_val;
 533 }
 534
 535 /**
 536  *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
 537  *  @hw: pointer to the HW structure
 538  *  @offset: offset of the register to read
 539  *  @data: value to write to the register
 540  *
 541  *  Write to the GG82563 PHY register.
 542  **/
 543 STATIC s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 544                                                    u32 offset, u16 data)
 545 {
 546         s32 ret_val;
 547         u32 page_select;
 548         u16 temp;
 549
 550         DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan");
 551
 552         ret_val = e1000_acquire_phy_80003es2lan(hw);
 553         if (ret_val)
 554                 return ret_val;
 555
 556         /* Select Configuration Page */
 557         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 558                 page_select = GG82563_PHY_PAGE_SELECT;
 559         } else {
 560                 /* Use Alternative Page Select register to access
 561                  * registers 30 and 31
 562                  */
 563                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 564         }
 565
 566         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 567         ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
 568         if (ret_val) {
 569                 e1000_release_phy_80003es2lan(hw);
 570                 return ret_val;
 571         }
 572
 573         if (hw->dev_spec._80003es2lan.mdic_wa_enable) {
 574                 /* The "ready" bit in the MDIC register may be incorrectly set
 575                  * before the device has completed the "Page Select" MDI
 576                  * transaction.  So we wait 200us after each MDI command...
 577                  */
 578                 usec_delay(200);
 579
 580                 /* ...and verify the command was successful. */
 581                 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
 582
 583                 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 584                         e1000_release_phy_80003es2lan(hw);
 585                         return -E1000_ERR_PHY;
 586                 }
 587
 588                 usec_delay(200);
 589
 590                 ret_val = e1000_write_phy_reg_mdic(hw,
 591                                                   MAX_PHY_REG_ADDRESS & offset,
 592                                                   data);
 593
 594                 usec_delay(200);
 595         } else {
 596                 ret_val = e1000_write_phy_reg_mdic(hw,
 597                                                   MAX_PHY_REG_ADDRESS & offset,
 598                                                   data);
 599         }
 600
 601         e1000_release_phy_80003es2lan(hw);
 602
 603         return ret_val;
 604 }
 605
 606 /**
 607  *  e1000_write_nvm_80003es2lan - Write to ESB2 NVM
 608  *  @hw: pointer to the HW structure
 609  *  @offset: offset of the register to read
 610  *  @words: number of words to write
 611  *  @data: buffer of data to write to the NVM
 612  *
 613  *  Write "words" of data to the ESB2 NVM.
 614  **/
 615 STATIC s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
 616                                        u16 words, u16 *data)
 617 {
 618         DEBUGFUNC("e1000_write_nvm_80003es2lan");
 619
 620         return e1000_write_nvm_spi(hw, offset, words, data);
 621 }
 622
 623 /**
 624  *  e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
 625  *  @hw: pointer to the HW structure
 626  *
 627  *  Wait a specific amount of time for manageability processes to complete.
 628  *  This is a function pointer entry point called by the phy module.
 629  **/
 630 STATIC s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
 631 {
 632         s32 timeout = PHY_CFG_TIMEOUT;
 633         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
 634
 635         DEBUGFUNC("e1000_get_cfg_done_80003es2lan");
 636
 637         if (hw->bus.func == 1)
 638                 mask = E1000_NVM_CFG_DONE_PORT_1;
 639
 640         while (timeout) {
 641                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
 642                         break;
 643                 msec_delay(1);
 644                 timeout--;
 645         }
 646         if (!timeout) {
 647                 DEBUGOUT("MNG configuration cycle has not completed.\n");
 648                 return -E1000_ERR_RESET;
 649         }
 650
 651         return E1000_SUCCESS;
 652 }
 653
 654 /**
 655  *  e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
 656  *  @hw: pointer to the HW structure
 657  *
 658  *  Force the speed and duplex settings onto the PHY.  This is a
 659  *  function pointer entry point called by the phy module.
 660  **/
 661 STATIC s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
 662 {
 663         s32 ret_val;
 664         u16 phy_data;
 665         bool link;
 666
 667         DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan");
 668
 669         if (!(hw->phy.ops.read_reg))
 670                 return E1000_SUCCESS;
 671
 672         /* Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
 673          * forced whenever speed and duplex are forced.
 674          */
 675         ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
 676         if (ret_val)
 677                 return ret_val;
 678
 679         phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
 680         ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
 681         if (ret_val)
 682                 return ret_val;
 683
 684         DEBUGOUT1("GG82563 PSCR: %X\n", phy_data);
 685
 686         ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data);
 687         if (ret_val)
 688                 return ret_val;
 689
 690         e1000_phy_force_speed_duplex_setup(hw, &phy_data);
 691
 692         /* Reset the phy to commit changes. */
 693         phy_data |= MII_CR_RESET;
 694
 695         ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data);
 696         if (ret_val)
 697                 return ret_val;
 698
 699         usec_delay(1);
 700
 701         if (hw->phy.autoneg_wait_to_complete) {
 702                 DEBUGOUT("Waiting for forced speed/duplex link on GG82563 phy.\n");
 703
 704                 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 705                                                      100000, &link);
 706                 if (ret_val)
 707                         return ret_val;
 708
 709                 if (!link) {
 710                         /* We didn't get link.
 711                          * Reset the DSP and cross our fingers.
 712                          */
 713                         ret_val = e1000_phy_reset_dsp_generic(hw);
 714                         if (ret_val)
 715                                 return ret_val;
 716                 }
 717
 718                 /* Try once more */
 719                 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 720                                                      100000, &link);
 721                 if (ret_val)
 722                         return ret_val;
 723         }
 724
 725         ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
 726                                        &phy_data);
 727         if (ret_val)
 728                 return ret_val;
 729
 730         /* Resetting the phy means we need to verify the TX_CLK corresponds
 731          * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
 732          */
 733         phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
 734         if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
 735                 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
 736         else
 737                 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
 738
 739         /* In addition, we must re-enable CRS on Tx for both half and full
 740          * duplex.
 741          */
 742         phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 743         ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
 744                                         phy_data);
 745
 746         return ret_val;
 747 }
 748
 749 /**
 750  *  e1000_get_cable_length_80003es2lan - Set approximate cable length
 751  *  @hw: pointer to the HW structure
 752  *
 753  *  Find the approximate cable length as measured by the GG82563 PHY.
 754  *  This is a function pointer entry point called by the phy module.
 755  **/
 756 STATIC s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
 757 {
 758         struct e1000_phy_info *phy = &hw->phy;
 759         s32 ret_val;
 760         u16 phy_data, index;
 761
 762         DEBUGFUNC("e1000_get_cable_length_80003es2lan");
 763
 764         if (!(hw->phy.ops.read_reg))
 765                 return E1000_SUCCESS;
 766
 767         ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
 768         if (ret_val)
 769                 return ret_val;
 770
 771         index = phy_data & GG82563_DSPD_CABLE_LENGTH;
 772
 773         if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5)
 774                 return -E1000_ERR_PHY;
 775
 776         phy->min_cable_length = e1000_gg82563_cable_length_table[index];
 777         phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
 778
 779         phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
 780
 781         return E1000_SUCCESS;
 782 }
 783
 784 /**
 785  *  e1000_get_link_up_info_80003es2lan - Report speed and duplex
 786  *  @hw: pointer to the HW structure
 787  *  @speed: pointer to speed buffer
 788  *  @duplex: pointer to duplex buffer
 789  *
 790  *  Retrieve the current speed and duplex configuration.
 791  **/
 792 STATIC s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
 793                                               u16 *duplex)
 794 {
 795         s32 ret_val;
 796
 797         DEBUGFUNC("e1000_get_link_up_info_80003es2lan");
 798
 799         if (hw->phy.media_type == e1000_media_type_copper) {
 800                 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
 801                                                                     duplex);
 802                 hw->phy.ops.cfg_on_link_up(hw);
 803         } else {
 804                 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw,
 805                                                                   speed,
 806                                                                   duplex);
 807         }
 808
 809         return ret_val;
 810 }
 811
 812 /**
 813  *  e1000_reset_hw_80003es2lan - Reset the ESB2 controller
 814  *  @hw: pointer to the HW structure
 815  *
 816  *  Perform a global reset to the ESB2 controller.
 817  **/
 818 STATIC s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
 819 {
 820         u32 ctrl;
 821         s32 ret_val;
 822         u16 kum_reg_data;
 823
 824         DEBUGFUNC("e1000_reset_hw_80003es2lan");
 825
 826         /* Prevent the PCI-E bus from sticking if there is no TLP connection
 827          * on the last TLP read/write transaction when MAC is reset.
 828          */
 829         ret_val = e1000_disable_pcie_master_generic(hw);
 830         if (ret_val)
 831                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
 832
 833         DEBUGOUT("Masking off all interrupts\n");
 834         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
 835
 836         E1000_WRITE_REG(hw, E1000_RCTL, 0);
 837         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
 838         E1000_WRITE_FLUSH(hw);
 839
 840         msec_delay(10);
 841
 842         ctrl = E1000_READ_REG(hw, E1000_CTRL);
 843
 844         ret_val = e1000_acquire_phy_80003es2lan(hw);
 845         if (ret_val)
 846                 return ret_val;
 847
 848         DEBUGOUT("Issuing a global reset to MAC\n");
 849         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
 850         e1000_release_phy_80003es2lan(hw);
 851
 852         /* Disable IBIST slave mode (far-end loopback) */
 853         e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 854                                         &kum_reg_data);
 855         kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
 856         e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 857                                         kum_reg_data);
 858
 859         ret_val = e1000_get_auto_rd_done_generic(hw);
 860         if (ret_val)
 861                 /* We don't want to continue accessing MAC registers. */
 862                 return ret_val;
 863
 864         /* Clear any pending interrupt events. */
 865         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
 866         E1000_READ_REG(hw, E1000_ICR);
 867
 868         return e1000_check_alt_mac_addr_generic(hw);
 869 }
 870
 871 /**
 872  *  e1000_init_hw_80003es2lan - Initialize the ESB2 controller
 873  *  @hw: pointer to the HW structure
 874  *
 875  *  Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
 876  **/
 877 STATIC s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
 878 {
 879         struct e1000_mac_info *mac = &hw->mac;
 880         u32 reg_data;
 881         s32 ret_val;
 882         u16 kum_reg_data;
 883         u16 i;
 884
 885         DEBUGFUNC("e1000_init_hw_80003es2lan");
 886
 887         e1000_initialize_hw_bits_80003es2lan(hw);
 888
 889         /* Initialize identification LED */
 890         ret_val = mac->ops.id_led_init(hw);
 891         /* An error is not fatal and we should not stop init due to this */
 892         if (ret_val)
 893                 DEBUGOUT("Error initializing identification LED\n");
 894
 895         /* Disabling VLAN filtering */
 896         DEBUGOUT("Initializing the IEEE VLAN\n");
 897         mac->ops.clear_vfta(hw);
 898
 899         /* Setup the receive address. */
 900         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
 901
 902         /* Zero out the Multicast HASH table */
 903         DEBUGOUT("Zeroing the MTA\n");
 904         for (i = 0; i < mac->mta_reg_count; i++)
 905                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 906
 907         /* Setup link and flow control */
 908         ret_val = mac->ops.setup_link(hw);
 909         if (ret_val)
 910                 return ret_val;
 911
 912         /* Disable IBIST slave mode (far-end loopback) */
 913         e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 914                                         &kum_reg_data);
 915         kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
 916         e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 917                                          kum_reg_data);
 918
 919         /* Set the transmit descriptor write-back policy */
 920         reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
 921         reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
 922                     E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
 923         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
 924
 925         /* ...for both queues. */
 926         reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
 927         reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
 928                     E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
 929         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
 930
 931         /* Enable retransmit on late collisions */
 932         reg_data = E1000_READ_REG(hw, E1000_TCTL);
 933         reg_data |= E1000_TCTL_RTLC;
 934         E1000_WRITE_REG(hw, E1000_TCTL, reg_data);
 935
 936         /* Configure Gigabit Carry Extend Padding */
 937         reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT);
 938         reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
 939         reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
 940         E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data);
 941
 942         /* Configure Transmit Inter-Packet Gap */
 943         reg_data = E1000_READ_REG(hw, E1000_TIPG);
 944         reg_data &= ~E1000_TIPG_IPGT_MASK;
 945         reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
 946         E1000_WRITE_REG(hw, E1000_TIPG, reg_data);
 947
 948         reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
 949         reg_data &= ~0x00100000;
 950         E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
 951
 952         /* default to true to enable the MDIC W/A */
 953         hw->dev_spec._80003es2lan.mdic_wa_enable = true;
 954
 955         ret_val =
 956             e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >>
 957                                             E1000_KMRNCTRLSTA_OFFSET_SHIFT, &i);
 958         if (!ret_val) {
 959                 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
 960                      E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
 961                         hw->dev_spec._80003es2lan.mdic_wa_enable = false;
 962         }
 963
 964         /* Clear all of the statistics registers (clear on read).  It is
 965          * important that we do this after we have tried to establish link
 966          * because the symbol error count will increment wildly if there
 967          * is no link.
 968          */
 969         e1000_clear_hw_cntrs_80003es2lan(hw);
 970
 971         return ret_val;
 972 }
 973
 974 /**
 975  *  e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
 976  *  @hw: pointer to the HW structure
 977  *
 978  *  Initializes required hardware-dependent bits needed for normal operation.
 979  **/
 980 STATIC void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
 981 {
 982         u32 reg;
 983
 984         DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan");
 985
 986         /* Transmit Descriptor Control 0 */
 987         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
 988         reg |= (1 << 22);
 989         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
 990
 991         /* Transmit Descriptor Control 1 */
 992         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
 993         reg |= (1 << 22);
 994         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
 995
 996         /* Transmit Arbitration Control 0 */
 997         reg = E1000_READ_REG(hw, E1000_TARC(0));
 998         reg &= ~(0xF << 27); /* 30:27 */
 999         if (hw->phy.media_type != e1000_media_type_copper)
1000                 reg &= ~(1 << 20);
1001         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1002
1003         /* Transmit Arbitration Control 1 */
1004         reg = E1000_READ_REG(hw, E1000_TARC(1));
1005         if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1006                 reg &= ~(1 << 28);
1007         else
1008                 reg |= (1 << 28);
1009         E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1010
1011         /* Disable IPv6 extension header parsing because some malformed
1012          * IPv6 headers can hang the Rx.
1013          */
1014         reg = E1000_READ_REG(hw, E1000_RFCTL);
1015         reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1016         E1000_WRITE_REG(hw, E1000_RFCTL, reg);
1017
1018         return;
1019 }
1020
1021 /**
1022  *  e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
1023  *  @hw: pointer to the HW structure
1024  *
1025  *  Setup some GG82563 PHY registers for obtaining link
1026  **/
1027 STATIC s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
1028 {
1029         struct e1000_phy_info *phy = &hw->phy;
1030         s32 ret_val;
1031         u32 reg;
1032         u16 data;
1033
1034         DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan");
1035
1036         ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
1037         if (ret_val)
1038                 return ret_val;
1039
1040         data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1041         /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
1042         data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
1043
1044         ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
1045         if (ret_val)
1046                 return ret_val;
1047
1048         /* Options:
1049          *   MDI/MDI-X = 0 (default)
1050          *   0 - Auto for all speeds
1051          *   1 - MDI mode
1052          *   2 - MDI-X mode
1053          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1054          */
1055         ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data);
1056         if (ret_val)
1057                 return ret_val;
1058
1059         data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1060
1061         switch (phy->mdix) {
1062         case 1:
1063                 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1064                 break;
1065         case 2:
1066                 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1067                 break;
1068         case 0:
1069         default:
1070                 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1071                 break;
1072         }
1073
1074         /* Options:
1075          *   disable_polarity_correction = 0 (default)
1076          *       Automatic Correction for Reversed Cable Polarity
1077          *   0 - Disabled
1078          *   1 - Enabled
1079          */
1080         data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1081         if (phy->disable_polarity_correction)
1082                 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1083
1084         ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data);
1085         if (ret_val)
1086                 return ret_val;
1087
1088         /* SW Reset the PHY so all changes take effect */
1089         ret_val = hw->phy.ops.commit(hw);
1090         if (ret_val) {
1091                 DEBUGOUT("Error Resetting the PHY\n");
1092                 return ret_val;
1093         }
1094
1095         /* Bypass Rx and Tx FIFO's */
1096         reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL;
1097         data = (E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1098                 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1099         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
1100         if (ret_val)
1101                 return ret_val;
1102
1103         reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE;
1104         ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data);
1105         if (ret_val)
1106                 return ret_val;
1107         data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1108         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
1109         if (ret_val)
1110                 return ret_val;
1111
1112         ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1113         if (ret_val)
1114                 return ret_val;
1115
1116         data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1117         ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data);
1118         if (ret_val)
1119                 return ret_val;
1120
1121         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1122         reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1123         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1124
1125         ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1126         if (ret_val)
1127                 return ret_val;
1128
1129         /* Do not init these registers when the HW is in IAMT mode, since the
1130          * firmware will have already initialized them.  We only initialize
1131          * them if the HW is not in IAMT mode.
1132          */
1133         if (!hw->mac.ops.check_mng_mode(hw)) {
1134                 /* Enable Electrical Idle on the PHY */
1135                 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1136                 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1137                                                 data);
1138                 if (ret_val)
1139                         return ret_val;
1140
1141                 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1142                                                &data);
1143                 if (ret_val)
1144                         return ret_val;
1145
1146                 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1147                 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1148                                                 data);
1149                 if (ret_val)
1150                         return ret_val;
1151         }
1152
1153         /* Workaround: Disable padding in Kumeran interface in the MAC
1154          * and in the PHY to avoid CRC errors.
1155          */
1156         ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data);
1157         if (ret_val)
1158                 return ret_val;
1159
1160         data |= GG82563_ICR_DIS_PADDING;
1161         ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data);
1162         if (ret_val)
1163                 return ret_val;
1164
1165         return E1000_SUCCESS;
1166 }
1167
1168 /**
1169  *  e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1170  *  @hw: pointer to the HW structure
1171  *
1172  *  Essentially a wrapper for setting up all things "copper" related.
1173  *  This is a function pointer entry point called by the mac module.
1174  **/
1175 STATIC s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1176 {
1177         u32 ctrl;
1178         s32 ret_val;
1179         u16 reg_data;
1180
1181         DEBUGFUNC("e1000_setup_copper_link_80003es2lan");
1182
1183         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1184         ctrl |= E1000_CTRL_SLU;
1185         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1186         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1187
1188         /* Set the mac to wait the maximum time between each
1189          * iteration and increase the max iterations when
1190          * polling the phy; this fixes erroneous timeouts at 10Mbps.
1191          */
1192         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1193                                                    0xFFFF);
1194         if (ret_val)
1195                 return ret_val;
1196         ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1197                                                   &reg_data);
1198         if (ret_val)
1199                 return ret_val;
1200         reg_data |= 0x3F;
1201         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1202                                                    reg_data);
1203         if (ret_val)
1204                 return ret_val;
1205         ret_val =
1206             e1000_read_kmrn_reg_80003es2lan(hw,
1207                                             E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1208                                             &reg_data);
1209         if (ret_val)
1210                 return ret_val;
1211         reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1212         ret_val =
1213             e1000_write_kmrn_reg_80003es2lan(hw,
1214                                              E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1215                                              reg_data);
1216         if (ret_val)
1217                 return ret_val;
1218
1219         ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1220         if (ret_val)
1221                 return ret_val;
1222
1223         return e1000_setup_copper_link_generic(hw);
1224 }
1225
1226 /**
1227  *  e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1228  *  @hw: pointer to the HW structure
1229  *  @duplex: current duplex setting
1230  *
1231  *  Configure the KMRN interface by applying last minute quirks for
1232  *  10/100 operation.
1233  **/
1234 STATIC s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1235 {
1236         s32 ret_val = E1000_SUCCESS;
1237         u16 speed;
1238         u16 duplex;
1239
1240         DEBUGFUNC("e1000_configure_on_link_up");
1241
1242         if (hw->phy.media_type == e1000_media_type_copper) {
1243                 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, &speed,
1244                                                                     &duplex);
1245                 if (ret_val)
1246                         return ret_val;
1247
1248                 if (speed == SPEED_1000)
1249                         ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1250                 else
1251                         ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1252         }
1253
1254         return ret_val;
1255 }
1256
1257 /**
1258  *  e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1259  *  @hw: pointer to the HW structure
1260  *  @duplex: current duplex setting
1261  *
1262  *  Configure the KMRN interface by applying last minute quirks for
1263  *  10/100 operation.
1264  **/
1265 STATIC s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1266 {
1267         s32 ret_val;
1268         u32 tipg;
1269         u32 i = 0;
1270         u16 reg_data, reg_data2;
1271
1272         DEBUGFUNC("e1000_configure_kmrn_for_10_100");
1273
1274         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1275         ret_val =
1276             e1000_write_kmrn_reg_80003es2lan(hw,
1277                                              E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1278                                              reg_data);
1279         if (ret_val)
1280                 return ret_val;
1281
1282         /* Configure Transmit Inter-Packet Gap */
1283         tipg = E1000_READ_REG(hw, E1000_TIPG);
1284         tipg &= ~E1000_TIPG_IPGT_MASK;
1285         tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1286         E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1287
1288         do {
1289                 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1290                                                &reg_data);
1291                 if (ret_val)
1292                         return ret_val;
1293
1294                 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1295                                                &reg_data2);
1296                 if (ret_val)
1297                         return ret_val;
1298                 i++;
1299         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1300
1301         if (duplex == HALF_DUPLEX)
1302                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1303         else
1304                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1305
1306         return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1307 }
1308
1309 /**
1310  *  e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1311  *  @hw: pointer to the HW structure
1312  *
1313  *  Configure the KMRN interface by applying last minute quirks for
1314  *  gigabit operation.
1315  **/
1316 STATIC s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1317 {
1318         s32 ret_val;
1319         u16 reg_data, reg_data2;
1320         u32 tipg;
1321         u32 i = 0;
1322
1323         DEBUGFUNC("e1000_configure_kmrn_for_1000");
1324
1325         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1326         ret_val =
1327             e1000_write_kmrn_reg_80003es2lan(hw,
1328                                              E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1329                                              reg_data);
1330         if (ret_val)
1331                 return ret_val;
1332
1333         /* Configure Transmit Inter-Packet Gap */
1334         tipg = E1000_READ_REG(hw, E1000_TIPG);
1335         tipg &= ~E1000_TIPG_IPGT_MASK;
1336         tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1337         E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1338
1339         do {
1340                 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1341                                                &reg_data);
1342                 if (ret_val)
1343                         return ret_val;
1344
1345                 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1346                                                &reg_data2);
1347                 if (ret_val)
1348                         return ret_val;
1349                 i++;
1350         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1351
1352         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1353
1354         return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1355 }
1356
1357 /**
1358  *  e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1359  *  @hw: pointer to the HW structure
1360  *  @offset: register offset to be read
1361  *  @data: pointer to the read data
1362  *
1363  *  Acquire semaphore, then read the PHY register at offset
1364  *  using the kumeran interface.  The information retrieved is stored in data.
1365  *  Release the semaphore before exiting.
1366  **/
1367 STATIC s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1368                                            u16 *data)
1369 {
1370         u32 kmrnctrlsta;
1371         s32 ret_val;
1372
1373         DEBUGFUNC("e1000_read_kmrn_reg_80003es2lan");
1374
1375         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1376         if (ret_val)
1377                 return ret_val;
1378
1379         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1380                        E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1381         E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1382         E1000_WRITE_FLUSH(hw);
1383
1384         usec_delay(2);
1385
1386         kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
1387         *data = (u16)kmrnctrlsta;
1388
1389         e1000_release_mac_csr_80003es2lan(hw);
1390
1391         return ret_val;
1392 }
1393
1394 /**
1395  *  e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1396  *  @hw: pointer to the HW structure
1397  *  @offset: register offset to write to
1398  *  @data: data to write at register offset
1399  *
1400  *  Acquire semaphore, then write the data to PHY register
1401  *  at the offset using the kumeran interface.  Release semaphore
1402  *  before exiting.
1403  **/
1404 STATIC s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1405                                             u16 data)
1406 {
1407         u32 kmrnctrlsta;
1408         s32 ret_val;
1409
1410         DEBUGFUNC("e1000_write_kmrn_reg_80003es2lan");
1411
1412         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1413         if (ret_val)
1414                 return ret_val;
1415
1416         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1417                        E1000_KMRNCTRLSTA_OFFSET) | data;
1418         E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1419         E1000_WRITE_FLUSH(hw);
1420
1421         usec_delay(2);
1422
1423         e1000_release_mac_csr_80003es2lan(hw);
1424
1425         return ret_val;
1426 }
1427
1428 /**
1429  *  e1000_read_mac_addr_80003es2lan - Read device MAC address
1430  *  @hw: pointer to the HW structure
1431  **/
1432 STATIC s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1433 {
1434         s32 ret_val;
1435
1436         DEBUGFUNC("e1000_read_mac_addr_80003es2lan");
1437
1438         /* If there's an alternate MAC address place it in RAR0
1439          * so that it will override the Si installed default perm
1440          * address.
1441          */
1442         ret_val = e1000_check_alt_mac_addr_generic(hw);
1443         if (ret_val)
1444                 return ret_val;
1445
1446         return e1000_read_mac_addr_generic(hw);
1447 }
1448
1449 /**
1450  * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1451  * @hw: pointer to the HW structure
1452  *
1453  * In the case of a PHY power down to save power, or to turn off link during a
1454  * driver unload, or wake on lan is not enabled, remove the link.
1455  **/
1456 STATIC void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1457 {
1458         /* If the management interface is not enabled, then power down */
1459         if (!(hw->mac.ops.check_mng_mode(hw) ||
1460               hw->phy.ops.check_reset_block(hw)))
1461                 e1000_power_down_phy_copper(hw);
1462
1463         return;
1464 }
1465
1466 /**
1467  *  e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1468  *  @hw: pointer to the HW structure
1469  *
1470  *  Clears the hardware counters by reading the counter registers.
1471  **/
1472 STATIC void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1473 {
1474         DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan");
1475
1476         e1000_clear_hw_cntrs_base_generic(hw);
1477
1478         E1000_READ_REG(hw, E1000_PRC64);
1479         E1000_READ_REG(hw, E1000_PRC127);
1480         E1000_READ_REG(hw, E1000_PRC255);
1481         E1000_READ_REG(hw, E1000_PRC511);
1482         E1000_READ_REG(hw, E1000_PRC1023);
1483         E1000_READ_REG(hw, E1000_PRC1522);
1484         E1000_READ_REG(hw, E1000_PTC64);
1485         E1000_READ_REG(hw, E1000_PTC127);
1486         E1000_READ_REG(hw, E1000_PTC255);
1487         E1000_READ_REG(hw, E1000_PTC511);
1488         E1000_READ_REG(hw, E1000_PTC1023);
1489         E1000_READ_REG(hw, E1000_PTC1522);
1490
1491         E1000_READ_REG(hw, E1000_ALGNERRC);
1492         E1000_READ_REG(hw, E1000_RXERRC);
1493         E1000_READ_REG(hw, E1000_TNCRS);
1494         E1000_READ_REG(hw, E1000_CEXTERR);
1495         E1000_READ_REG(hw, E1000_TSCTC);
1496         E1000_READ_REG(hw, E1000_TSCTFC);
1497
1498         E1000_READ_REG(hw, E1000_MGTPRC);
1499         E1000_READ_REG(hw, E1000_MGTPDC);
1500         E1000_READ_REG(hw, E1000_MGTPTC);
1501
1502         E1000_READ_REG(hw, E1000_IAC);
1503         E1000_READ_REG(hw, E1000_ICRXOC);
1504
1505         E1000_READ_REG(hw, E1000_ICRXPTC);
1506         E1000_READ_REG(hw, E1000_ICRXATC);
1507         E1000_READ_REG(hw, E1000_ICTXPTC);
1508         E1000_READ_REG(hw, E1000_ICTXATC);
1509         E1000_READ_REG(hw, E1000_ICTXQEC);
1510         E1000_READ_REG(hw, E1000_ICTXQMTC);
1511         E1000_READ_REG(hw, E1000_ICRXDMTC);
1512 }