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3 Copyright (c) 2001-2012, Intel Corporation
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32 ***************************************************************************/
35 * 80003ES2LAN Gigabit Ethernet Controller (Copper)
36 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
39 #include "e1000_api.h"
41 STATIC s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw);
42 STATIC s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw);
43 STATIC s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw);
44 STATIC s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw);
45 STATIC void e1000_release_phy_80003es2lan(struct e1000_hw *hw);
46 STATIC s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw);
47 STATIC void e1000_release_nvm_80003es2lan(struct e1000_hw *hw);
48 STATIC s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
51 STATIC s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
54 STATIC s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
55 u16 words, u16 *data);
56 STATIC s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw);
57 STATIC s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw);
58 STATIC s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw);
59 STATIC s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
61 STATIC s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw);
62 STATIC s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw);
63 STATIC s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
64 STATIC void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
65 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
66 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
67 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
68 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
69 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
71 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
73 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw);
74 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
75 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
76 STATIC s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw);
77 STATIC void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
80 * A table for the GG82563 cable length where the range is defined
81 * with a lower bound at "index" and the upper bound at
84 static const u16 e1000_gg82563_cable_length_table[] = {
85 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
86 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
87 (sizeof(e1000_gg82563_cable_length_table) / \
88 sizeof(e1000_gg82563_cable_length_table[0]))
91 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
92 * @hw: pointer to the HW structure
94 STATIC s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
96 struct e1000_phy_info *phy = &hw->phy;
99 DEBUGFUNC("e1000_init_phy_params_80003es2lan");
101 if (hw->phy.media_type != e1000_media_type_copper) {
102 phy->type = e1000_phy_none;
103 return E1000_SUCCESS;
105 phy->ops.power_up = e1000_power_up_phy_copper;
106 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
110 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
111 phy->reset_delay_us = 100;
112 phy->type = e1000_phy_gg82563;
114 phy->ops.acquire = e1000_acquire_phy_80003es2lan;
115 phy->ops.check_polarity = e1000_check_polarity_m88;
116 phy->ops.check_reset_block = e1000_check_reset_block_generic;
117 phy->ops.commit = e1000_phy_sw_reset_generic;
118 phy->ops.get_cfg_done = e1000_get_cfg_done_80003es2lan;
119 phy->ops.get_info = e1000_get_phy_info_m88;
120 phy->ops.release = e1000_release_phy_80003es2lan;
121 phy->ops.reset = e1000_phy_hw_reset_generic;
122 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
124 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan;
125 phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan;
126 phy->ops.read_reg = e1000_read_phy_reg_gg82563_80003es2lan;
127 phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan;
129 phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan;
131 /* This can only be done after all function pointers are setup. */
132 ret_val = e1000_get_phy_id(hw);
135 if (phy->id != GG82563_E_PHY_ID)
136 return -E1000_ERR_PHY;
142 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
143 * @hw: pointer to the HW structure
145 STATIC s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
147 struct e1000_nvm_info *nvm = &hw->nvm;
148 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
151 DEBUGFUNC("e1000_init_nvm_params_80003es2lan");
153 nvm->opcode_bits = 8;
155 switch (nvm->override) {
156 case e1000_nvm_override_spi_large:
158 nvm->address_bits = 16;
160 case e1000_nvm_override_spi_small:
162 nvm->address_bits = 8;
165 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
166 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
170 nvm->type = e1000_nvm_eeprom_spi;
172 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
173 E1000_EECD_SIZE_EX_SHIFT);
176 * Added to a constant, "size" becomes the left-shift value
177 * for setting word_size.
179 size += NVM_WORD_SIZE_BASE_SHIFT;
181 /* EEPROM access above 16k is unsupported */
184 nvm->word_size = 1 << size;
186 /* Function Pointers */
187 nvm->ops.acquire = e1000_acquire_nvm_80003es2lan;
188 nvm->ops.read = e1000_read_nvm_eerd;
189 nvm->ops.release = e1000_release_nvm_80003es2lan;
190 nvm->ops.update = e1000_update_nvm_checksum_generic;
191 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
192 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
193 nvm->ops.write = e1000_write_nvm_80003es2lan;
195 return E1000_SUCCESS;
199 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
200 * @hw: pointer to the HW structure
202 STATIC s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
204 struct e1000_mac_info *mac = &hw->mac;
206 DEBUGFUNC("e1000_init_mac_params_80003es2lan");
208 /* Set media type and media-dependent function pointers */
209 switch (hw->device_id) {
210 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
211 hw->phy.media_type = e1000_media_type_internal_serdes;
212 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
213 mac->ops.setup_physical_interface =
214 e1000_setup_fiber_serdes_link_generic;
217 hw->phy.media_type = e1000_media_type_copper;
218 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
219 mac->ops.setup_physical_interface =
220 e1000_setup_copper_link_80003es2lan;
224 /* Set mta register count */
225 mac->mta_reg_count = 128;
226 /* Set rar entry count */
227 mac->rar_entry_count = E1000_RAR_ENTRIES;
228 /* Set if part includes ASF firmware */
229 mac->asf_firmware_present = true;
231 mac->has_fwsm = true;
232 /* ARC supported; valid only if manageability features are enabled. */
233 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) &
234 E1000_FWSM_MODE_MASK);
235 /* Adaptive IFS not supported */
236 mac->adaptive_ifs = false;
238 /* Function pointers */
240 /* bus type/speed/width */
241 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
243 mac->ops.reset_hw = e1000_reset_hw_80003es2lan;
244 /* hw initialization */
245 mac->ops.init_hw = e1000_init_hw_80003es2lan;
247 mac->ops.setup_link = e1000_setup_link_generic;
248 /* check management mode */
249 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
250 /* multicast address update */
251 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
253 mac->ops.write_vfta = e1000_write_vfta_generic;
255 mac->ops.clear_vfta = e1000_clear_vfta_generic;
256 /* read mac address */
257 mac->ops.read_mac_addr = e1000_read_mac_addr_80003es2lan;
259 mac->ops.id_led_init = e1000_id_led_init_generic;
261 mac->ops.blink_led = e1000_blink_led_generic;
263 mac->ops.setup_led = e1000_setup_led_generic;
265 mac->ops.cleanup_led = e1000_cleanup_led_generic;
266 /* turn on/off LED */
267 mac->ops.led_on = e1000_led_on_generic;
268 mac->ops.led_off = e1000_led_off_generic;
269 /* clear hardware counters */
270 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan;
272 mac->ops.get_link_up_info = e1000_get_link_up_info_80003es2lan;
274 /* set lan id for port to determine which phy lock to use */
275 hw->mac.ops.set_lan_id(hw);
277 return E1000_SUCCESS;
281 * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs.
282 * @hw: pointer to the HW structure
284 * Called to initialize all function pointers and parameters.
286 void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw)
288 DEBUGFUNC("e1000_init_function_pointers_80003es2lan");
290 hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan;
291 hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan;
292 hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan;
296 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
297 * @hw: pointer to the HW structure
299 * A wrapper to acquire access rights to the correct PHY.
301 STATIC s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
305 DEBUGFUNC("e1000_acquire_phy_80003es2lan");
307 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
308 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
312 * e1000_release_phy_80003es2lan - Release rights to access PHY
313 * @hw: pointer to the HW structure
315 * A wrapper to release access rights to the correct PHY.
317 STATIC void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
321 DEBUGFUNC("e1000_release_phy_80003es2lan");
323 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
324 e1000_release_swfw_sync_80003es2lan(hw, mask);
328 * e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register
329 * @hw: pointer to the HW structure
331 * Acquire the semaphore to access the Kumeran interface.
334 STATIC s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
338 DEBUGFUNC("e1000_acquire_mac_csr_80003es2lan");
340 mask = E1000_SWFW_CSR_SM;
342 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
346 * e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register
347 * @hw: pointer to the HW structure
349 * Release the semaphore used to access the Kumeran interface
351 STATIC void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
355 DEBUGFUNC("e1000_release_mac_csr_80003es2lan");
357 mask = E1000_SWFW_CSR_SM;
359 e1000_release_swfw_sync_80003es2lan(hw, mask);
363 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
364 * @hw: pointer to the HW structure
366 * Acquire the semaphore to access the EEPROM.
368 STATIC s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
372 DEBUGFUNC("e1000_acquire_nvm_80003es2lan");
374 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
378 ret_val = e1000_acquire_nvm_generic(hw);
381 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
387 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
388 * @hw: pointer to the HW structure
390 * Release the semaphore used to access the EEPROM.
392 STATIC void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
394 DEBUGFUNC("e1000_release_nvm_80003es2lan");
396 e1000_release_nvm_generic(hw);
397 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
401 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
402 * @hw: pointer to the HW structure
403 * @mask: specifies which semaphore to acquire
405 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
406 * will also specify which port we're acquiring the lock for.
408 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
412 u32 fwmask = mask << 16;
416 DEBUGFUNC("e1000_acquire_swfw_sync_80003es2lan");
418 while (i < timeout) {
419 if (e1000_get_hw_semaphore_generic(hw))
420 return -E1000_ERR_SWFW_SYNC;
422 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
423 if (!(swfw_sync & (fwmask | swmask)))
427 * Firmware currently using resource (fwmask)
428 * or other software thread using resource (swmask)
430 e1000_put_hw_semaphore_generic(hw);
436 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
437 return -E1000_ERR_SWFW_SYNC;
441 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
443 e1000_put_hw_semaphore_generic(hw);
445 return E1000_SUCCESS;
449 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
450 * @hw: pointer to the HW structure
451 * @mask: specifies which semaphore to acquire
453 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
454 * will also specify which port we're releasing the lock for.
456 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
460 DEBUGFUNC("e1000_release_swfw_sync_80003es2lan");
462 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
465 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
467 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
469 e1000_put_hw_semaphore_generic(hw);
473 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
474 * @hw: pointer to the HW structure
475 * @offset: offset of the register to read
476 * @data: pointer to the data returned from the operation
478 * Read the GG82563 PHY register.
480 STATIC s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
481 u32 offset, u16 *data)
487 DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan");
489 ret_val = e1000_acquire_phy_80003es2lan(hw);
493 /* Select Configuration Page */
494 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
495 page_select = GG82563_PHY_PAGE_SELECT;
498 * Use Alternative Page Select register to access
499 * registers 30 and 31
501 page_select = GG82563_PHY_PAGE_SELECT_ALT;
504 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
505 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
507 e1000_release_phy_80003es2lan(hw);
511 if (hw->dev_spec._80003es2lan.mdic_wa_enable) {
513 * The "ready" bit in the MDIC register may be incorrectly set
514 * before the device has completed the "Page Select" MDI
515 * transaction. So we wait 200us after each MDI command...
519 /* ...and verify the command was successful. */
520 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
522 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
523 e1000_release_phy_80003es2lan(hw);
524 return -E1000_ERR_PHY;
529 ret_val = e1000_read_phy_reg_mdic(hw,
530 MAX_PHY_REG_ADDRESS & offset,
535 ret_val = e1000_read_phy_reg_mdic(hw,
536 MAX_PHY_REG_ADDRESS & offset,
540 e1000_release_phy_80003es2lan(hw);
546 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
547 * @hw: pointer to the HW structure
548 * @offset: offset of the register to read
549 * @data: value to write to the register
551 * Write to the GG82563 PHY register.
553 STATIC s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
554 u32 offset, u16 data)
560 DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan");
562 ret_val = e1000_acquire_phy_80003es2lan(hw);
566 /* Select Configuration Page */
567 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
568 page_select = GG82563_PHY_PAGE_SELECT;
571 * Use Alternative Page Select register to access
572 * registers 30 and 31
574 page_select = GG82563_PHY_PAGE_SELECT_ALT;
577 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
578 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
580 e1000_release_phy_80003es2lan(hw);
584 if (hw->dev_spec._80003es2lan.mdic_wa_enable) {
586 * The "ready" bit in the MDIC register may be incorrectly set
587 * before the device has completed the "Page Select" MDI
588 * transaction. So we wait 200us after each MDI command...
592 /* ...and verify the command was successful. */
593 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
595 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
596 e1000_release_phy_80003es2lan(hw);
597 return -E1000_ERR_PHY;
602 ret_val = e1000_write_phy_reg_mdic(hw,
603 MAX_PHY_REG_ADDRESS & offset,
608 ret_val = e1000_write_phy_reg_mdic(hw,
609 MAX_PHY_REG_ADDRESS & offset,
613 e1000_release_phy_80003es2lan(hw);
619 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM
620 * @hw: pointer to the HW structure
621 * @offset: offset of the register to read
622 * @words: number of words to write
623 * @data: buffer of data to write to the NVM
625 * Write "words" of data to the ESB2 NVM.
627 STATIC s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
628 u16 words, u16 *data)
630 DEBUGFUNC("e1000_write_nvm_80003es2lan");
632 return e1000_write_nvm_spi(hw, offset, words, data);
636 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
637 * @hw: pointer to the HW structure
639 * Wait a specific amount of time for manageability processes to complete.
640 * This is a function pointer entry point called by the phy module.
642 STATIC s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
644 s32 timeout = PHY_CFG_TIMEOUT;
645 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
647 DEBUGFUNC("e1000_get_cfg_done_80003es2lan");
649 if (hw->bus.func == 1)
650 mask = E1000_NVM_CFG_DONE_PORT_1;
653 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
659 DEBUGOUT("MNG configuration cycle has not completed.\n");
660 return -E1000_ERR_RESET;
663 return E1000_SUCCESS;
667 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
668 * @hw: pointer to the HW structure
670 * Force the speed and duplex settings onto the PHY. This is a
671 * function pointer entry point called by the phy module.
673 STATIC s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
679 DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan");
681 if (!(hw->phy.ops.read_reg))
682 return E1000_SUCCESS;
685 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
686 * forced whenever speed and duplex are forced.
688 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
692 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
693 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
697 DEBUGOUT1("GG82563 PSCR: %X\n", phy_data);
699 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data);
703 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
705 /* Reset the phy to commit changes. */
706 phy_data |= MII_CR_RESET;
708 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data);
714 if (hw->phy.autoneg_wait_to_complete) {
715 DEBUGOUT("Waiting for forced speed/duplex link on GG82563 phy.\n");
717 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
724 * We didn't get link.
725 * Reset the DSP and cross our fingers.
727 ret_val = e1000_phy_reset_dsp_generic(hw);
733 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
739 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
745 * Resetting the phy means we need to verify the TX_CLK corresponds
746 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
748 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
749 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
750 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
752 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
755 * In addition, we must re-enable CRS on Tx for both half and full
758 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
759 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
766 * e1000_get_cable_length_80003es2lan - Set approximate cable length
767 * @hw: pointer to the HW structure
769 * Find the approximate cable length as measured by the GG82563 PHY.
770 * This is a function pointer entry point called by the phy module.
772 STATIC s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
774 struct e1000_phy_info *phy = &hw->phy;
775 s32 ret_val = E1000_SUCCESS;
778 DEBUGFUNC("e1000_get_cable_length_80003es2lan");
780 if (!(hw->phy.ops.read_reg))
781 return E1000_SUCCESS;
783 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
787 index = phy_data & GG82563_DSPD_CABLE_LENGTH;
789 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5)
790 return -E1000_ERR_PHY;
792 phy->min_cable_length = e1000_gg82563_cable_length_table[index];
793 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
795 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
797 return E1000_SUCCESS;
801 * e1000_get_link_up_info_80003es2lan - Report speed and duplex
802 * @hw: pointer to the HW structure
803 * @speed: pointer to speed buffer
804 * @duplex: pointer to duplex buffer
806 * Retrieve the current speed and duplex configuration.
808 STATIC s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
813 DEBUGFUNC("e1000_get_link_up_info_80003es2lan");
815 if (hw->phy.media_type == e1000_media_type_copper) {
816 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
818 hw->phy.ops.cfg_on_link_up(hw);
820 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw,
829 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
830 * @hw: pointer to the HW structure
832 * Perform a global reset to the ESB2 controller.
834 STATIC s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
840 DEBUGFUNC("e1000_reset_hw_80003es2lan");
843 * Prevent the PCI-E bus from sticking if there is no TLP connection
844 * on the last TLP read/write transaction when MAC is reset.
846 ret_val = e1000_disable_pcie_master_generic(hw);
848 DEBUGOUT("PCI-E Master disable polling has failed.\n");
850 DEBUGOUT("Masking off all interrupts\n");
851 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
853 E1000_WRITE_REG(hw, E1000_RCTL, 0);
854 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
855 E1000_WRITE_FLUSH(hw);
859 ctrl = E1000_READ_REG(hw, E1000_CTRL);
861 ret_val = e1000_acquire_phy_80003es2lan(hw);
862 DEBUGOUT("Issuing a global reset to MAC\n");
863 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
864 e1000_release_phy_80003es2lan(hw);
866 /* Disable IBIST slave mode (far-end loopback) */
867 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
869 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
870 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
873 ret_val = e1000_get_auto_rd_done_generic(hw);
875 /* We don't want to continue accessing MAC registers. */
878 /* Clear any pending interrupt events. */
879 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
880 E1000_READ_REG(hw, E1000_ICR);
882 return e1000_check_alt_mac_addr_generic(hw);
886 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
887 * @hw: pointer to the HW structure
889 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
891 STATIC s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
893 struct e1000_mac_info *mac = &hw->mac;
899 DEBUGFUNC("e1000_init_hw_80003es2lan");
901 e1000_initialize_hw_bits_80003es2lan(hw);
903 /* Initialize identification LED */
904 ret_val = mac->ops.id_led_init(hw);
906 DEBUGOUT("Error initializing identification LED\n");
907 /* This is not fatal and we should not stop init due to this */
909 /* Disabling VLAN filtering */
910 DEBUGOUT("Initializing the IEEE VLAN\n");
911 mac->ops.clear_vfta(hw);
913 /* Setup the receive address. */
914 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
916 /* Zero out the Multicast HASH table */
917 DEBUGOUT("Zeroing the MTA\n");
918 for (i = 0; i < mac->mta_reg_count; i++)
919 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
921 /* Setup link and flow control */
922 ret_val = mac->ops.setup_link(hw);
924 /* Disable IBIST slave mode (far-end loopback) */
925 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
927 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
928 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
931 /* Set the transmit descriptor write-back policy */
932 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
933 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
934 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
935 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
937 /* ...for both queues. */
938 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
939 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
940 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
941 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
943 /* Enable retransmit on late collisions */
944 reg_data = E1000_READ_REG(hw, E1000_TCTL);
945 reg_data |= E1000_TCTL_RTLC;
946 E1000_WRITE_REG(hw, E1000_TCTL, reg_data);
948 /* Configure Gigabit Carry Extend Padding */
949 reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT);
950 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
951 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
952 E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data);
954 /* Configure Transmit Inter-Packet Gap */
955 reg_data = E1000_READ_REG(hw, E1000_TIPG);
956 reg_data &= ~E1000_TIPG_IPGT_MASK;
957 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
958 E1000_WRITE_REG(hw, E1000_TIPG, reg_data);
960 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
961 reg_data &= ~0x00100000;
962 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
964 /* default to true to enable the MDIC W/A */
965 hw->dev_spec._80003es2lan.mdic_wa_enable = true;
967 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
968 E1000_KMRNCTRLSTA_OFFSET >>
969 E1000_KMRNCTRLSTA_OFFSET_SHIFT,
972 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
973 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
974 hw->dev_spec._80003es2lan.mdic_wa_enable = false;
978 * Clear all of the statistics registers (clear on read). It is
979 * important that we do this after we have tried to establish link
980 * because the symbol error count will increment wildly if there
983 e1000_clear_hw_cntrs_80003es2lan(hw);
989 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
990 * @hw: pointer to the HW structure
992 * Initializes required hardware-dependent bits needed for normal operation.
994 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
998 DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan");
1000 /* Transmit Descriptor Control 0 */
1001 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1003 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1005 /* Transmit Descriptor Control 1 */
1006 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1008 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1010 /* Transmit Arbitration Control 0 */
1011 reg = E1000_READ_REG(hw, E1000_TARC(0));
1012 reg &= ~(0xF << 27); /* 30:27 */
1013 if (hw->phy.media_type != e1000_media_type_copper)
1015 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1017 /* Transmit Arbitration Control 1 */
1018 reg = E1000_READ_REG(hw, E1000_TARC(1));
1019 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1023 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1026 * Disable IPv6 extension header parsing because some malformed
1027 * IPv6 headers can hang the Rx.
1029 reg = E1000_READ_REG(hw, E1000_RFCTL);
1030 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1031 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
1037 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
1038 * @hw: pointer to the HW structure
1040 * Setup some GG82563 PHY registers for obtaining link
1042 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
1044 struct e1000_phy_info *phy = &hw->phy;
1049 DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan");
1051 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
1055 data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1056 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
1057 data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
1059 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
1065 * MDI/MDI-X = 0 (default)
1066 * 0 - Auto for all speeds
1069 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1071 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data);
1075 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1077 switch (phy->mdix) {
1079 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1082 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1086 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1092 * disable_polarity_correction = 0 (default)
1093 * Automatic Correction for Reversed Cable Polarity
1097 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1098 if (phy->disable_polarity_correction)
1099 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1101 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data);
1105 /* SW Reset the PHY so all changes take effect */
1106 ret_val = hw->phy.ops.commit(hw);
1108 DEBUGOUT("Error Resetting the PHY\n");
1112 /* Bypass Rx and Tx FIFO's */
1113 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1114 E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
1115 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1116 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1120 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1121 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, &data);
1124 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1125 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1126 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, data);
1130 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1134 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1135 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data);
1139 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1140 ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1141 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1143 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1148 * Do not init these registers when the HW is in IAMT mode, since the
1149 * firmware will have already initialized them. We only initialize
1150 * them if the HW is not in IAMT mode.
1152 if (!hw->mac.ops.check_mng_mode(hw)) {
1153 /* Enable Electrical Idle on the PHY */
1154 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1155 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1160 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1165 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1166 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1173 * Workaround: Disable padding in Kumeran interface in the MAC
1174 * and in the PHY to avoid CRC errors.
1176 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data);
1180 data |= GG82563_ICR_DIS_PADDING;
1181 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data);
1185 return E1000_SUCCESS;
1189 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1190 * @hw: pointer to the HW structure
1192 * Essentially a wrapper for setting up all things "copper" related.
1193 * This is a function pointer entry point called by the mac module.
1195 STATIC s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1201 DEBUGFUNC("e1000_setup_copper_link_80003es2lan");
1203 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1204 ctrl |= E1000_CTRL_SLU;
1205 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1206 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1209 * Set the mac to wait the maximum time between each
1210 * iteration and increase the max iterations when
1211 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1213 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1217 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1222 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1226 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1227 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, ®_data);
1230 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1231 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1232 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, reg_data);
1236 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1240 return e1000_setup_copper_link_generic(hw);
1244 * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1245 * @hw: pointer to the HW structure
1246 * @duplex: current duplex setting
1248 * Configure the KMRN interface by applying last minute quirks for
1251 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1253 s32 ret_val = E1000_SUCCESS;
1257 DEBUGFUNC("e1000_configure_on_link_up");
1259 if (hw->phy.media_type == e1000_media_type_copper) {
1260 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, &speed,
1265 if (speed == SPEED_1000)
1266 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1268 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1275 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1276 * @hw: pointer to the HW structure
1277 * @duplex: current duplex setting
1279 * Configure the KMRN interface by applying last minute quirks for
1282 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1287 u16 reg_data, reg_data2;
1289 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
1291 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1292 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1293 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1298 /* Configure Transmit Inter-Packet Gap */
1299 tipg = E1000_READ_REG(hw, E1000_TIPG);
1300 tipg &= ~E1000_TIPG_IPGT_MASK;
1301 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1302 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1305 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1310 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1315 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1317 if (duplex == HALF_DUPLEX)
1318 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1320 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1322 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1326 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1327 * @hw: pointer to the HW structure
1329 * Configure the KMRN interface by applying last minute quirks for
1330 * gigabit operation.
1332 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1335 u16 reg_data, reg_data2;
1339 DEBUGFUNC("e1000_configure_kmrn_for_1000");
1341 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1342 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1343 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, reg_data);
1347 /* Configure Transmit Inter-Packet Gap */
1348 tipg = E1000_READ_REG(hw, E1000_TIPG);
1349 tipg &= ~E1000_TIPG_IPGT_MASK;
1350 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1351 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1354 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1359 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1364 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1366 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1368 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1372 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1373 * @hw: pointer to the HW structure
1374 * @offset: register offset to be read
1375 * @data: pointer to the read data
1377 * Acquire semaphore, then read the PHY register at offset
1378 * using the kumeran interface. The information retrieved is stored in data.
1379 * Release the semaphore before exiting.
1381 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1385 s32 ret_val = E1000_SUCCESS;
1387 DEBUGFUNC("e1000_read_kmrn_reg_80003es2lan");
1389 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1393 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1394 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1395 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1396 E1000_WRITE_FLUSH(hw);
1400 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
1401 *data = (u16)kmrnctrlsta;
1403 e1000_release_mac_csr_80003es2lan(hw);
1409 * e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1410 * @hw: pointer to the HW structure
1411 * @offset: register offset to write to
1412 * @data: data to write at register offset
1414 * Acquire semaphore, then write the data to PHY register
1415 * at the offset using the kumeran interface. Release semaphore
1418 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1422 s32 ret_val = E1000_SUCCESS;
1424 DEBUGFUNC("e1000_write_kmrn_reg_80003es2lan");
1426 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1430 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1431 E1000_KMRNCTRLSTA_OFFSET) | data;
1432 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1433 E1000_WRITE_FLUSH(hw);
1437 e1000_release_mac_csr_80003es2lan(hw);
1443 * e1000_read_mac_addr_80003es2lan - Read device MAC address
1444 * @hw: pointer to the HW structure
1446 STATIC s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1448 s32 ret_val = E1000_SUCCESS;
1450 DEBUGFUNC("e1000_read_mac_addr_80003es2lan");
1453 * If there's an alternate MAC address place it in RAR0
1454 * so that it will override the Si installed default perm
1457 ret_val = e1000_check_alt_mac_addr_generic(hw);
1461 return e1000_read_mac_addr_generic(hw);
1465 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1466 * @hw: pointer to the HW structure
1468 * In the case of a PHY power down to save power, or to turn off link during a
1469 * driver unload, or wake on lan is not enabled, remove the link.
1471 STATIC void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1473 /* If the management interface is not enabled, then power down */
1474 if (!(hw->mac.ops.check_mng_mode(hw) ||
1475 hw->phy.ops.check_reset_block(hw)))
1476 e1000_power_down_phy_copper(hw);
1482 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1483 * @hw: pointer to the HW structure
1485 * Clears the hardware counters by reading the counter registers.
1487 STATIC void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1489 DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan");
1491 e1000_clear_hw_cntrs_base_generic(hw);
1493 E1000_READ_REG(hw, E1000_PRC64);
1494 E1000_READ_REG(hw, E1000_PRC127);
1495 E1000_READ_REG(hw, E1000_PRC255);
1496 E1000_READ_REG(hw, E1000_PRC511);
1497 E1000_READ_REG(hw, E1000_PRC1023);
1498 E1000_READ_REG(hw, E1000_PRC1522);
1499 E1000_READ_REG(hw, E1000_PTC64);
1500 E1000_READ_REG(hw, E1000_PTC127);
1501 E1000_READ_REG(hw, E1000_PTC255);
1502 E1000_READ_REG(hw, E1000_PTC511);
1503 E1000_READ_REG(hw, E1000_PTC1023);
1504 E1000_READ_REG(hw, E1000_PTC1522);
1506 E1000_READ_REG(hw, E1000_ALGNERRC);
1507 E1000_READ_REG(hw, E1000_RXERRC);
1508 E1000_READ_REG(hw, E1000_TNCRS);
1509 E1000_READ_REG(hw, E1000_CEXTERR);
1510 E1000_READ_REG(hw, E1000_TSCTC);
1511 E1000_READ_REG(hw, E1000_TSCTFC);
1513 E1000_READ_REG(hw, E1000_MGTPRC);
1514 E1000_READ_REG(hw, E1000_MGTPDC);
1515 E1000_READ_REG(hw, E1000_MGTPTC);
1517 E1000_READ_REG(hw, E1000_IAC);
1518 E1000_READ_REG(hw, E1000_ICRXOC);
1520 E1000_READ_REG(hw, E1000_ICRXPTC);
1521 E1000_READ_REG(hw, E1000_ICRXATC);
1522 E1000_READ_REG(hw, E1000_ICTXPTC);
1523 E1000_READ_REG(hw, E1000_ICTXATC);
1524 E1000_READ_REG(hw, E1000_ICTXQEC);
1525 E1000_READ_REG(hw, E1000_ICTXQMTC);
1526 E1000_READ_REG(hw, E1000_ICRXDMTC);