1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 /* 80003ES2LAN Gigabit Ethernet Controller (Copper)
35 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
38 #include "e1000_api.h"
40 STATIC s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw);
41 STATIC s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw);
42 STATIC s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw);
43 STATIC s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw);
44 STATIC void e1000_release_phy_80003es2lan(struct e1000_hw *hw);
45 STATIC s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw);
46 STATIC void e1000_release_nvm_80003es2lan(struct e1000_hw *hw);
47 STATIC s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
50 STATIC s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
53 STATIC s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
54 u16 words, u16 *data);
55 STATIC s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw);
56 STATIC s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw);
57 STATIC s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw);
58 STATIC s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
60 STATIC s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw);
61 STATIC s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw);
62 STATIC s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
63 STATIC void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
64 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
65 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
66 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
67 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
68 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
70 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
72 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw);
73 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
74 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
75 STATIC s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw);
76 STATIC void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
78 /* A table for the GG82563 cable length where the range is defined
79 * with a lower bound at "index" and the upper bound at
82 static const u16 e1000_gg82563_cable_length_table[] = {
83 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
84 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
85 (sizeof(e1000_gg82563_cable_length_table) / \
86 sizeof(e1000_gg82563_cable_length_table[0]))
89 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
90 * @hw: pointer to the HW structure
92 STATIC s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
94 struct e1000_phy_info *phy = &hw->phy;
97 DEBUGFUNC("e1000_init_phy_params_80003es2lan");
99 if (hw->phy.media_type != e1000_media_type_copper) {
100 phy->type = e1000_phy_none;
101 return E1000_SUCCESS;
103 phy->ops.power_up = e1000_power_up_phy_copper;
104 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
108 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
109 phy->reset_delay_us = 100;
110 phy->type = e1000_phy_gg82563;
112 phy->ops.acquire = e1000_acquire_phy_80003es2lan;
113 phy->ops.check_polarity = e1000_check_polarity_m88;
114 phy->ops.check_reset_block = e1000_check_reset_block_generic;
115 phy->ops.commit = e1000_phy_sw_reset_generic;
116 phy->ops.get_cfg_done = e1000_get_cfg_done_80003es2lan;
117 phy->ops.get_info = e1000_get_phy_info_m88;
118 phy->ops.release = e1000_release_phy_80003es2lan;
119 phy->ops.reset = e1000_phy_hw_reset_generic;
120 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
122 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan;
123 phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan;
124 phy->ops.read_reg = e1000_read_phy_reg_gg82563_80003es2lan;
125 phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan;
127 phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan;
129 /* This can only be done after all function pointers are setup. */
130 ret_val = e1000_get_phy_id(hw);
133 if (phy->id != GG82563_E_PHY_ID)
134 return -E1000_ERR_PHY;
140 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
141 * @hw: pointer to the HW structure
143 STATIC s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
145 struct e1000_nvm_info *nvm = &hw->nvm;
146 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
149 DEBUGFUNC("e1000_init_nvm_params_80003es2lan");
151 nvm->opcode_bits = 8;
153 switch (nvm->override) {
154 case e1000_nvm_override_spi_large:
156 nvm->address_bits = 16;
158 case e1000_nvm_override_spi_small:
160 nvm->address_bits = 8;
163 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
164 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
168 nvm->type = e1000_nvm_eeprom_spi;
170 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
171 E1000_EECD_SIZE_EX_SHIFT);
173 /* Added to a constant, "size" becomes the left-shift value
174 * for setting word_size.
176 size += NVM_WORD_SIZE_BASE_SHIFT;
178 /* EEPROM access above 16k is unsupported */
181 nvm->word_size = 1 << size;
183 /* Function Pointers */
184 nvm->ops.acquire = e1000_acquire_nvm_80003es2lan;
185 nvm->ops.read = e1000_read_nvm_eerd;
186 nvm->ops.release = e1000_release_nvm_80003es2lan;
187 nvm->ops.update = e1000_update_nvm_checksum_generic;
188 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
189 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
190 nvm->ops.write = e1000_write_nvm_80003es2lan;
192 return E1000_SUCCESS;
196 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
197 * @hw: pointer to the HW structure
199 STATIC s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
201 struct e1000_mac_info *mac = &hw->mac;
203 DEBUGFUNC("e1000_init_mac_params_80003es2lan");
205 /* Set media type and media-dependent function pointers */
206 switch (hw->device_id) {
207 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
208 hw->phy.media_type = e1000_media_type_internal_serdes;
209 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
210 mac->ops.setup_physical_interface =
211 e1000_setup_fiber_serdes_link_generic;
214 hw->phy.media_type = e1000_media_type_copper;
215 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
216 mac->ops.setup_physical_interface =
217 e1000_setup_copper_link_80003es2lan;
221 /* Set mta register count */
222 mac->mta_reg_count = 128;
223 /* Set rar entry count */
224 mac->rar_entry_count = E1000_RAR_ENTRIES;
225 /* Set if part includes ASF firmware */
226 mac->asf_firmware_present = true;
228 mac->has_fwsm = true;
229 /* ARC supported; valid only if manageability features are enabled. */
230 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) &
231 E1000_FWSM_MODE_MASK);
232 /* Adaptive IFS not supported */
233 mac->adaptive_ifs = false;
235 /* Function pointers */
237 /* bus type/speed/width */
238 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
240 mac->ops.reset_hw = e1000_reset_hw_80003es2lan;
241 /* hw initialization */
242 mac->ops.init_hw = e1000_init_hw_80003es2lan;
244 mac->ops.setup_link = e1000_setup_link_generic;
245 /* check management mode */
246 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
247 /* multicast address update */
248 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
250 mac->ops.write_vfta = e1000_write_vfta_generic;
252 mac->ops.clear_vfta = e1000_clear_vfta_generic;
253 /* read mac address */
254 mac->ops.read_mac_addr = e1000_read_mac_addr_80003es2lan;
256 mac->ops.id_led_init = e1000_id_led_init_generic;
258 mac->ops.blink_led = e1000_blink_led_generic;
260 mac->ops.setup_led = e1000_setup_led_generic;
262 mac->ops.cleanup_led = e1000_cleanup_led_generic;
263 /* turn on/off LED */
264 mac->ops.led_on = e1000_led_on_generic;
265 mac->ops.led_off = e1000_led_off_generic;
266 /* clear hardware counters */
267 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan;
269 mac->ops.get_link_up_info = e1000_get_link_up_info_80003es2lan;
271 /* set lan id for port to determine which phy lock to use */
272 hw->mac.ops.set_lan_id(hw);
274 return E1000_SUCCESS;
278 * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs.
279 * @hw: pointer to the HW structure
281 * Called to initialize all function pointers and parameters.
283 void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw)
285 DEBUGFUNC("e1000_init_function_pointers_80003es2lan");
287 hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan;
288 hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan;
289 hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan;
293 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
294 * @hw: pointer to the HW structure
296 * A wrapper to acquire access rights to the correct PHY.
298 STATIC s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
302 DEBUGFUNC("e1000_acquire_phy_80003es2lan");
304 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
305 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
309 * e1000_release_phy_80003es2lan - Release rights to access PHY
310 * @hw: pointer to the HW structure
312 * A wrapper to release access rights to the correct PHY.
314 STATIC void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
318 DEBUGFUNC("e1000_release_phy_80003es2lan");
320 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
321 e1000_release_swfw_sync_80003es2lan(hw, mask);
325 * e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register
326 * @hw: pointer to the HW structure
328 * Acquire the semaphore to access the Kumeran interface.
331 STATIC s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
335 DEBUGFUNC("e1000_acquire_mac_csr_80003es2lan");
337 mask = E1000_SWFW_CSR_SM;
339 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
343 * e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register
344 * @hw: pointer to the HW structure
346 * Release the semaphore used to access the Kumeran interface
348 STATIC void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
352 DEBUGFUNC("e1000_release_mac_csr_80003es2lan");
354 mask = E1000_SWFW_CSR_SM;
356 e1000_release_swfw_sync_80003es2lan(hw, mask);
360 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
361 * @hw: pointer to the HW structure
363 * Acquire the semaphore to access the EEPROM.
365 STATIC s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
369 DEBUGFUNC("e1000_acquire_nvm_80003es2lan");
371 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
375 ret_val = e1000_acquire_nvm_generic(hw);
378 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
384 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
385 * @hw: pointer to the HW structure
387 * Release the semaphore used to access the EEPROM.
389 STATIC void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
391 DEBUGFUNC("e1000_release_nvm_80003es2lan");
393 e1000_release_nvm_generic(hw);
394 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
398 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
399 * @hw: pointer to the HW structure
400 * @mask: specifies which semaphore to acquire
402 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
403 * will also specify which port we're acquiring the lock for.
405 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
409 u32 fwmask = mask << 16;
413 DEBUGFUNC("e1000_acquire_swfw_sync_80003es2lan");
415 while (i < timeout) {
416 if (e1000_get_hw_semaphore_generic(hw))
417 return -E1000_ERR_SWFW_SYNC;
419 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
420 if (!(swfw_sync & (fwmask | swmask)))
423 /* Firmware currently using resource (fwmask)
424 * or other software thread using resource (swmask)
426 e1000_put_hw_semaphore_generic(hw);
432 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
433 return -E1000_ERR_SWFW_SYNC;
437 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
439 e1000_put_hw_semaphore_generic(hw);
441 return E1000_SUCCESS;
445 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
446 * @hw: pointer to the HW structure
447 * @mask: specifies which semaphore to acquire
449 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
450 * will also specify which port we're releasing the lock for.
452 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
456 DEBUGFUNC("e1000_release_swfw_sync_80003es2lan");
458 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
461 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
463 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
465 e1000_put_hw_semaphore_generic(hw);
469 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
470 * @hw: pointer to the HW structure
471 * @offset: offset of the register to read
472 * @data: pointer to the data returned from the operation
474 * Read the GG82563 PHY register.
476 STATIC s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
477 u32 offset, u16 *data)
483 DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan");
485 ret_val = e1000_acquire_phy_80003es2lan(hw);
489 /* Select Configuration Page */
490 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
491 page_select = GG82563_PHY_PAGE_SELECT;
493 /* Use Alternative Page Select register to access
494 * registers 30 and 31
496 page_select = GG82563_PHY_PAGE_SELECT_ALT;
499 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
500 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
502 e1000_release_phy_80003es2lan(hw);
506 if (hw->dev_spec._80003es2lan.mdic_wa_enable) {
507 /* The "ready" bit in the MDIC register may be incorrectly set
508 * before the device has completed the "Page Select" MDI
509 * transaction. So we wait 200us after each MDI command...
513 /* ...and verify the command was successful. */
514 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
516 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
517 e1000_release_phy_80003es2lan(hw);
518 return -E1000_ERR_PHY;
523 ret_val = e1000_read_phy_reg_mdic(hw,
524 MAX_PHY_REG_ADDRESS & offset,
529 ret_val = e1000_read_phy_reg_mdic(hw,
530 MAX_PHY_REG_ADDRESS & offset,
534 e1000_release_phy_80003es2lan(hw);
540 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
541 * @hw: pointer to the HW structure
542 * @offset: offset of the register to read
543 * @data: value to write to the register
545 * Write to the GG82563 PHY register.
547 STATIC s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
548 u32 offset, u16 data)
554 DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan");
556 ret_val = e1000_acquire_phy_80003es2lan(hw);
560 /* Select Configuration Page */
561 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
562 page_select = GG82563_PHY_PAGE_SELECT;
564 /* Use Alternative Page Select register to access
565 * registers 30 and 31
567 page_select = GG82563_PHY_PAGE_SELECT_ALT;
570 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
571 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
573 e1000_release_phy_80003es2lan(hw);
577 if (hw->dev_spec._80003es2lan.mdic_wa_enable) {
578 /* The "ready" bit in the MDIC register may be incorrectly set
579 * before the device has completed the "Page Select" MDI
580 * transaction. So we wait 200us after each MDI command...
584 /* ...and verify the command was successful. */
585 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
587 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
588 e1000_release_phy_80003es2lan(hw);
589 return -E1000_ERR_PHY;
594 ret_val = e1000_write_phy_reg_mdic(hw,
595 MAX_PHY_REG_ADDRESS & offset,
600 ret_val = e1000_write_phy_reg_mdic(hw,
601 MAX_PHY_REG_ADDRESS & offset,
605 e1000_release_phy_80003es2lan(hw);
611 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM
612 * @hw: pointer to the HW structure
613 * @offset: offset of the register to read
614 * @words: number of words to write
615 * @data: buffer of data to write to the NVM
617 * Write "words" of data to the ESB2 NVM.
619 STATIC s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
620 u16 words, u16 *data)
622 DEBUGFUNC("e1000_write_nvm_80003es2lan");
624 return e1000_write_nvm_spi(hw, offset, words, data);
628 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
629 * @hw: pointer to the HW structure
631 * Wait a specific amount of time for manageability processes to complete.
632 * This is a function pointer entry point called by the phy module.
634 STATIC s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
636 s32 timeout = PHY_CFG_TIMEOUT;
637 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
639 DEBUGFUNC("e1000_get_cfg_done_80003es2lan");
641 if (hw->bus.func == 1)
642 mask = E1000_NVM_CFG_DONE_PORT_1;
645 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
651 DEBUGOUT("MNG configuration cycle has not completed.\n");
652 return -E1000_ERR_RESET;
655 return E1000_SUCCESS;
659 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
660 * @hw: pointer to the HW structure
662 * Force the speed and duplex settings onto the PHY. This is a
663 * function pointer entry point called by the phy module.
665 STATIC s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
671 DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan");
673 if (!(hw->phy.ops.read_reg))
674 return E1000_SUCCESS;
676 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
677 * forced whenever speed and duplex are forced.
679 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
683 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
684 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
688 DEBUGOUT1("GG82563 PSCR: %X\n", phy_data);
690 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data);
694 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
696 /* Reset the phy to commit changes. */
697 phy_data |= MII_CR_RESET;
699 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data);
705 if (hw->phy.autoneg_wait_to_complete) {
706 DEBUGOUT("Waiting for forced speed/duplex link on GG82563 phy.\n");
708 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
714 /* We didn't get link.
715 * Reset the DSP and cross our fingers.
717 ret_val = e1000_phy_reset_dsp_generic(hw);
723 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
729 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
734 /* Resetting the phy means we need to verify the TX_CLK corresponds
735 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
737 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
738 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
739 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
741 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
743 /* In addition, we must re-enable CRS on Tx for both half and full
746 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
747 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
754 * e1000_get_cable_length_80003es2lan - Set approximate cable length
755 * @hw: pointer to the HW structure
757 * Find the approximate cable length as measured by the GG82563 PHY.
758 * This is a function pointer entry point called by the phy module.
760 STATIC s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
762 struct e1000_phy_info *phy = &hw->phy;
763 s32 ret_val = E1000_SUCCESS;
766 DEBUGFUNC("e1000_get_cable_length_80003es2lan");
768 if (!(hw->phy.ops.read_reg))
769 return E1000_SUCCESS;
771 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
775 index = phy_data & GG82563_DSPD_CABLE_LENGTH;
777 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5)
778 return -E1000_ERR_PHY;
780 phy->min_cable_length = e1000_gg82563_cable_length_table[index];
781 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
783 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
785 return E1000_SUCCESS;
789 * e1000_get_link_up_info_80003es2lan - Report speed and duplex
790 * @hw: pointer to the HW structure
791 * @speed: pointer to speed buffer
792 * @duplex: pointer to duplex buffer
794 * Retrieve the current speed and duplex configuration.
796 STATIC s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
801 DEBUGFUNC("e1000_get_link_up_info_80003es2lan");
803 if (hw->phy.media_type == e1000_media_type_copper) {
804 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
806 hw->phy.ops.cfg_on_link_up(hw);
808 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw,
817 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
818 * @hw: pointer to the HW structure
820 * Perform a global reset to the ESB2 controller.
822 STATIC s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
828 DEBUGFUNC("e1000_reset_hw_80003es2lan");
830 /* Prevent the PCI-E bus from sticking if there is no TLP connection
831 * on the last TLP read/write transaction when MAC is reset.
833 ret_val = e1000_disable_pcie_master_generic(hw);
835 DEBUGOUT("PCI-E Master disable polling has failed.\n");
837 DEBUGOUT("Masking off all interrupts\n");
838 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
840 E1000_WRITE_REG(hw, E1000_RCTL, 0);
841 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
842 E1000_WRITE_FLUSH(hw);
846 ctrl = E1000_READ_REG(hw, E1000_CTRL);
848 ret_val = e1000_acquire_phy_80003es2lan(hw);
849 DEBUGOUT("Issuing a global reset to MAC\n");
850 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
851 e1000_release_phy_80003es2lan(hw);
853 /* Disable IBIST slave mode (far-end loopback) */
854 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
856 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
857 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
860 ret_val = e1000_get_auto_rd_done_generic(hw);
862 /* We don't want to continue accessing MAC registers. */
865 /* Clear any pending interrupt events. */
866 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
867 E1000_READ_REG(hw, E1000_ICR);
869 return e1000_check_alt_mac_addr_generic(hw);
873 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
874 * @hw: pointer to the HW structure
876 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
878 STATIC s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
880 struct e1000_mac_info *mac = &hw->mac;
886 DEBUGFUNC("e1000_init_hw_80003es2lan");
888 e1000_initialize_hw_bits_80003es2lan(hw);
890 /* Initialize identification LED */
891 ret_val = mac->ops.id_led_init(hw);
893 DEBUGOUT("Error initializing identification LED\n");
894 /* This is not fatal and we should not stop init due to this */
896 /* Disabling VLAN filtering */
897 DEBUGOUT("Initializing the IEEE VLAN\n");
898 mac->ops.clear_vfta(hw);
900 /* Setup the receive address. */
901 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
903 /* Zero out the Multicast HASH table */
904 DEBUGOUT("Zeroing the MTA\n");
905 for (i = 0; i < mac->mta_reg_count; i++)
906 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
908 /* Setup link and flow control */
909 ret_val = mac->ops.setup_link(hw);
911 /* Disable IBIST slave mode (far-end loopback) */
912 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
914 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
915 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
918 /* Set the transmit descriptor write-back policy */
919 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
920 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
921 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
922 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
924 /* ...for both queues. */
925 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
926 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
927 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
928 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
930 /* Enable retransmit on late collisions */
931 reg_data = E1000_READ_REG(hw, E1000_TCTL);
932 reg_data |= E1000_TCTL_RTLC;
933 E1000_WRITE_REG(hw, E1000_TCTL, reg_data);
935 /* Configure Gigabit Carry Extend Padding */
936 reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT);
937 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
938 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
939 E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data);
941 /* Configure Transmit Inter-Packet Gap */
942 reg_data = E1000_READ_REG(hw, E1000_TIPG);
943 reg_data &= ~E1000_TIPG_IPGT_MASK;
944 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
945 E1000_WRITE_REG(hw, E1000_TIPG, reg_data);
947 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
948 reg_data &= ~0x00100000;
949 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
951 /* default to true to enable the MDIC W/A */
952 hw->dev_spec._80003es2lan.mdic_wa_enable = true;
954 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
955 E1000_KMRNCTRLSTA_OFFSET >>
956 E1000_KMRNCTRLSTA_OFFSET_SHIFT,
959 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
960 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
961 hw->dev_spec._80003es2lan.mdic_wa_enable = false;
964 /* Clear all of the statistics registers (clear on read). It is
965 * important that we do this after we have tried to establish link
966 * because the symbol error count will increment wildly if there
969 e1000_clear_hw_cntrs_80003es2lan(hw);
975 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
976 * @hw: pointer to the HW structure
978 * Initializes required hardware-dependent bits needed for normal operation.
980 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
984 DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan");
986 /* Transmit Descriptor Control 0 */
987 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
989 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
991 /* Transmit Descriptor Control 1 */
992 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
994 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
996 /* Transmit Arbitration Control 0 */
997 reg = E1000_READ_REG(hw, E1000_TARC(0));
998 reg &= ~(0xF << 27); /* 30:27 */
999 if (hw->phy.media_type != e1000_media_type_copper)
1001 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1003 /* Transmit Arbitration Control 1 */
1004 reg = E1000_READ_REG(hw, E1000_TARC(1));
1005 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1009 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1011 /* Disable IPv6 extension header parsing because some malformed
1012 * IPv6 headers can hang the Rx.
1014 reg = E1000_READ_REG(hw, E1000_RFCTL);
1015 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1016 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
1022 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
1023 * @hw: pointer to the HW structure
1025 * Setup some GG82563 PHY registers for obtaining link
1027 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
1029 struct e1000_phy_info *phy = &hw->phy;
1034 DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan");
1036 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
1040 data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1041 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
1042 data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
1044 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
1049 * MDI/MDI-X = 0 (default)
1050 * 0 - Auto for all speeds
1053 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1055 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data);
1059 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1061 switch (phy->mdix) {
1063 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1066 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1070 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1075 * disable_polarity_correction = 0 (default)
1076 * Automatic Correction for Reversed Cable Polarity
1080 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1081 if (phy->disable_polarity_correction)
1082 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1084 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data);
1088 /* SW Reset the PHY so all changes take effect */
1089 ret_val = hw->phy.ops.commit(hw);
1091 DEBUGOUT("Error Resetting the PHY\n");
1095 /* Bypass Rx and Tx FIFO's */
1096 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1097 E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
1098 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1099 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1103 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1104 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, &data);
1107 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1108 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1109 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, data);
1113 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1117 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1118 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data);
1122 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1123 ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1124 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1126 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1130 /* Do not init these registers when the HW is in IAMT mode, since the
1131 * firmware will have already initialized them. We only initialize
1132 * them if the HW is not in IAMT mode.
1134 if (!hw->mac.ops.check_mng_mode(hw)) {
1135 /* Enable Electrical Idle on the PHY */
1136 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1137 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1142 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1147 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1148 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1154 /* Workaround: Disable padding in Kumeran interface in the MAC
1155 * and in the PHY to avoid CRC errors.
1157 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data);
1161 data |= GG82563_ICR_DIS_PADDING;
1162 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data);
1166 return E1000_SUCCESS;
1170 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1171 * @hw: pointer to the HW structure
1173 * Essentially a wrapper for setting up all things "copper" related.
1174 * This is a function pointer entry point called by the mac module.
1176 STATIC s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1182 DEBUGFUNC("e1000_setup_copper_link_80003es2lan");
1184 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1185 ctrl |= E1000_CTRL_SLU;
1186 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1187 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1189 /* Set the mac to wait the maximum time between each
1190 * iteration and increase the max iterations when
1191 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1193 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1197 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1202 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1206 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1207 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, ®_data);
1210 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1211 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1212 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, reg_data);
1216 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1220 return e1000_setup_copper_link_generic(hw);
1224 * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1225 * @hw: pointer to the HW structure
1226 * @duplex: current duplex setting
1228 * Configure the KMRN interface by applying last minute quirks for
1231 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1233 s32 ret_val = E1000_SUCCESS;
1237 DEBUGFUNC("e1000_configure_on_link_up");
1239 if (hw->phy.media_type == e1000_media_type_copper) {
1240 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, &speed,
1245 if (speed == SPEED_1000)
1246 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1248 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1255 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1256 * @hw: pointer to the HW structure
1257 * @duplex: current duplex setting
1259 * Configure the KMRN interface by applying last minute quirks for
1262 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1267 u16 reg_data, reg_data2;
1269 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
1271 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1272 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1273 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1278 /* Configure Transmit Inter-Packet Gap */
1279 tipg = E1000_READ_REG(hw, E1000_TIPG);
1280 tipg &= ~E1000_TIPG_IPGT_MASK;
1281 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1282 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1285 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1290 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1295 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1297 if (duplex == HALF_DUPLEX)
1298 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1300 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1302 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1306 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1307 * @hw: pointer to the HW structure
1309 * Configure the KMRN interface by applying last minute quirks for
1310 * gigabit operation.
1312 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1315 u16 reg_data, reg_data2;
1319 DEBUGFUNC("e1000_configure_kmrn_for_1000");
1321 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1322 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1323 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, reg_data);
1327 /* Configure Transmit Inter-Packet Gap */
1328 tipg = E1000_READ_REG(hw, E1000_TIPG);
1329 tipg &= ~E1000_TIPG_IPGT_MASK;
1330 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1331 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1334 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1339 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1344 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1346 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1348 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1352 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1353 * @hw: pointer to the HW structure
1354 * @offset: register offset to be read
1355 * @data: pointer to the read data
1357 * Acquire semaphore, then read the PHY register at offset
1358 * using the kumeran interface. The information retrieved is stored in data.
1359 * Release the semaphore before exiting.
1361 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1365 s32 ret_val = E1000_SUCCESS;
1367 DEBUGFUNC("e1000_read_kmrn_reg_80003es2lan");
1369 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1373 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1374 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1375 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1376 E1000_WRITE_FLUSH(hw);
1380 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
1381 *data = (u16)kmrnctrlsta;
1383 e1000_release_mac_csr_80003es2lan(hw);
1389 * e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1390 * @hw: pointer to the HW structure
1391 * @offset: register offset to write to
1392 * @data: data to write at register offset
1394 * Acquire semaphore, then write the data to PHY register
1395 * at the offset using the kumeran interface. Release semaphore
1398 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1402 s32 ret_val = E1000_SUCCESS;
1404 DEBUGFUNC("e1000_write_kmrn_reg_80003es2lan");
1406 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1410 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1411 E1000_KMRNCTRLSTA_OFFSET) | data;
1412 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1413 E1000_WRITE_FLUSH(hw);
1417 e1000_release_mac_csr_80003es2lan(hw);
1423 * e1000_read_mac_addr_80003es2lan - Read device MAC address
1424 * @hw: pointer to the HW structure
1426 STATIC s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1428 s32 ret_val = E1000_SUCCESS;
1430 DEBUGFUNC("e1000_read_mac_addr_80003es2lan");
1432 /* If there's an alternate MAC address place it in RAR0
1433 * so that it will override the Si installed default perm
1436 ret_val = e1000_check_alt_mac_addr_generic(hw);
1440 return e1000_read_mac_addr_generic(hw);
1444 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1445 * @hw: pointer to the HW structure
1447 * In the case of a PHY power down to save power, or to turn off link during a
1448 * driver unload, or wake on lan is not enabled, remove the link.
1450 STATIC void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1452 /* If the management interface is not enabled, then power down */
1453 if (!(hw->mac.ops.check_mng_mode(hw) ||
1454 hw->phy.ops.check_reset_block(hw)))
1455 e1000_power_down_phy_copper(hw);
1461 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1462 * @hw: pointer to the HW structure
1464 * Clears the hardware counters by reading the counter registers.
1466 STATIC void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1468 DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan");
1470 e1000_clear_hw_cntrs_base_generic(hw);
1472 E1000_READ_REG(hw, E1000_PRC64);
1473 E1000_READ_REG(hw, E1000_PRC127);
1474 E1000_READ_REG(hw, E1000_PRC255);
1475 E1000_READ_REG(hw, E1000_PRC511);
1476 E1000_READ_REG(hw, E1000_PRC1023);
1477 E1000_READ_REG(hw, E1000_PRC1522);
1478 E1000_READ_REG(hw, E1000_PTC64);
1479 E1000_READ_REG(hw, E1000_PTC127);
1480 E1000_READ_REG(hw, E1000_PTC255);
1481 E1000_READ_REG(hw, E1000_PTC511);
1482 E1000_READ_REG(hw, E1000_PTC1023);
1483 E1000_READ_REG(hw, E1000_PTC1522);
1485 E1000_READ_REG(hw, E1000_ALGNERRC);
1486 E1000_READ_REG(hw, E1000_RXERRC);
1487 E1000_READ_REG(hw, E1000_TNCRS);
1488 E1000_READ_REG(hw, E1000_CEXTERR);
1489 E1000_READ_REG(hw, E1000_TSCTC);
1490 E1000_READ_REG(hw, E1000_TSCTFC);
1492 E1000_READ_REG(hw, E1000_MGTPRC);
1493 E1000_READ_REG(hw, E1000_MGTPDC);
1494 E1000_READ_REG(hw, E1000_MGTPTC);
1496 E1000_READ_REG(hw, E1000_IAC);
1497 E1000_READ_REG(hw, E1000_ICRXOC);
1499 E1000_READ_REG(hw, E1000_ICRXPTC);
1500 E1000_READ_REG(hw, E1000_ICRXATC);
1501 E1000_READ_REG(hw, E1000_ICTXPTC);
1502 E1000_READ_REG(hw, E1000_ICTXATC);
1503 E1000_READ_REG(hw, E1000_ICTXQEC);
1504 E1000_READ_REG(hw, E1000_ICTXQMTC);
1505 E1000_READ_REG(hw, E1000_ICRXDMTC);