1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ***************************************************************************/
34 /* 82571EB Gigabit Ethernet Controller
35 * 82571EB Gigabit Ethernet Controller (Copper)
36 * 82571EB Gigabit Ethernet Controller (Fiber)
37 * 82571EB Dual Port Gigabit Mezzanine Adapter
38 * 82571EB Quad Port Gigabit Mezzanine Adapter
39 * 82571PT Gigabit PT Quad Port Server ExpressModule
40 * 82572EI Gigabit Ethernet Controller (Copper)
41 * 82572EI Gigabit Ethernet Controller (Fiber)
42 * 82572EI Gigabit Ethernet Controller
43 * 82573V Gigabit Ethernet Controller (Copper)
44 * 82573E Gigabit Ethernet Controller (Copper)
45 * 82573L Gigabit Ethernet Controller
46 * 82574L Gigabit Network Connection
47 * 82583V Gigabit Network Connection
50 #include "e1000_api.h"
52 STATIC s32 e1000_acquire_nvm_82571(struct e1000_hw *hw);
53 STATIC void e1000_release_nvm_82571(struct e1000_hw *hw);
54 STATIC s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
55 u16 words, u16 *data);
56 STATIC s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
57 STATIC s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
58 STATIC s32 e1000_get_cfg_done_82571(struct e1000_hw *hw);
59 STATIC s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
61 STATIC s32 e1000_reset_hw_82571(struct e1000_hw *hw);
62 STATIC s32 e1000_init_hw_82571(struct e1000_hw *hw);
63 STATIC void e1000_clear_vfta_82571(struct e1000_hw *hw);
64 STATIC bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
65 STATIC s32 e1000_led_on_82574(struct e1000_hw *hw);
66 STATIC s32 e1000_setup_link_82571(struct e1000_hw *hw);
67 STATIC s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
68 STATIC s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
69 STATIC s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
70 STATIC s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
71 STATIC void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
72 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw);
73 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
74 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
75 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
76 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
77 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
78 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
79 STATIC s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw,
81 STATIC s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw,
83 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
84 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
85 u16 words, u16 *data);
86 STATIC s32 e1000_read_mac_addr_82571(struct e1000_hw *hw);
87 STATIC void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
90 * e1000_init_phy_params_82571 - Init PHY func ptrs.
91 * @hw: pointer to the HW structure
93 STATIC s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
95 struct e1000_phy_info *phy = &hw->phy;
98 DEBUGFUNC("e1000_init_phy_params_82571");
100 if (hw->phy.media_type != e1000_media_type_copper) {
101 phy->type = e1000_phy_none;
102 return E1000_SUCCESS;
106 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
107 phy->reset_delay_us = 100;
109 phy->ops.check_reset_block = e1000_check_reset_block_generic;
110 phy->ops.reset = e1000_phy_hw_reset_generic;
111 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571;
112 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
113 phy->ops.power_up = e1000_power_up_phy_copper;
114 phy->ops.power_down = e1000_power_down_phy_copper_82571;
116 switch (hw->mac.type) {
119 phy->type = e1000_phy_igp_2;
120 phy->ops.get_cfg_done = e1000_get_cfg_done_82571;
121 phy->ops.get_info = e1000_get_phy_info_igp;
122 phy->ops.check_polarity = e1000_check_polarity_igp;
123 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
124 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
125 phy->ops.read_reg = e1000_read_phy_reg_igp;
126 phy->ops.write_reg = e1000_write_phy_reg_igp;
127 phy->ops.acquire = e1000_get_hw_semaphore_82571;
128 phy->ops.release = e1000_put_hw_semaphore_82571;
131 phy->type = e1000_phy_m88;
132 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
133 phy->ops.get_info = e1000_get_phy_info_m88;
134 phy->ops.check_polarity = e1000_check_polarity_m88;
135 phy->ops.commit = e1000_phy_sw_reset_generic;
136 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
137 phy->ops.get_cable_length = e1000_get_cable_length_m88;
138 phy->ops.read_reg = e1000_read_phy_reg_m88;
139 phy->ops.write_reg = e1000_write_phy_reg_m88;
140 phy->ops.acquire = e1000_get_hw_semaphore_82571;
141 phy->ops.release = e1000_put_hw_semaphore_82571;
145 E1000_MUTEX_INIT(&hw->dev_spec._82571.swflag_mutex);
147 phy->type = e1000_phy_bm;
148 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
149 phy->ops.get_info = e1000_get_phy_info_m88;
150 phy->ops.check_polarity = e1000_check_polarity_m88;
151 phy->ops.commit = e1000_phy_sw_reset_generic;
152 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
153 phy->ops.get_cable_length = e1000_get_cable_length_m88;
154 phy->ops.read_reg = e1000_read_phy_reg_bm2;
155 phy->ops.write_reg = e1000_write_phy_reg_bm2;
156 phy->ops.acquire = e1000_get_hw_semaphore_82574;
157 phy->ops.release = e1000_put_hw_semaphore_82574;
158 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
159 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
162 return -E1000_ERR_PHY;
166 /* This can only be done after all function pointers are setup. */
167 ret_val = e1000_get_phy_id_82571(hw);
169 DEBUGOUT("Error getting PHY ID\n");
174 switch (hw->mac.type) {
177 if (phy->id != IGP01E1000_I_PHY_ID)
178 ret_val = -E1000_ERR_PHY;
181 if (phy->id != M88E1111_I_PHY_ID)
182 ret_val = -E1000_ERR_PHY;
186 if (phy->id != BME1000_E_PHY_ID_R2)
187 ret_val = -E1000_ERR_PHY;
190 ret_val = -E1000_ERR_PHY;
195 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
201 * e1000_init_nvm_params_82571 - Init NVM func ptrs.
202 * @hw: pointer to the HW structure
204 STATIC s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
206 struct e1000_nvm_info *nvm = &hw->nvm;
207 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
210 DEBUGFUNC("e1000_init_nvm_params_82571");
212 nvm->opcode_bits = 8;
214 switch (nvm->override) {
215 case e1000_nvm_override_spi_large:
217 nvm->address_bits = 16;
219 case e1000_nvm_override_spi_small:
221 nvm->address_bits = 8;
224 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
225 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
229 switch (hw->mac.type) {
233 if (((eecd >> 15) & 0x3) == 0x3) {
234 nvm->type = e1000_nvm_flash_hw;
235 nvm->word_size = 2048;
236 /* Autonomous Flash update bit must be cleared due
237 * to Flash update issue.
239 eecd &= ~E1000_EECD_AUPDEN;
240 E1000_WRITE_REG(hw, E1000_EECD, eecd);
245 nvm->type = e1000_nvm_eeprom_spi;
246 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
247 E1000_EECD_SIZE_EX_SHIFT);
248 /* Added to a constant, "size" becomes the left-shift value
249 * for setting word_size.
251 size += NVM_WORD_SIZE_BASE_SHIFT;
253 /* EEPROM access above 16k is unsupported */
256 nvm->word_size = 1 << size;
260 /* Function Pointers */
261 switch (hw->mac.type) {
264 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
265 nvm->ops.release = e1000_put_hw_semaphore_82574;
268 nvm->ops.acquire = e1000_acquire_nvm_82571;
269 nvm->ops.release = e1000_release_nvm_82571;
272 nvm->ops.read = e1000_read_nvm_eerd;
273 nvm->ops.update = e1000_update_nvm_checksum_82571;
274 nvm->ops.validate = e1000_validate_nvm_checksum_82571;
275 nvm->ops.valid_led_default = e1000_valid_led_default_82571;
276 nvm->ops.write = e1000_write_nvm_82571;
278 return E1000_SUCCESS;
282 * e1000_init_mac_params_82571 - Init MAC func ptrs.
283 * @hw: pointer to the HW structure
285 STATIC s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
287 struct e1000_mac_info *mac = &hw->mac;
290 bool force_clear_smbi = false;
292 DEBUGFUNC("e1000_init_mac_params_82571");
294 /* Set media type and media-dependent function pointers */
295 switch (hw->device_id) {
296 case E1000_DEV_ID_82571EB_FIBER:
297 case E1000_DEV_ID_82572EI_FIBER:
298 case E1000_DEV_ID_82571EB_QUAD_FIBER:
299 hw->phy.media_type = e1000_media_type_fiber;
300 mac->ops.setup_physical_interface =
301 e1000_setup_fiber_serdes_link_82571;
302 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
303 mac->ops.get_link_up_info =
304 e1000_get_speed_and_duplex_fiber_serdes_generic;
306 case E1000_DEV_ID_82571EB_SERDES:
307 case E1000_DEV_ID_82571EB_SERDES_DUAL:
308 case E1000_DEV_ID_82571EB_SERDES_QUAD:
309 case E1000_DEV_ID_82572EI_SERDES:
310 hw->phy.media_type = e1000_media_type_internal_serdes;
311 mac->ops.setup_physical_interface =
312 e1000_setup_fiber_serdes_link_82571;
313 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
314 mac->ops.get_link_up_info =
315 e1000_get_speed_and_duplex_fiber_serdes_generic;
318 hw->phy.media_type = e1000_media_type_copper;
319 mac->ops.setup_physical_interface =
320 e1000_setup_copper_link_82571;
321 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
322 mac->ops.get_link_up_info =
323 e1000_get_speed_and_duplex_copper_generic;
327 /* Set mta register count */
328 mac->mta_reg_count = 128;
329 /* Set rar entry count */
330 mac->rar_entry_count = E1000_RAR_ENTRIES;
331 /* Set if part includes ASF firmware */
332 mac->asf_firmware_present = true;
333 /* Adaptive IFS supported */
334 mac->adaptive_ifs = true;
336 /* Function pointers */
338 /* bus type/speed/width */
339 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
341 mac->ops.reset_hw = e1000_reset_hw_82571;
342 /* hw initialization */
343 mac->ops.init_hw = e1000_init_hw_82571;
345 mac->ops.setup_link = e1000_setup_link_82571;
346 /* multicast address update */
347 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
349 mac->ops.write_vfta = e1000_write_vfta_generic;
351 mac->ops.clear_vfta = e1000_clear_vfta_82571;
352 /* read mac address */
353 mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
355 mac->ops.id_led_init = e1000_id_led_init_generic;
357 mac->ops.setup_led = e1000_setup_led_generic;
359 mac->ops.cleanup_led = e1000_cleanup_led_generic;
361 mac->ops.led_off = e1000_led_off_generic;
362 /* clear hardware counters */
363 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
365 /* MAC-specific function pointers */
366 switch (hw->mac.type) {
368 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
369 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
370 mac->ops.led_on = e1000_led_on_generic;
371 mac->ops.blink_led = e1000_blink_led_generic;
374 mac->has_fwsm = true;
375 /* ARC supported; valid only if manageability features are
378 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) &
379 E1000_FWSM_MODE_MASK);
383 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
384 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
385 mac->ops.led_on = e1000_led_on_82574;
388 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
389 mac->ops.led_on = e1000_led_on_generic;
390 mac->ops.blink_led = e1000_blink_led_generic;
393 mac->has_fwsm = true;
397 /* Ensure that the inter-port SWSM.SMBI lock bit is clear before
398 * first NVM or PHY acess. This should be done for single-port
399 * devices, and for one port only on dual-port devices so that
400 * for those devices we can still use the SMBI lock to synchronize
401 * inter-port accesses to the PHY & NVM.
403 switch (hw->mac.type) {
406 swsm2 = E1000_READ_REG(hw, E1000_SWSM2);
408 if (!(swsm2 & E1000_SWSM2_LOCK)) {
409 /* Only do this for the first interface on this card */
410 E1000_WRITE_REG(hw, E1000_SWSM2, swsm2 |
412 force_clear_smbi = true;
414 force_clear_smbi = false;
418 force_clear_smbi = true;
422 if (force_clear_smbi) {
423 /* Make sure SWSM.SMBI is clear */
424 swsm = E1000_READ_REG(hw, E1000_SWSM);
425 if (swsm & E1000_SWSM_SMBI) {
426 /* This bit should not be set on a first interface, and
427 * indicates that the bootagent or EFI code has
428 * improperly left this bit enabled
430 DEBUGOUT("Please update your 82571 Bootagent\n");
432 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI);
435 /* Initialze device specific counter of SMBI acquisition timeouts. */
436 hw->dev_spec._82571.smb_counter = 0;
438 return E1000_SUCCESS;
442 * e1000_init_function_pointers_82571 - Init func ptrs.
443 * @hw: pointer to the HW structure
445 * Called to initialize all function pointers and parameters.
447 void e1000_init_function_pointers_82571(struct e1000_hw *hw)
449 DEBUGFUNC("e1000_init_function_pointers_82571");
451 hw->mac.ops.init_params = e1000_init_mac_params_82571;
452 hw->nvm.ops.init_params = e1000_init_nvm_params_82571;
453 hw->phy.ops.init_params = e1000_init_phy_params_82571;
457 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
458 * @hw: pointer to the HW structure
460 * Reads the PHY registers and stores the PHY ID and possibly the PHY
461 * revision in the hardware structure.
463 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
465 struct e1000_phy_info *phy = &hw->phy;
469 DEBUGFUNC("e1000_get_phy_id_82571");
471 switch (hw->mac.type) {
474 /* The 82571 firmware may still be configuring the PHY.
475 * In this case, we cannot access the PHY until the
476 * configuration is done. So we explicitly set the
479 phy->id = IGP01E1000_I_PHY_ID;
482 return e1000_get_phy_id(hw);
486 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
490 phy->id = (u32)(phy_id << 16);
492 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
496 phy->id |= (u32)(phy_id);
497 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
500 return -E1000_ERR_PHY;
504 return E1000_SUCCESS;
508 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
509 * @hw: pointer to the HW structure
511 * Acquire the HW semaphore to access the PHY or NVM
513 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
516 s32 sw_timeout = hw->nvm.word_size + 1;
517 s32 fw_timeout = hw->nvm.word_size + 1;
520 DEBUGFUNC("e1000_get_hw_semaphore_82571");
522 /* If we have timedout 3 times on trying to acquire
523 * the inter-port SMBI semaphore, there is old code
524 * operating on the other port, and it is not
525 * releasing SMBI. Modify the number of times that
526 * we try for the semaphore to interwork with this
529 if (hw->dev_spec._82571.smb_counter > 2)
532 /* Get the SW semaphore */
533 while (i < sw_timeout) {
534 swsm = E1000_READ_REG(hw, E1000_SWSM);
535 if (!(swsm & E1000_SWSM_SMBI))
542 if (i == sw_timeout) {
543 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
544 hw->dev_spec._82571.smb_counter++;
546 /* Get the FW semaphore. */
547 for (i = 0; i < fw_timeout; i++) {
548 swsm = E1000_READ_REG(hw, E1000_SWSM);
549 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
551 /* Semaphore acquired if bit latched */
552 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
558 if (i == fw_timeout) {
559 /* Release semaphores */
560 e1000_put_hw_semaphore_82571(hw);
561 DEBUGOUT("Driver can't access the NVM\n");
562 return -E1000_ERR_NVM;
565 return E1000_SUCCESS;
569 * e1000_put_hw_semaphore_82571 - Release hardware semaphore
570 * @hw: pointer to the HW structure
572 * Release hardware semaphore used to access the PHY or NVM
574 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
578 DEBUGFUNC("e1000_put_hw_semaphore_generic");
580 swsm = E1000_READ_REG(hw, E1000_SWSM);
582 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
584 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
588 * e1000_get_hw_semaphore_82573 - Acquire hardware semaphore
589 * @hw: pointer to the HW structure
591 * Acquire the HW semaphore during reset.
594 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
599 DEBUGFUNC("e1000_get_hw_semaphore_82573");
601 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
603 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
604 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
605 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
607 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
612 } while (i < MDIO_OWNERSHIP_TIMEOUT);
614 if (i == MDIO_OWNERSHIP_TIMEOUT) {
615 /* Release semaphores */
616 e1000_put_hw_semaphore_82573(hw);
617 DEBUGOUT("Driver can't access the PHY\n");
618 return -E1000_ERR_PHY;
621 return E1000_SUCCESS;
625 * e1000_put_hw_semaphore_82573 - Release hardware semaphore
626 * @hw: pointer to the HW structure
628 * Release hardware semaphore used during reset.
631 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
635 DEBUGFUNC("e1000_put_hw_semaphore_82573");
637 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
638 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
639 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
643 * e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
644 * @hw: pointer to the HW structure
646 * Acquire the HW semaphore to access the PHY or NVM.
649 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
653 DEBUGFUNC("e1000_get_hw_semaphore_82574");
655 E1000_MUTEX_LOCK(&hw->dev_spec._82571.swflag_mutex);
656 ret_val = e1000_get_hw_semaphore_82573(hw);
658 E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex);
663 * e1000_put_hw_semaphore_82574 - Release hardware semaphore
664 * @hw: pointer to the HW structure
666 * Release hardware semaphore used to access the PHY or NVM
669 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
671 DEBUGFUNC("e1000_put_hw_semaphore_82574");
673 e1000_put_hw_semaphore_82573(hw);
674 E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex);
678 * e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state
679 * @hw: pointer to the HW structure
680 * @active: true to enable LPLU, false to disable
682 * Sets the LPLU D0 state according to the active flag.
683 * LPLU will not be activated unless the
684 * device autonegotiation advertisement meets standards of
685 * either 10 or 10/100 or 10/100/1000 at all duplexes.
686 * This is a function pointer entry point only called by
687 * PHY setup routines.
689 STATIC s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
691 u32 data = E1000_READ_REG(hw, E1000_POEMB);
693 DEBUGFUNC("e1000_set_d0_lplu_state_82574");
696 data |= E1000_PHY_CTRL_D0A_LPLU;
698 data &= ~E1000_PHY_CTRL_D0A_LPLU;
700 E1000_WRITE_REG(hw, E1000_POEMB, data);
701 return E1000_SUCCESS;
705 * e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3
706 * @hw: pointer to the HW structure
707 * @active: boolean used to enable/disable lplu
709 * The low power link up (lplu) state is set to the power management level D3
710 * when active is true, else clear lplu for D3. LPLU
711 * is used during Dx states where the power conservation is most important.
712 * During driver activity, SmartSpeed should be enabled so performance is
715 STATIC s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
717 u32 data = E1000_READ_REG(hw, E1000_POEMB);
719 DEBUGFUNC("e1000_set_d3_lplu_state_82574");
722 data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
723 } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
724 (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
725 (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
726 data |= E1000_PHY_CTRL_NOND0A_LPLU;
729 E1000_WRITE_REG(hw, E1000_POEMB, data);
730 return E1000_SUCCESS;
734 * e1000_acquire_nvm_82571 - Request for access to the EEPROM
735 * @hw: pointer to the HW structure
737 * To gain access to the EEPROM, first we must obtain a hardware semaphore.
738 * Then for non-82573 hardware, set the EEPROM access request bit and wait
739 * for EEPROM access grant bit. If the access grant bit is not set, release
740 * hardware semaphore.
742 STATIC s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
746 DEBUGFUNC("e1000_acquire_nvm_82571");
748 ret_val = e1000_get_hw_semaphore_82571(hw);
752 switch (hw->mac.type) {
756 ret_val = e1000_acquire_nvm_generic(hw);
761 e1000_put_hw_semaphore_82571(hw);
767 * e1000_release_nvm_82571 - Release exclusive access to EEPROM
768 * @hw: pointer to the HW structure
770 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
772 STATIC void e1000_release_nvm_82571(struct e1000_hw *hw)
774 DEBUGFUNC("e1000_release_nvm_82571");
776 e1000_release_nvm_generic(hw);
777 e1000_put_hw_semaphore_82571(hw);
781 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
782 * @hw: pointer to the HW structure
783 * @offset: offset within the EEPROM to be written to
784 * @words: number of words to write
785 * @data: 16 bit word(s) to be written to the EEPROM
787 * For non-82573 silicon, write data to EEPROM at offset using SPI interface.
789 * If e1000_update_nvm_checksum is not called after this function, the
790 * EEPROM will most likely contain an invalid checksum.
792 STATIC s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
797 DEBUGFUNC("e1000_write_nvm_82571");
799 switch (hw->mac.type) {
803 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
807 ret_val = e1000_write_nvm_spi(hw, offset, words, data);
810 ret_val = -E1000_ERR_NVM;
818 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum
819 * @hw: pointer to the HW structure
821 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
822 * up to the checksum. Then calculates the EEPROM checksum and writes the
823 * value to the EEPROM.
825 STATIC s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
831 DEBUGFUNC("e1000_update_nvm_checksum_82571");
833 ret_val = e1000_update_nvm_checksum_generic(hw);
837 /* If our nvm is an EEPROM, then we're done
838 * otherwise, commit the checksum to the flash NVM.
840 if (hw->nvm.type != e1000_nvm_flash_hw)
841 return E1000_SUCCESS;
843 /* Check for pending operations. */
844 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
846 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
850 if (i == E1000_FLASH_UPDATES)
851 return -E1000_ERR_NVM;
853 /* Reset the firmware if using STM opcode. */
854 if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) {
855 /* The enabling of and the actual reset must be done
856 * in two write cycles.
858 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE);
859 E1000_WRITE_FLUSH(hw);
860 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET);
863 /* Commit the write to flash */
864 eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD;
865 E1000_WRITE_REG(hw, E1000_EECD, eecd);
867 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
869 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
873 if (i == E1000_FLASH_UPDATES)
874 return -E1000_ERR_NVM;
876 return E1000_SUCCESS;
880 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
881 * @hw: pointer to the HW structure
883 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
884 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
886 STATIC s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
888 DEBUGFUNC("e1000_validate_nvm_checksum_82571");
890 if (hw->nvm.type == e1000_nvm_flash_hw)
891 e1000_fix_nvm_checksum_82571(hw);
893 return e1000_validate_nvm_checksum_generic(hw);
897 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
898 * @hw: pointer to the HW structure
899 * @offset: offset within the EEPROM to be written to
900 * @words: number of words to write
901 * @data: 16 bit word(s) to be written to the EEPROM
903 * After checking for invalid values, poll the EEPROM to ensure the previous
904 * command has completed before trying to write the next word. After write
905 * poll for completion.
907 * If e1000_update_nvm_checksum is not called after this function, the
908 * EEPROM will most likely contain an invalid checksum.
910 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
911 u16 words, u16 *data)
913 struct e1000_nvm_info *nvm = &hw->nvm;
915 s32 ret_val = E1000_SUCCESS;
917 DEBUGFUNC("e1000_write_nvm_eewr_82571");
919 /* A check for invalid values: offset too large, too many words,
920 * and not enough words.
922 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
924 DEBUGOUT("nvm parameter(s) out of bounds\n");
925 return -E1000_ERR_NVM;
928 for (i = 0; i < words; i++) {
929 eewr = ((data[i] << E1000_NVM_RW_REG_DATA) |
930 ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) |
931 E1000_NVM_RW_REG_START);
933 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
937 E1000_WRITE_REG(hw, E1000_EEWR, eewr);
939 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
948 * e1000_get_cfg_done_82571 - Poll for configuration done
949 * @hw: pointer to the HW structure
951 * Reads the management control register for the config done bit to be set.
953 STATIC s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
955 s32 timeout = PHY_CFG_TIMEOUT;
957 DEBUGFUNC("e1000_get_cfg_done_82571");
960 if (E1000_READ_REG(hw, E1000_EEMNGCTL) &
961 E1000_NVM_CFG_DONE_PORT_0)
967 DEBUGOUT("MNG configuration cycle has not completed.\n");
968 return -E1000_ERR_RESET;
971 return E1000_SUCCESS;
975 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
976 * @hw: pointer to the HW structure
977 * @active: true to enable LPLU, false to disable
979 * Sets the LPLU D0 state according to the active flag. When activating LPLU
980 * this function also disables smart speed and vice versa. LPLU will not be
981 * activated unless the device autonegotiation advertisement meets standards
982 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function
983 * pointer entry point only called by PHY setup routines.
985 STATIC s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
987 struct e1000_phy_info *phy = &hw->phy;
991 DEBUGFUNC("e1000_set_d0_lplu_state_82571");
993 if (!(phy->ops.read_reg))
994 return E1000_SUCCESS;
996 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1001 data |= IGP02E1000_PM_D0_LPLU;
1002 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1007 /* When LPLU is enabled, we should disable SmartSpeed */
1008 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1012 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1013 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1018 data &= ~IGP02E1000_PM_D0_LPLU;
1019 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1021 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1022 * during Dx states where the power conservation is most
1023 * important. During driver activity we should enable
1024 * SmartSpeed, so performance is maintained.
1026 if (phy->smart_speed == e1000_smart_speed_on) {
1027 ret_val = phy->ops.read_reg(hw,
1028 IGP01E1000_PHY_PORT_CONFIG,
1033 data |= IGP01E1000_PSCFR_SMART_SPEED;
1034 ret_val = phy->ops.write_reg(hw,
1035 IGP01E1000_PHY_PORT_CONFIG,
1039 } else if (phy->smart_speed == e1000_smart_speed_off) {
1040 ret_val = phy->ops.read_reg(hw,
1041 IGP01E1000_PHY_PORT_CONFIG,
1046 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1047 ret_val = phy->ops.write_reg(hw,
1048 IGP01E1000_PHY_PORT_CONFIG,
1055 return E1000_SUCCESS;
1059 * e1000_reset_hw_82571 - Reset hardware
1060 * @hw: pointer to the HW structure
1062 * This resets the hardware into a known state.
1064 STATIC s32 e1000_reset_hw_82571(struct e1000_hw *hw)
1066 u32 ctrl, ctrl_ext, eecd, tctl;
1069 DEBUGFUNC("e1000_reset_hw_82571");
1071 /* Prevent the PCI-E bus from sticking if there is no TLP connection
1072 * on the last TLP read/write transaction when MAC is reset.
1074 ret_val = e1000_disable_pcie_master_generic(hw);
1076 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1078 DEBUGOUT("Masking off all interrupts\n");
1079 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1081 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1082 tctl = E1000_READ_REG(hw, E1000_TCTL);
1083 tctl &= ~E1000_TCTL_EN;
1084 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1085 E1000_WRITE_FLUSH(hw);
1089 /* Must acquire the MDIO ownership before MAC reset.
1090 * Ownership defaults to firmware after a reset.
1092 switch (hw->mac.type) {
1094 ret_val = e1000_get_hw_semaphore_82573(hw);
1098 ret_val = e1000_get_hw_semaphore_82574(hw);
1104 DEBUGOUT("Cannot acquire MDIO ownership\n");
1106 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1108 DEBUGOUT("Issuing a global reset to MAC\n");
1109 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1111 /* Must release MDIO ownership and mutex after MAC reset. */
1112 switch (hw->mac.type) {
1115 e1000_put_hw_semaphore_82574(hw);
1121 if (hw->nvm.type == e1000_nvm_flash_hw) {
1123 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1124 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1125 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1126 E1000_WRITE_FLUSH(hw);
1129 ret_val = e1000_get_auto_rd_done_generic(hw);
1131 /* We don't want to continue accessing MAC registers. */
1134 /* Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1135 * Need to wait for Phy configuration completion before accessing
1139 switch (hw->mac.type) {
1142 /* REQ and GNT bits need to be cleared when using AUTO_RD
1143 * to access the EEPROM.
1145 eecd = E1000_READ_REG(hw, E1000_EECD);
1146 eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);
1147 E1000_WRITE_REG(hw, E1000_EECD, eecd);
1158 /* Clear any pending interrupt events. */
1159 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1160 E1000_READ_REG(hw, E1000_ICR);
1162 if (hw->mac.type == e1000_82571) {
1163 /* Install any alternate MAC address into RAR0 */
1164 ret_val = e1000_check_alt_mac_addr_generic(hw);
1168 e1000_set_laa_state_82571(hw, true);
1171 /* Reinitialize the 82571 serdes link state machine */
1172 if (hw->phy.media_type == e1000_media_type_internal_serdes)
1173 hw->mac.serdes_link_state = e1000_serdes_link_down;
1175 return E1000_SUCCESS;
1179 * e1000_init_hw_82571 - Initialize hardware
1180 * @hw: pointer to the HW structure
1182 * This inits the hardware readying it for operation.
1184 STATIC s32 e1000_init_hw_82571(struct e1000_hw *hw)
1186 struct e1000_mac_info *mac = &hw->mac;
1189 u16 i, rar_count = mac->rar_entry_count;
1191 DEBUGFUNC("e1000_init_hw_82571");
1193 e1000_initialize_hw_bits_82571(hw);
1195 /* Initialize identification LED */
1196 ret_val = mac->ops.id_led_init(hw);
1197 /* An error is not fatal and we should not stop init due to this */
1199 DEBUGOUT("Error initializing identification LED\n");
1201 /* Disabling VLAN filtering */
1202 DEBUGOUT("Initializing the IEEE VLAN\n");
1203 mac->ops.clear_vfta(hw);
1205 /* Setup the receive address.
1206 * If, however, a locally administered address was assigned to the
1207 * 82571, we must reserve a RAR for it to work around an issue where
1208 * resetting one port will reload the MAC on the other port.
1210 if (e1000_get_laa_state_82571(hw))
1212 e1000_init_rx_addrs_generic(hw, rar_count);
1214 /* Zero out the Multicast HASH table */
1215 DEBUGOUT("Zeroing the MTA\n");
1216 for (i = 0; i < mac->mta_reg_count; i++)
1217 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1219 /* Setup link and flow control */
1220 ret_val = mac->ops.setup_link(hw);
1222 /* Set the transmit descriptor write-back policy */
1223 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
1224 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1225 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
1226 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
1228 /* ...for both queues. */
1229 switch (mac->type) {
1231 e1000_enable_tx_pkt_filtering_generic(hw);
1235 reg_data = E1000_READ_REG(hw, E1000_GCR);
1236 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1237 E1000_WRITE_REG(hw, E1000_GCR, reg_data);
1240 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
1241 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1242 E1000_TXDCTL_FULL_TX_DESC_WB |
1243 E1000_TXDCTL_COUNT_DESC);
1244 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
1248 /* Clear all of the statistics registers (clear on read). It is
1249 * important that we do this after we have tried to establish link
1250 * because the symbol error count will increment wildly if there
1253 e1000_clear_hw_cntrs_82571(hw);
1259 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1260 * @hw: pointer to the HW structure
1262 * Initializes required hardware-dependent bits needed for normal operation.
1264 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1268 DEBUGFUNC("e1000_initialize_hw_bits_82571");
1270 /* Transmit Descriptor Control 0 */
1271 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1273 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1275 /* Transmit Descriptor Control 1 */
1276 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1278 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1280 /* Transmit Arbitration Control 0 */
1281 reg = E1000_READ_REG(hw, E1000_TARC(0));
1282 reg &= ~(0xF << 27); /* 30:27 */
1283 switch (hw->mac.type) {
1286 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1295 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1297 /* Transmit Arbitration Control 1 */
1298 reg = E1000_READ_REG(hw, E1000_TARC(1));
1299 switch (hw->mac.type) {
1302 reg &= ~((1 << 29) | (1 << 30));
1303 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1304 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1308 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1314 /* Device Control */
1315 switch (hw->mac.type) {
1319 reg = E1000_READ_REG(hw, E1000_CTRL);
1321 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1327 /* Extended Device Control */
1328 switch (hw->mac.type) {
1332 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1335 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1341 if (hw->mac.type == e1000_82571) {
1342 reg = E1000_READ_REG(hw, E1000_PBA_ECC);
1343 reg |= E1000_PBA_ECC_CORR_EN;
1344 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg);
1347 /* Workaround for hardware errata.
1348 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1350 if ((hw->mac.type == e1000_82571) ||
1351 (hw->mac.type == e1000_82572)) {
1352 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1353 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1354 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1357 /* Disable IPv6 extension header parsing because some malformed
1358 * IPv6 headers can hang the Rx.
1360 if (hw->mac.type <= e1000_82573) {
1361 reg = E1000_READ_REG(hw, E1000_RFCTL);
1362 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1363 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
1366 /* PCI-Ex Control Registers */
1367 switch (hw->mac.type) {
1370 reg = E1000_READ_REG(hw, E1000_GCR);
1372 E1000_WRITE_REG(hw, E1000_GCR, reg);
1374 /* Workaround for hardware errata.
1375 * apply workaround for hardware errata documented in errata
1376 * docs Fixes issue where some error prone or unreliable PCIe
1377 * completions are occurring, particularly with ASPM enabled.
1378 * Without fix, issue can cause Tx timeouts.
1380 reg = E1000_READ_REG(hw, E1000_GCR2);
1382 E1000_WRITE_REG(hw, E1000_GCR2, reg);
1392 * e1000_clear_vfta_82571 - Clear VLAN filter table
1393 * @hw: pointer to the HW structure
1395 * Clears the register array which contains the VLAN filter table by
1396 * setting all the values to 0.
1398 STATIC void e1000_clear_vfta_82571(struct e1000_hw *hw)
1402 u32 vfta_offset = 0;
1403 u32 vfta_bit_in_reg = 0;
1405 DEBUGFUNC("e1000_clear_vfta_82571");
1407 switch (hw->mac.type) {
1411 if (hw->mng_cookie.vlan_id != 0) {
1412 /* The VFTA is a 4096b bit-field, each identifying
1413 * a single VLAN ID. The following operations
1414 * determine which 32b entry (i.e. offset) into the
1415 * array we want to set the VLAN ID (i.e. bit) of
1416 * the manageability unit.
1418 vfta_offset = (hw->mng_cookie.vlan_id >>
1419 E1000_VFTA_ENTRY_SHIFT) &
1420 E1000_VFTA_ENTRY_MASK;
1422 1 << (hw->mng_cookie.vlan_id &
1423 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1429 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1430 /* If the offset we want to clear is the same offset of the
1431 * manageability VLAN ID, then clear all bits except that of
1432 * the manageability unit.
1434 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1435 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1436 E1000_WRITE_FLUSH(hw);
1441 * e1000_check_mng_mode_82574 - Check manageability is enabled
1442 * @hw: pointer to the HW structure
1444 * Reads the NVM Initialization Control Word 2 and returns true
1445 * (>0) if any manageability is enabled, else false (0).
1447 STATIC bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1451 DEBUGFUNC("e1000_check_mng_mode_82574");
1453 hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1454 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1458 * e1000_led_on_82574 - Turn LED on
1459 * @hw: pointer to the HW structure
1463 STATIC s32 e1000_led_on_82574(struct e1000_hw *hw)
1468 DEBUGFUNC("e1000_led_on_82574");
1470 ctrl = hw->mac.ledctl_mode2;
1471 if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) {
1472 /* If no link, then turn LED on by setting the invert bit
1473 * for each LED that's "on" (0x0E) in ledctl_mode2.
1475 for (i = 0; i < 4; i++)
1476 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1477 E1000_LEDCTL_MODE_LED_ON)
1478 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1480 E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl);
1482 return E1000_SUCCESS;
1486 * e1000_check_phy_82574 - check 82574 phy hung state
1487 * @hw: pointer to the HW structure
1489 * Returns whether phy is hung or not
1491 bool e1000_check_phy_82574(struct e1000_hw *hw)
1493 u16 status_1kbt = 0;
1494 u16 receive_errors = 0;
1497 DEBUGFUNC("e1000_check_phy_82574");
1499 /* Read PHY Receive Error counter first, if its is max - all F's then
1500 * read the Base1000T status register If both are max then PHY is hung.
1502 ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,
1506 if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1507 ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,
1511 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1512 E1000_IDLE_ERROR_COUNT_MASK)
1521 * e1000_setup_link_82571 - Setup flow control and link settings
1522 * @hw: pointer to the HW structure
1524 * Determines which flow control settings to use, then configures flow
1525 * control. Calls the appropriate media-specific link configuration
1526 * function. Assuming the adapter has a valid link partner, a valid link
1527 * should be established. Assumes the hardware has previously been reset
1528 * and the transmitter and receiver are not enabled.
1530 STATIC s32 e1000_setup_link_82571(struct e1000_hw *hw)
1532 DEBUGFUNC("e1000_setup_link_82571");
1534 /* 82573 does not have a word in the NVM to determine
1535 * the default flow control setting, so we explicitly
1538 switch (hw->mac.type) {
1542 if (hw->fc.requested_mode == e1000_fc_default)
1543 hw->fc.requested_mode = e1000_fc_full;
1549 return e1000_setup_link_generic(hw);
1553 * e1000_setup_copper_link_82571 - Configure copper link settings
1554 * @hw: pointer to the HW structure
1556 * Configures the link for auto-neg or forced speed and duplex. Then we check
1557 * for link, once link is established calls to configure collision distance
1558 * and flow control are called.
1560 STATIC s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1565 DEBUGFUNC("e1000_setup_copper_link_82571");
1567 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1568 ctrl |= E1000_CTRL_SLU;
1569 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1570 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1572 switch (hw->phy.type) {
1575 ret_val = e1000_copper_link_setup_m88(hw);
1577 case e1000_phy_igp_2:
1578 ret_val = e1000_copper_link_setup_igp(hw);
1581 return -E1000_ERR_PHY;
1588 return e1000_setup_copper_link_generic(hw);
1592 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1593 * @hw: pointer to the HW structure
1595 * Configures collision distance and flow control for fiber and serdes links.
1596 * Upon successful setup, poll for link.
1598 STATIC s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1600 DEBUGFUNC("e1000_setup_fiber_serdes_link_82571");
1602 switch (hw->mac.type) {
1605 /* If SerDes loopback mode is entered, there is no form
1606 * of reset to take the adapter out of that mode. So we
1607 * have to explicitly take the adapter out of loopback
1608 * mode. This prevents drivers from twiddling their thumbs
1609 * if another tool failed to take it out of loopback mode.
1611 E1000_WRITE_REG(hw, E1000_SCTL,
1612 E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1618 return e1000_setup_fiber_serdes_link_generic(hw);
1622 * e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1623 * @hw: pointer to the HW structure
1625 * Reports the link state as up or down.
1627 * If autonegotiation is supported by the link partner, the link state is
1628 * determined by the result of autonegotiation. This is the most likely case.
1629 * If autonegotiation is not supported by the link partner, and the link
1630 * has a valid signal, force the link up.
1632 * The link state is represented internally here by 4 states:
1635 * 2) autoneg_progress
1636 * 3) autoneg_complete (the link successfully autonegotiated)
1637 * 4) forced_up (the link has been forced up, it did not autonegotiate)
1640 STATIC s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1642 struct e1000_mac_info *mac = &hw->mac;
1648 s32 ret_val = E1000_SUCCESS;
1650 DEBUGFUNC("e1000_check_for_serdes_link_82571");
1652 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1653 status = E1000_READ_REG(hw, E1000_STATUS);
1654 E1000_READ_REG(hw, E1000_RXCW);
1655 /* SYNCH bit and IV bit are sticky */
1657 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1659 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1660 /* Receiver is synchronized with no invalid bits. */
1661 switch (mac->serdes_link_state) {
1662 case e1000_serdes_link_autoneg_complete:
1663 if (!(status & E1000_STATUS_LU)) {
1664 /* We have lost link, retry autoneg before
1665 * reporting link failure
1667 mac->serdes_link_state =
1668 e1000_serdes_link_autoneg_progress;
1669 mac->serdes_has_link = false;
1670 DEBUGOUT("AN_UP -> AN_PROG\n");
1672 mac->serdes_has_link = true;
1676 case e1000_serdes_link_forced_up:
1677 /* If we are receiving /C/ ordered sets, re-enable
1678 * auto-negotiation in the TXCW register and disable
1679 * forced link in the Device Control register in an
1680 * attempt to auto-negotiate with our link partner.
1682 if (rxcw & E1000_RXCW_C) {
1683 /* Enable autoneg, and unforce link up */
1684 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1685 E1000_WRITE_REG(hw, E1000_CTRL,
1686 (ctrl & ~E1000_CTRL_SLU));
1687 mac->serdes_link_state =
1688 e1000_serdes_link_autoneg_progress;
1689 mac->serdes_has_link = false;
1690 DEBUGOUT("FORCED_UP -> AN_PROG\n");
1692 mac->serdes_has_link = true;
1696 case e1000_serdes_link_autoneg_progress:
1697 if (rxcw & E1000_RXCW_C) {
1698 /* We received /C/ ordered sets, meaning the
1699 * link partner has autonegotiated, and we can
1700 * trust the Link Up (LU) status bit.
1702 if (status & E1000_STATUS_LU) {
1703 mac->serdes_link_state =
1704 e1000_serdes_link_autoneg_complete;
1705 DEBUGOUT("AN_PROG -> AN_UP\n");
1706 mac->serdes_has_link = true;
1708 /* Autoneg completed, but failed. */
1709 mac->serdes_link_state =
1710 e1000_serdes_link_down;
1711 DEBUGOUT("AN_PROG -> DOWN\n");
1714 /* The link partner did not autoneg.
1715 * Force link up and full duplex, and change
1718 E1000_WRITE_REG(hw, E1000_TXCW,
1719 (mac->txcw & ~E1000_TXCW_ANE));
1720 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1721 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1723 /* Configure Flow Control after link up. */
1725 e1000_config_fc_after_link_up_generic(hw);
1727 DEBUGOUT("Error config flow control\n");
1730 mac->serdes_link_state =
1731 e1000_serdes_link_forced_up;
1732 mac->serdes_has_link = true;
1733 DEBUGOUT("AN_PROG -> FORCED_UP\n");
1737 case e1000_serdes_link_down:
1739 /* The link was down but the receiver has now gained
1740 * valid sync, so lets see if we can bring the link
1743 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1744 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl &
1746 mac->serdes_link_state =
1747 e1000_serdes_link_autoneg_progress;
1748 mac->serdes_has_link = false;
1749 DEBUGOUT("DOWN -> AN_PROG\n");
1753 if (!(rxcw & E1000_RXCW_SYNCH)) {
1754 mac->serdes_has_link = false;
1755 mac->serdes_link_state = e1000_serdes_link_down;
1756 DEBUGOUT("ANYSTATE -> DOWN\n");
1758 /* Check several times, if SYNCH bit and CONFIG
1759 * bit both are consistently 1 then simply ignore
1760 * the IV bit and restart Autoneg
1762 for (i = 0; i < AN_RETRY_COUNT; i++) {
1764 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1765 if ((rxcw & E1000_RXCW_SYNCH) &&
1766 (rxcw & E1000_RXCW_C))
1769 if (rxcw & E1000_RXCW_IV) {
1770 mac->serdes_has_link = false;
1771 mac->serdes_link_state =
1772 e1000_serdes_link_down;
1773 DEBUGOUT("ANYSTATE -> DOWN\n");
1778 if (i == AN_RETRY_COUNT) {
1779 txcw = E1000_READ_REG(hw, E1000_TXCW);
1780 txcw |= E1000_TXCW_ANE;
1781 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1782 mac->serdes_link_state =
1783 e1000_serdes_link_autoneg_progress;
1784 mac->serdes_has_link = false;
1785 DEBUGOUT("ANYSTATE -> AN_PROG\n");
1794 * e1000_valid_led_default_82571 - Verify a valid default LED config
1795 * @hw: pointer to the HW structure
1796 * @data: pointer to the NVM (EEPROM)
1798 * Read the EEPROM for the current default LED configuration. If the
1799 * LED configuration is not valid, set to a valid LED configuration.
1801 STATIC s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1805 DEBUGFUNC("e1000_valid_led_default_82571");
1807 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1809 DEBUGOUT("NVM Read Error\n");
1813 switch (hw->mac.type) {
1817 if (*data == ID_LED_RESERVED_F746)
1818 *data = ID_LED_DEFAULT_82573;
1821 if (*data == ID_LED_RESERVED_0000 ||
1822 *data == ID_LED_RESERVED_FFFF)
1823 *data = ID_LED_DEFAULT;
1827 return E1000_SUCCESS;
1831 * e1000_get_laa_state_82571 - Get locally administered address state
1832 * @hw: pointer to the HW structure
1834 * Retrieve and return the current locally administered address state.
1836 bool e1000_get_laa_state_82571(struct e1000_hw *hw)
1838 DEBUGFUNC("e1000_get_laa_state_82571");
1840 if (hw->mac.type != e1000_82571)
1843 return hw->dev_spec._82571.laa_is_present;
1847 * e1000_set_laa_state_82571 - Set locally administered address state
1848 * @hw: pointer to the HW structure
1849 * @state: enable/disable locally administered address
1851 * Enable/Disable the current locally administered address state.
1853 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state)
1855 DEBUGFUNC("e1000_set_laa_state_82571");
1857 if (hw->mac.type != e1000_82571)
1860 hw->dev_spec._82571.laa_is_present = state;
1862 /* If workaround is activated... */
1864 /* Hold a copy of the LAA in RAR[14] This is done so that
1865 * between the time RAR[0] gets clobbered and the time it
1866 * gets fixed, the actual LAA is in one of the RARs and no
1867 * incoming packets directed to this port are dropped.
1868 * Eventually the LAA will be in RAR[0] and RAR[14].
1870 hw->mac.ops.rar_set(hw, hw->mac.addr,
1871 hw->mac.rar_entry_count - 1);
1876 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1877 * @hw: pointer to the HW structure
1879 * Verifies that the EEPROM has completed the update. After updating the
1880 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If
1881 * the checksum fix is not implemented, we need to set the bit and update
1882 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,
1883 * we need to return bad checksum.
1885 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1887 struct e1000_nvm_info *nvm = &hw->nvm;
1891 DEBUGFUNC("e1000_fix_nvm_checksum_82571");
1893 if (nvm->type != e1000_nvm_flash_hw)
1894 return E1000_SUCCESS;
1896 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
1897 * 10h-12h. Checksum may need to be fixed.
1899 ret_val = nvm->ops.read(hw, 0x10, 1, &data);
1903 if (!(data & 0x10)) {
1904 /* Read 0x23 and check bit 15. This bit is a 1
1905 * when the checksum has already been fixed. If
1906 * the checksum is still wrong and this bit is a
1907 * 1, we need to return bad checksum. Otherwise,
1908 * we need to set this bit to a 1 and update the
1911 ret_val = nvm->ops.read(hw, 0x23, 1, &data);
1915 if (!(data & 0x8000)) {
1917 ret_val = nvm->ops.write(hw, 0x23, 1, &data);
1920 ret_val = nvm->ops.update(hw);
1926 return E1000_SUCCESS;
1931 * e1000_read_mac_addr_82571 - Read device MAC address
1932 * @hw: pointer to the HW structure
1934 STATIC s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1936 DEBUGFUNC("e1000_read_mac_addr_82571");
1938 if (hw->mac.type == e1000_82571) {
1941 /* If there's an alternate MAC address place it in RAR0
1942 * so that it will override the Si installed default perm
1945 ret_val = e1000_check_alt_mac_addr_generic(hw);
1950 return e1000_read_mac_addr_generic(hw);
1954 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1955 * @hw: pointer to the HW structure
1957 * In the case of a PHY power down to save power, or to turn off link during a
1958 * driver unload, or wake on lan is not enabled, remove the link.
1960 STATIC void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1962 struct e1000_phy_info *phy = &hw->phy;
1963 struct e1000_mac_info *mac = &hw->mac;
1965 if (!phy->ops.check_reset_block)
1968 /* If the management interface is not enabled, then power down */
1969 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1970 e1000_power_down_phy_copper(hw);
1976 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1977 * @hw: pointer to the HW structure
1979 * Clears the hardware counters by reading the counter registers.
1981 STATIC void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1983 DEBUGFUNC("e1000_clear_hw_cntrs_82571");
1985 e1000_clear_hw_cntrs_base_generic(hw);
1987 E1000_READ_REG(hw, E1000_PRC64);
1988 E1000_READ_REG(hw, E1000_PRC127);
1989 E1000_READ_REG(hw, E1000_PRC255);
1990 E1000_READ_REG(hw, E1000_PRC511);
1991 E1000_READ_REG(hw, E1000_PRC1023);
1992 E1000_READ_REG(hw, E1000_PRC1522);
1993 E1000_READ_REG(hw, E1000_PTC64);
1994 E1000_READ_REG(hw, E1000_PTC127);
1995 E1000_READ_REG(hw, E1000_PTC255);
1996 E1000_READ_REG(hw, E1000_PTC511);
1997 E1000_READ_REG(hw, E1000_PTC1023);
1998 E1000_READ_REG(hw, E1000_PTC1522);
2000 E1000_READ_REG(hw, E1000_ALGNERRC);
2001 E1000_READ_REG(hw, E1000_RXERRC);
2002 E1000_READ_REG(hw, E1000_TNCRS);
2003 E1000_READ_REG(hw, E1000_CEXTERR);
2004 E1000_READ_REG(hw, E1000_TSCTC);
2005 E1000_READ_REG(hw, E1000_TSCTFC);
2007 E1000_READ_REG(hw, E1000_MGTPRC);
2008 E1000_READ_REG(hw, E1000_MGTPDC);
2009 E1000_READ_REG(hw, E1000_MGTPTC);
2011 E1000_READ_REG(hw, E1000_IAC);
2012 E1000_READ_REG(hw, E1000_ICRXOC);
2014 E1000_READ_REG(hw, E1000_ICRXPTC);
2015 E1000_READ_REG(hw, E1000_ICRXATC);
2016 E1000_READ_REG(hw, E1000_ICTXPTC);
2017 E1000_READ_REG(hw, E1000_ICTXATC);
2018 E1000_READ_REG(hw, E1000_ICTXQEC);
2019 E1000_READ_REG(hw, E1000_ICTXQMTC);
2020 E1000_READ_REG(hw, E1000_ICRXDMTC);