lib/librte_pmd_e1000/e1000/e1000_82571.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2012, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 /*
  35  * 82571EB Gigabit Ethernet Controller
  36  * 82571EB Gigabit Ethernet Controller (Copper)
  37  * 82571EB Gigabit Ethernet Controller (Fiber)
  38  * 82571EB Dual Port Gigabit Mezzanine Adapter
  39  * 82571EB Quad Port Gigabit Mezzanine Adapter
  40  * 82571PT Gigabit PT Quad Port Server ExpressModule
  41  * 82572EI Gigabit Ethernet Controller (Copper)
  42  * 82572EI Gigabit Ethernet Controller (Fiber)
  43  * 82572EI Gigabit Ethernet Controller
  44  * 82573V Gigabit Ethernet Controller (Copper)
  45  * 82573E Gigabit Ethernet Controller (Copper)
  46  * 82573L Gigabit Ethernet Controller
  47  * 82574L Gigabit Network Connection
  48  * 82583V Gigabit Network Connection
  49  */
  50
  51 #include "e1000_api.h"
  52
  53 STATIC s32  e1000_init_phy_params_82571(struct e1000_hw *hw);
  54 STATIC s32  e1000_init_nvm_params_82571(struct e1000_hw *hw);
  55 STATIC s32  e1000_init_mac_params_82571(struct e1000_hw *hw);
  56 STATIC s32  e1000_acquire_nvm_82571(struct e1000_hw *hw);
  57 STATIC void e1000_release_nvm_82571(struct e1000_hw *hw);
  58 STATIC s32  e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
  59                                   u16 words, u16 *data);
  60 STATIC s32  e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
  61 STATIC s32  e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
  62 STATIC s32  e1000_get_cfg_done_82571(struct e1000_hw *hw);
  63 STATIC s32  e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
  64                                           bool active);
  65 STATIC s32  e1000_reset_hw_82571(struct e1000_hw *hw);
  66 STATIC s32  e1000_init_hw_82571(struct e1000_hw *hw);
  67 STATIC void e1000_clear_vfta_82571(struct e1000_hw *hw);
  68 STATIC bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
  69 STATIC s32 e1000_led_on_82574(struct e1000_hw *hw);
  70 STATIC s32  e1000_setup_link_82571(struct e1000_hw *hw);
  71 STATIC s32  e1000_setup_copper_link_82571(struct e1000_hw *hw);
  72 STATIC s32  e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
  73 STATIC s32  e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
  74 STATIC s32  e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
  75 STATIC void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
  76 static s32  e1000_get_hw_semaphore_82571(struct e1000_hw *hw);
  77 static s32  e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
  78 static s32  e1000_get_phy_id_82571(struct e1000_hw *hw);
  79 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
  80 static s32  e1000_get_hw_semaphore_82573(struct e1000_hw *hw);
  81 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
  82 static s32  e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
  83 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
  84 STATIC s32  e1000_set_d0_lplu_state_82574(struct e1000_hw *hw,
  85                                           bool active);
  86 STATIC s32  e1000_set_d3_lplu_state_82574(struct e1000_hw *hw,
  87                                           bool active);
  88 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
  89 static s32  e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
  90                                        u16 words, u16 *data);
  91 STATIC s32  e1000_read_mac_addr_82571(struct e1000_hw *hw);
  92 STATIC void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
  93
  94 /**
  95  *  e1000_init_phy_params_82571 - Init PHY func ptrs.
  96  *  @hw: pointer to the HW structure
  97  **/
  98 STATIC s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
  99 {
 100         struct e1000_phy_info *phy = &hw->phy;
 101         s32 ret_val;
 102
 103         DEBUGFUNC("e1000_init_phy_params_82571");
 104
 105         if (hw->phy.media_type != e1000_media_type_copper) {
 106                 phy->type = e1000_phy_none;
 107                 return E1000_SUCCESS;
 108         }
 109
 110         phy->addr                       = 1;
 111         phy->autoneg_mask               = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 112         phy->reset_delay_us             = 100;
 113
 114         phy->ops.check_reset_block      = e1000_check_reset_block_generic;
 115         phy->ops.reset                  = e1000_phy_hw_reset_generic;
 116         phy->ops.set_d0_lplu_state      = e1000_set_d0_lplu_state_82571;
 117         phy->ops.set_d3_lplu_state      = e1000_set_d3_lplu_state_generic;
 118         phy->ops.power_up               = e1000_power_up_phy_copper;
 119         phy->ops.power_down             = e1000_power_down_phy_copper_82571;
 120
 121         switch (hw->mac.type) {
 122         case e1000_82571:
 123         case e1000_82572:
 124                 phy->type               = e1000_phy_igp_2;
 125                 phy->ops.get_cfg_done   = e1000_get_cfg_done_82571;
 126                 phy->ops.get_info       = e1000_get_phy_info_igp;
 127                 phy->ops.check_polarity = e1000_check_polarity_igp;
 128                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 129                 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 130                 phy->ops.read_reg       = e1000_read_phy_reg_igp;
 131                 phy->ops.write_reg      = e1000_write_phy_reg_igp;
 132                 phy->ops.acquire        = e1000_get_hw_semaphore_82571;
 133                 phy->ops.release        = e1000_put_hw_semaphore_82571;
 134                 break;
 135         case e1000_82573:
 136                 phy->type               = e1000_phy_m88;
 137                 phy->ops.get_cfg_done   = e1000_get_cfg_done_generic;
 138                 phy->ops.get_info       = e1000_get_phy_info_m88;
 139                 phy->ops.check_polarity = e1000_check_polarity_m88;
 140                 phy->ops.commit         = e1000_phy_sw_reset_generic;
 141                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 142                 phy->ops.get_cable_length = e1000_get_cable_length_m88;
 143                 phy->ops.read_reg       = e1000_read_phy_reg_m88;
 144                 phy->ops.write_reg      = e1000_write_phy_reg_m88;
 145                 phy->ops.acquire        = e1000_get_hw_semaphore_82571;
 146                 phy->ops.release        = e1000_put_hw_semaphore_82571;
 147                 break;
 148         case e1000_82574:
 149         case e1000_82583:
 150                 E1000_MUTEX_INIT(&hw->dev_spec._82571.swflag_mutex);
 151
 152                 phy->type               = e1000_phy_bm;
 153                 phy->ops.get_cfg_done   = e1000_get_cfg_done_generic;
 154                 phy->ops.get_info       = e1000_get_phy_info_m88;
 155                 phy->ops.check_polarity = e1000_check_polarity_m88;
 156                 phy->ops.commit         = e1000_phy_sw_reset_generic;
 157                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 158                 phy->ops.get_cable_length = e1000_get_cable_length_m88;
 159                 phy->ops.read_reg       = e1000_read_phy_reg_bm2;
 160                 phy->ops.write_reg      = e1000_write_phy_reg_bm2;
 161                 phy->ops.acquire        = e1000_get_hw_semaphore_82574;
 162                 phy->ops.release        = e1000_put_hw_semaphore_82574;
 163                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
 164                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
 165                 break;
 166         default:
 167                 return -E1000_ERR_PHY;
 168                 break;
 169         }
 170
 171         /* This can only be done after all function pointers are setup. */
 172         ret_val = e1000_get_phy_id_82571(hw);
 173         if (ret_val) {
 174                 DEBUGOUT("Error getting PHY ID\n");
 175                 return ret_val;
 176         }
 177
 178         /* Verify phy id */
 179         switch (hw->mac.type) {
 180         case e1000_82571:
 181         case e1000_82572:
 182                 if (phy->id != IGP01E1000_I_PHY_ID)
 183                         ret_val = -E1000_ERR_PHY;
 184                 break;
 185         case e1000_82573:
 186                 if (phy->id != M88E1111_I_PHY_ID)
 187                         ret_val = -E1000_ERR_PHY;
 188                 break;
 189         case e1000_82574:
 190         case e1000_82583:
 191                 if (phy->id != BME1000_E_PHY_ID_R2)
 192                         ret_val = -E1000_ERR_PHY;
 193                 break;
 194         default:
 195                 ret_val = -E1000_ERR_PHY;
 196                 break;
 197         }
 198
 199         if (ret_val)
 200                 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
 201
 202         return ret_val;
 203 }
 204
 205 /**
 206  *  e1000_init_nvm_params_82571 - Init NVM func ptrs.
 207  *  @hw: pointer to the HW structure
 208  **/
 209 STATIC s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
 210 {
 211         struct e1000_nvm_info *nvm = &hw->nvm;
 212         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 213         u16 size;
 214
 215         DEBUGFUNC("e1000_init_nvm_params_82571");
 216
 217         nvm->opcode_bits = 8;
 218         nvm->delay_usec = 1;
 219         switch (nvm->override) {
 220         case e1000_nvm_override_spi_large:
 221                 nvm->page_size = 32;
 222                 nvm->address_bits = 16;
 223                 break;
 224         case e1000_nvm_override_spi_small:
 225                 nvm->page_size = 8;
 226                 nvm->address_bits = 8;
 227                 break;
 228         default:
 229                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 230                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 231                 break;
 232         }
 233
 234         switch (hw->mac.type) {
 235         case e1000_82573:
 236         case e1000_82574:
 237         case e1000_82583:
 238                 if (((eecd >> 15) & 0x3) == 0x3) {
 239                         nvm->type = e1000_nvm_flash_hw;
 240                         nvm->word_size = 2048;
 241                         /*
 242                          * Autonomous Flash update bit must be cleared due
 243                          * to Flash update issue.
 244                          */
 245                         eecd &= ~E1000_EECD_AUPDEN;
 246                         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 247                         break;
 248                 }
 249                 /* Fall Through */
 250         default:
 251                 nvm->type = e1000_nvm_eeprom_spi;
 252                 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 253                              E1000_EECD_SIZE_EX_SHIFT);
 254                 /*
 255                  * Added to a constant, "size" becomes the left-shift value
 256                  * for setting word_size.
 257                  */
 258                 size += NVM_WORD_SIZE_BASE_SHIFT;
 259
 260                 /* EEPROM access above 16k is unsupported */
 261                 if (size > 14)
 262                         size = 14;
 263                 nvm->word_size = 1 << size;
 264                 break;
 265         }
 266
 267         /* Function Pointers */
 268         switch (hw->mac.type) {
 269         case e1000_82574:
 270         case e1000_82583:
 271                 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
 272                 nvm->ops.release = e1000_put_hw_semaphore_82574;
 273                 break;
 274         default:
 275                 nvm->ops.acquire = e1000_acquire_nvm_82571;
 276                 nvm->ops.release = e1000_release_nvm_82571;
 277                 break;
 278         }
 279         nvm->ops.read = e1000_read_nvm_eerd;
 280         nvm->ops.update = e1000_update_nvm_checksum_82571;
 281         nvm->ops.validate = e1000_validate_nvm_checksum_82571;
 282         nvm->ops.valid_led_default = e1000_valid_led_default_82571;
 283         nvm->ops.write = e1000_write_nvm_82571;
 284
 285         return E1000_SUCCESS;
 286 }
 287
 288 /**
 289  *  e1000_init_mac_params_82571 - Init MAC func ptrs.
 290  *  @hw: pointer to the HW structure
 291  **/
 292 STATIC s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
 293 {
 294         struct e1000_mac_info *mac = &hw->mac;
 295         u32 swsm = 0;
 296         u32 swsm2 = 0;
 297         bool force_clear_smbi = false;
 298
 299         DEBUGFUNC("e1000_init_mac_params_82571");
 300
 301         /* Set media type and media-dependent function pointers */
 302         switch (hw->device_id) {
 303         case E1000_DEV_ID_82571EB_FIBER:
 304         case E1000_DEV_ID_82572EI_FIBER:
 305         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 306                 hw->phy.media_type = e1000_media_type_fiber;
 307                 mac->ops.setup_physical_interface =
 308                         e1000_setup_fiber_serdes_link_82571;
 309                 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
 310                 mac->ops.get_link_up_info =
 311                         e1000_get_speed_and_duplex_fiber_serdes_generic;
 312                 break;
 313         case E1000_DEV_ID_82571EB_SERDES:
 314         case E1000_DEV_ID_82571EB_SERDES_DUAL:
 315         case E1000_DEV_ID_82571EB_SERDES_QUAD:
 316         case E1000_DEV_ID_82572EI_SERDES:
 317                 hw->phy.media_type = e1000_media_type_internal_serdes;
 318                 mac->ops.setup_physical_interface =
 319                         e1000_setup_fiber_serdes_link_82571;
 320                 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
 321                 mac->ops.get_link_up_info =
 322                         e1000_get_speed_and_duplex_fiber_serdes_generic;
 323                 break;
 324         default:
 325                 hw->phy.media_type = e1000_media_type_copper;
 326                 mac->ops.setup_physical_interface =
 327                         e1000_setup_copper_link_82571;
 328                 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
 329                 mac->ops.get_link_up_info =
 330                         e1000_get_speed_and_duplex_copper_generic;
 331                 break;
 332         }
 333
 334         /* Set mta register count */
 335         mac->mta_reg_count = 128;
 336         /* Set rar entry count */
 337         mac->rar_entry_count = E1000_RAR_ENTRIES;
 338         /* Set if part includes ASF firmware */
 339         mac->asf_firmware_present = true;
 340         /* Adaptive IFS supported */
 341         mac->adaptive_ifs = true;
 342
 343         /* Function pointers */
 344
 345         /* bus type/speed/width */
 346         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 347         /* reset */
 348         mac->ops.reset_hw = e1000_reset_hw_82571;
 349         /* hw initialization */
 350         mac->ops.init_hw = e1000_init_hw_82571;
 351         /* link setup */
 352         mac->ops.setup_link = e1000_setup_link_82571;
 353         /* multicast address update */
 354         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 355         /* writing VFTA */
 356         mac->ops.write_vfta = e1000_write_vfta_generic;
 357         /* clearing VFTA */
 358         mac->ops.clear_vfta = e1000_clear_vfta_82571;
 359         /* read mac address */
 360         mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
 361         /* ID LED init */
 362         mac->ops.id_led_init = e1000_id_led_init_generic;
 363         /* setup LED */
 364         mac->ops.setup_led = e1000_setup_led_generic;
 365         /* cleanup LED */
 366         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 367         /* turn off LED */
 368         mac->ops.led_off = e1000_led_off_generic;
 369         /* clear hardware counters */
 370         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
 371
 372         /* MAC-specific function pointers */
 373         switch (hw->mac.type) {
 374         case e1000_82573:
 375                 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 376                 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 377                 mac->ops.led_on = e1000_led_on_generic;
 378                 mac->ops.blink_led = e1000_blink_led_generic;
 379
 380                 /* FWSM register */
 381                 mac->has_fwsm = true;
 382                 /*
 383                  * ARC supported; valid only if manageability features are
 384                  * enabled.
 385                  */
 386                 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) &
 387                                               E1000_FWSM_MODE_MASK);
 388                 break;
 389         case e1000_82574:
 390         case e1000_82583:
 391                 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 392                 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
 393                 mac->ops.led_on = e1000_led_on_82574;
 394                 break;
 395         default:
 396                 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 397                 mac->ops.led_on = e1000_led_on_generic;
 398                 mac->ops.blink_led = e1000_blink_led_generic;
 399
 400                 /* FWSM register */
 401                 mac->has_fwsm = true;
 402                 break;
 403         }
 404
 405         /*
 406          * Ensure that the inter-port SWSM.SMBI lock bit is clear before
 407          * first NVM or PHY acess. This should be done for single-port
 408          * devices, and for one port only on dual-port devices so that
 409          * for those devices we can still use the SMBI lock to synchronize
 410          * inter-port accesses to the PHY & NVM.
 411          */
 412         switch (hw->mac.type) {
 413         case e1000_82571:
 414         case e1000_82572:
 415                 swsm2 = E1000_READ_REG(hw, E1000_SWSM2);
 416
 417                 if (!(swsm2 & E1000_SWSM2_LOCK)) {
 418                         /* Only do this for the first interface on this card */
 419                         E1000_WRITE_REG(hw, E1000_SWSM2, swsm2 |
 420                                         E1000_SWSM2_LOCK);
 421                         force_clear_smbi = true;
 422                 } else {
 423                         force_clear_smbi = false;
 424                 }
 425                 break;
 426         default:
 427                 force_clear_smbi = true;
 428                 break;
 429         }
 430
 431         if (force_clear_smbi) {
 432                 /* Make sure SWSM.SMBI is clear */
 433                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 434                 if (swsm & E1000_SWSM_SMBI) {
 435                         /* This bit should not be set on a first interface, and
 436                          * indicates that the bootagent or EFI code has
 437                          * improperly left this bit enabled
 438                          */
 439                         DEBUGOUT("Please update your 82571 Bootagent\n");
 440                 }
 441                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI);
 442         }
 443
 444         /*
 445          * Initialze device specific counter of SMBI acquisition
 446          * timeouts.
 447          */
 448          hw->dev_spec._82571.smb_counter = 0;
 449
 450         return E1000_SUCCESS;
 451 }
 452
 453 /**
 454  *  e1000_init_function_pointers_82571 - Init func ptrs.
 455  *  @hw: pointer to the HW structure
 456  *
 457  *  Called to initialize all function pointers and parameters.
 458  **/
 459 void e1000_init_function_pointers_82571(struct e1000_hw *hw)
 460 {
 461         DEBUGFUNC("e1000_init_function_pointers_82571");
 462
 463         hw->mac.ops.init_params = e1000_init_mac_params_82571;
 464         hw->nvm.ops.init_params = e1000_init_nvm_params_82571;
 465         hw->phy.ops.init_params = e1000_init_phy_params_82571;
 466 }
 467
 468 /**
 469  *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
 470  *  @hw: pointer to the HW structure
 471  *
 472  *  Reads the PHY registers and stores the PHY ID and possibly the PHY
 473  *  revision in the hardware structure.
 474  **/
 475 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
 476 {
 477         struct e1000_phy_info *phy = &hw->phy;
 478         s32 ret_val;
 479         u16 phy_id = 0;
 480
 481         DEBUGFUNC("e1000_get_phy_id_82571");
 482
 483         switch (hw->mac.type) {
 484         case e1000_82571:
 485         case e1000_82572:
 486                 /*
 487                  * The 82571 firmware may still be configuring the PHY.
 488                  * In this case, we cannot access the PHY until the
 489                  * configuration is done.  So we explicitly set the
 490                  * PHY ID.
 491                  */
 492                 phy->id = IGP01E1000_I_PHY_ID;
 493                 break;
 494         case e1000_82573:
 495                 return e1000_get_phy_id(hw);
 496                 break;
 497         case e1000_82574:
 498         case e1000_82583:
 499                 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
 500                 if (ret_val)
 501                         return ret_val;
 502
 503                 phy->id = (u32)(phy_id << 16);
 504                 usec_delay(20);
 505                 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
 506                 if (ret_val)
 507                         return ret_val;
 508
 509                 phy->id |= (u32)(phy_id);
 510                 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
 511                 break;
 512         default:
 513                 return -E1000_ERR_PHY;
 514                 break;
 515         }
 516
 517         return E1000_SUCCESS;
 518 }
 519
 520 /**
 521  *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
 522  *  @hw: pointer to the HW structure
 523  *
 524  *  Acquire the HW semaphore to access the PHY or NVM
 525  **/
 526 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
 527 {
 528         u32 swsm;
 529         s32 sw_timeout = hw->nvm.word_size + 1;
 530         s32 fw_timeout = hw->nvm.word_size + 1;
 531         s32 i = 0;
 532
 533         DEBUGFUNC("e1000_get_hw_semaphore_82571");
 534
 535         /*
 536          * If we have timedout 3 times on trying to acquire
 537          * the inter-port SMBI semaphore, there is old code
 538          * operating on the other port, and it is not
 539          * releasing SMBI. Modify the number of times that
 540          * we try for the semaphore to interwork with this
 541          * older code.
 542          */
 543         if (hw->dev_spec._82571.smb_counter > 2)
 544                 sw_timeout = 1;
 545
 546         /* Get the SW semaphore */
 547         while (i < sw_timeout) {
 548                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 549                 if (!(swsm & E1000_SWSM_SMBI))
 550                         break;
 551
 552                 usec_delay(50);
 553                 i++;
 554         }
 555
 556         if (i == sw_timeout) {
 557                 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
 558                 hw->dev_spec._82571.smb_counter++;
 559         }
 560         /* Get the FW semaphore. */
 561         for (i = 0; i < fw_timeout; i++) {
 562                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 563                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
 564
 565                 /* Semaphore acquired if bit latched */
 566                 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
 567                         break;
 568
 569                 usec_delay(50);
 570         }
 571
 572         if (i == fw_timeout) {
 573                 /* Release semaphores */
 574                 e1000_put_hw_semaphore_82571(hw);
 575                 DEBUGOUT("Driver can't access the NVM\n");
 576                 return -E1000_ERR_NVM;
 577         }
 578
 579         return E1000_SUCCESS;
 580 }
 581
 582 /**
 583  *  e1000_put_hw_semaphore_82571 - Release hardware semaphore
 584  *  @hw: pointer to the HW structure
 585  *
 586  *  Release hardware semaphore used to access the PHY or NVM
 587  **/
 588 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
 589 {
 590         u32 swsm;
 591
 592         DEBUGFUNC("e1000_put_hw_semaphore_generic");
 593
 594         swsm = E1000_READ_REG(hw, E1000_SWSM);
 595
 596         swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
 597
 598         E1000_WRITE_REG(hw, E1000_SWSM, swsm);
 599 }
 600
 601 /**
 602  *  e1000_get_hw_semaphore_82573 - Acquire hardware semaphore
 603  *  @hw: pointer to the HW structure
 604  *
 605  *  Acquire the HW semaphore during reset.
 606  *
 607  **/
 608 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
 609 {
 610         u32 extcnf_ctrl;
 611         s32 i = 0;
 612
 613         DEBUGFUNC("e1000_get_hw_semaphore_82573");
 614
 615         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 616         extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 617         do {
 618                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
 619                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 620
 621                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
 622                         break;
 623
 624                 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 625
 626                 msec_delay(2);
 627                 i++;
 628         } while (i < MDIO_OWNERSHIP_TIMEOUT);
 629
 630         if (i == MDIO_OWNERSHIP_TIMEOUT) {
 631                 /* Release semaphores */
 632                 e1000_put_hw_semaphore_82573(hw);
 633                 DEBUGOUT("Driver can't access the PHY\n");
 634                 return -E1000_ERR_PHY;
 635         }
 636
 637         return E1000_SUCCESS;
 638 }
 639
 640 /**
 641  *  e1000_put_hw_semaphore_82573 - Release hardware semaphore
 642  *  @hw: pointer to the HW structure
 643  *
 644  *  Release hardware semaphore used during reset.
 645  *
 646  **/
 647 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
 648 {
 649         u32 extcnf_ctrl;
 650
 651         DEBUGFUNC("e1000_put_hw_semaphore_82573");
 652
 653         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 654         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 655         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
 656 }
 657
 658 /**
 659  *  e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
 660  *  @hw: pointer to the HW structure
 661  *
 662  *  Acquire the HW semaphore to access the PHY or NVM.
 663  *
 664  **/
 665 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
 666 {
 667         s32 ret_val;
 668
 669         DEBUGFUNC("e1000_get_hw_semaphore_82574");
 670
 671         E1000_MUTEX_LOCK(&hw->dev_spec._82571.swflag_mutex);
 672         ret_val = e1000_get_hw_semaphore_82573(hw);
 673         if (ret_val)
 674                 E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex);
 675         return ret_val;
 676 }
 677
 678 /**
 679  *  e1000_put_hw_semaphore_82574 - Release hardware semaphore
 680  *  @hw: pointer to the HW structure
 681  *
 682  *  Release hardware semaphore used to access the PHY or NVM
 683  *
 684  **/
 685 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
 686 {
 687         DEBUGFUNC("e1000_put_hw_semaphore_82574");
 688
 689         e1000_put_hw_semaphore_82573(hw);
 690         E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex);
 691 }
 692
 693 /**
 694  *  e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state
 695  *  @hw: pointer to the HW structure
 696  *  @active: true to enable LPLU, false to disable
 697  *
 698  *  Sets the LPLU D0 state according to the active flag.
 699  *  LPLU will not be activated unless the
 700  *  device autonegotiation advertisement meets standards of
 701  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 702  *  This is a function pointer entry point only called by
 703  *  PHY setup routines.
 704  **/
 705 STATIC s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
 706 {
 707         u32 data = E1000_READ_REG(hw, E1000_POEMB);
 708
 709         DEBUGFUNC("e1000_set_d0_lplu_state_82574");
 710
 711         if (active)
 712                 data |= E1000_PHY_CTRL_D0A_LPLU;
 713         else
 714                 data &= ~E1000_PHY_CTRL_D0A_LPLU;
 715
 716         E1000_WRITE_REG(hw, E1000_POEMB, data);
 717         return E1000_SUCCESS;
 718 }
 719
 720 /**
 721  *  e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3
 722  *  @hw: pointer to the HW structure
 723  *  @active: boolean used to enable/disable lplu
 724  *
 725  *  The low power link up (lplu) state is set to the power management level D3
 726  *  when active is true, else clear lplu for D3. LPLU
 727  *  is used during Dx states where the power conservation is most important.
 728  *  During driver activity, SmartSpeed should be enabled so performance is
 729  *  maintained.
 730  **/
 731 STATIC s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
 732 {
 733         u32 data = E1000_READ_REG(hw, E1000_POEMB);
 734
 735         DEBUGFUNC("e1000_set_d3_lplu_state_82574");
 736
 737         if (!active) {
 738                 data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
 739         } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 740                    (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
 741                    (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
 742                 data |= E1000_PHY_CTRL_NOND0A_LPLU;
 743         }
 744
 745         E1000_WRITE_REG(hw, E1000_POEMB, data);
 746         return E1000_SUCCESS;
 747 }
 748
 749 /**
 750  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
 751  *  @hw: pointer to the HW structure
 752  *
 753  *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
 754  *  Then for non-82573 hardware, set the EEPROM access request bit and wait
 755  *  for EEPROM access grant bit.  If the access grant bit is not set, release
 756  *  hardware semaphore.
 757  **/
 758 STATIC s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
 759 {
 760         s32 ret_val;
 761
 762         DEBUGFUNC("e1000_acquire_nvm_82571");
 763
 764         ret_val = e1000_get_hw_semaphore_82571(hw);
 765         if (ret_val)
 766                 return ret_val;
 767
 768         switch (hw->mac.type) {
 769         case e1000_82573:
 770                 break;
 771         default:
 772                 ret_val = e1000_acquire_nvm_generic(hw);
 773                 break;
 774         }
 775
 776         if (ret_val)
 777                 e1000_put_hw_semaphore_82571(hw);
 778
 779         return ret_val;
 780 }
 781
 782 /**
 783  *  e1000_release_nvm_82571 - Release exclusive access to EEPROM
 784  *  @hw: pointer to the HW structure
 785  *
 786  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 787  **/
 788 STATIC void e1000_release_nvm_82571(struct e1000_hw *hw)
 789 {
 790         DEBUGFUNC("e1000_release_nvm_82571");
 791
 792         e1000_release_nvm_generic(hw);
 793         e1000_put_hw_semaphore_82571(hw);
 794 }
 795
 796 /**
 797  *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
 798  *  @hw: pointer to the HW structure
 799  *  @offset: offset within the EEPROM to be written to
 800  *  @words: number of words to write
 801  *  @data: 16 bit word(s) to be written to the EEPROM
 802  *
 803  *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
 804  *
 805  *  If e1000_update_nvm_checksum is not called after this function, the
 806  *  EEPROM will most likely contain an invalid checksum.
 807  **/
 808 STATIC s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
 809                                  u16 *data)
 810 {
 811         s32 ret_val;
 812
 813         DEBUGFUNC("e1000_write_nvm_82571");
 814
 815         switch (hw->mac.type) {
 816         case e1000_82573:
 817         case e1000_82574:
 818         case e1000_82583:
 819                 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
 820                 break;
 821         case e1000_82571:
 822         case e1000_82572:
 823                 ret_val = e1000_write_nvm_spi(hw, offset, words, data);
 824                 break;
 825         default:
 826                 ret_val = -E1000_ERR_NVM;
 827                 break;
 828         }
 829
 830         return ret_val;
 831 }
 832
 833 /**
 834  *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum
 835  *  @hw: pointer to the HW structure
 836  *
 837  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 838  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 839  *  value to the EEPROM.
 840  **/
 841 STATIC s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
 842 {
 843         u32 eecd;
 844         s32 ret_val;
 845         u16 i;
 846
 847         DEBUGFUNC("e1000_update_nvm_checksum_82571");
 848
 849         ret_val = e1000_update_nvm_checksum_generic(hw);
 850         if (ret_val)
 851                 return ret_val;
 852
 853         /*
 854          * If our nvm is an EEPROM, then we're done
 855          * otherwise, commit the checksum to the flash NVM.
 856          */
 857         if (hw->nvm.type != e1000_nvm_flash_hw)
 858                 return E1000_SUCCESS;
 859
 860         /* Check for pending operations. */
 861         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 862                 msec_delay(1);
 863                 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
 864                         break;
 865         }
 866
 867         if (i == E1000_FLASH_UPDATES)
 868                 return -E1000_ERR_NVM;
 869
 870         /* Reset the firmware if using STM opcode. */
 871         if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) {
 872                 /*
 873                  * The enabling of and the actual reset must be done
 874                  * in two write cycles.
 875                  */
 876                 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE);
 877                 E1000_WRITE_FLUSH(hw);
 878                 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET);
 879         }
 880
 881         /* Commit the write to flash */
 882         eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD;
 883         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 884
 885         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 886                 msec_delay(1);
 887                 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
 888                         break;
 889         }
 890
 891         if (i == E1000_FLASH_UPDATES)
 892                 return -E1000_ERR_NVM;
 893
 894         return E1000_SUCCESS;
 895 }
 896
 897 /**
 898  *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
 899  *  @hw: pointer to the HW structure
 900  *
 901  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
 902  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
 903  **/
 904 STATIC s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
 905 {
 906         DEBUGFUNC("e1000_validate_nvm_checksum_82571");
 907
 908         if (hw->nvm.type == e1000_nvm_flash_hw)
 909                 e1000_fix_nvm_checksum_82571(hw);
 910
 911         return e1000_validate_nvm_checksum_generic(hw);
 912 }
 913
 914 /**
 915  *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
 916  *  @hw: pointer to the HW structure
 917  *  @offset: offset within the EEPROM to be written to
 918  *  @words: number of words to write
 919  *  @data: 16 bit word(s) to be written to the EEPROM
 920  *
 921  *  After checking for invalid values, poll the EEPROM to ensure the previous
 922  *  command has completed before trying to write the next word.  After write
 923  *  poll for completion.
 924  *
 925  *  If e1000_update_nvm_checksum is not called after this function, the
 926  *  EEPROM will most likely contain an invalid checksum.
 927  **/
 928 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
 929                                       u16 words, u16 *data)
 930 {
 931         struct e1000_nvm_info *nvm = &hw->nvm;
 932         u32 i, eewr = 0;
 933         s32 ret_val = E1000_SUCCESS;
 934
 935         DEBUGFUNC("e1000_write_nvm_eewr_82571");
 936
 937         /*
 938          * A check for invalid values:  offset too large, too many words,
 939          * and not enough words.
 940          */
 941         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 942             (words == 0)) {
 943                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 944                 return -E1000_ERR_NVM;
 945         }
 946
 947         for (i = 0; i < words; i++) {
 948                 eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
 949                        ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
 950                        E1000_NVM_RW_REG_START;
 951
 952                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 953                 if (ret_val)
 954                         break;
 955
 956                 E1000_WRITE_REG(hw, E1000_EEWR, eewr);
 957
 958                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 959                 if (ret_val)
 960                         break;
 961         }
 962
 963         return ret_val;
 964 }
 965
 966 /**
 967  *  e1000_get_cfg_done_82571 - Poll for configuration done
 968  *  @hw: pointer to the HW structure
 969  *
 970  *  Reads the management control register for the config done bit to be set.
 971  **/
 972 STATIC s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
 973 {
 974         s32 timeout = PHY_CFG_TIMEOUT;
 975
 976         DEBUGFUNC("e1000_get_cfg_done_82571");
 977
 978         while (timeout) {
 979                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) &
 980                     E1000_NVM_CFG_DONE_PORT_0)
 981                         break;
 982                 msec_delay(1);
 983                 timeout--;
 984         }
 985         if (!timeout) {
 986                 DEBUGOUT("MNG configuration cycle has not completed.\n");
 987                 return -E1000_ERR_RESET;
 988         }
 989
 990         return E1000_SUCCESS;
 991 }
 992
 993 /**
 994  *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
 995  *  @hw: pointer to the HW structure
 996  *  @active: true to enable LPLU, false to disable
 997  *
 998  *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
 999  *  this function also disables smart speed and vice versa.  LPLU will not be
1000  *  activated unless the device autonegotiation advertisement meets standards
1001  *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
1002  *  pointer entry point only called by PHY setup routines.
1003  **/
1004 STATIC s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
1005 {
1006         struct e1000_phy_info *phy = &hw->phy;
1007         s32 ret_val;
1008         u16 data;
1009
1010         DEBUGFUNC("e1000_set_d0_lplu_state_82571");
1011
1012         if (!(phy->ops.read_reg))
1013                 return E1000_SUCCESS;
1014
1015         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1016         if (ret_val)
1017                 return ret_val;
1018
1019         if (active) {
1020                 data |= IGP02E1000_PM_D0_LPLU;
1021                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1022                                              data);
1023                 if (ret_val)
1024                         return ret_val;
1025
1026                 /* When LPLU is enabled, we should disable SmartSpeed */
1027                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1028                                             &data);
1029                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1030                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1031                                              data);
1032                 if (ret_val)
1033                         return ret_val;
1034         } else {
1035                 data &= ~IGP02E1000_PM_D0_LPLU;
1036                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1037                                              data);
1038                 /*
1039                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1040                  * during Dx states where the power conservation is most
1041                  * important.  During driver activity we should enable
1042                  * SmartSpeed, so performance is maintained.
1043                  */
1044                 if (phy->smart_speed == e1000_smart_speed_on) {
1045                         ret_val = phy->ops.read_reg(hw,
1046                                                     IGP01E1000_PHY_PORT_CONFIG,
1047                                                     &data);
1048                         if (ret_val)
1049                                 return ret_val;
1050
1051                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1052                         ret_val = phy->ops.write_reg(hw,
1053                                                      IGP01E1000_PHY_PORT_CONFIG,
1054                                                      data);
1055                         if (ret_val)
1056                                 return ret_val;
1057                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1058                         ret_val = phy->ops.read_reg(hw,
1059                                                     IGP01E1000_PHY_PORT_CONFIG,
1060                                                     &data);
1061                         if (ret_val)
1062                                 return ret_val;
1063
1064                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1065                         ret_val = phy->ops.write_reg(hw,
1066                                                      IGP01E1000_PHY_PORT_CONFIG,
1067                                                      data);
1068                         if (ret_val)
1069                                 return ret_val;
1070                 }
1071         }
1072
1073         return E1000_SUCCESS;
1074 }
1075
1076 /**
1077  *  e1000_reset_hw_82571 - Reset hardware
1078  *  @hw: pointer to the HW structure
1079  *
1080  *  This resets the hardware into a known state.
1081  **/
1082 STATIC s32 e1000_reset_hw_82571(struct e1000_hw *hw)
1083 {
1084         u32 ctrl, ctrl_ext, eecd, tctl;
1085         s32 ret_val;
1086
1087         DEBUGFUNC("e1000_reset_hw_82571");
1088
1089         /*
1090          * Prevent the PCI-E bus from sticking if there is no TLP connection
1091          * on the last TLP read/write transaction when MAC is reset.
1092          */
1093         ret_val = e1000_disable_pcie_master_generic(hw);
1094         if (ret_val)
1095                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1096
1097         DEBUGOUT("Masking off all interrupts\n");
1098         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1099
1100         E1000_WRITE_REG(hw, E1000_RCTL, 0);
1101         tctl = E1000_READ_REG(hw, E1000_TCTL);
1102         tctl &= ~E1000_TCTL_EN;
1103         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1104         E1000_WRITE_FLUSH(hw);
1105
1106         msec_delay(10);
1107
1108         /*
1109          * Must acquire the MDIO ownership before MAC reset.
1110          * Ownership defaults to firmware after a reset.
1111          */
1112         switch (hw->mac.type) {
1113         case e1000_82573:
1114                 ret_val = e1000_get_hw_semaphore_82573(hw);
1115                 break;
1116         case e1000_82574:
1117         case e1000_82583:
1118                 ret_val = e1000_get_hw_semaphore_82574(hw);
1119                 break;
1120         default:
1121                 break;
1122         }
1123         if (ret_val)
1124                 DEBUGOUT("Cannot acquire MDIO ownership\n");
1125
1126         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1127
1128         DEBUGOUT("Issuing a global reset to MAC\n");
1129         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1130
1131         /* Must release MDIO ownership and mutex after MAC reset. */
1132         switch (hw->mac.type) {
1133         case e1000_82574:
1134         case e1000_82583:
1135                 e1000_put_hw_semaphore_82574(hw);
1136                 break;
1137         default:
1138                 break;
1139         }
1140
1141         if (hw->nvm.type == e1000_nvm_flash_hw) {
1142                 usec_delay(10);
1143                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1144                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1145                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1146                 E1000_WRITE_FLUSH(hw);
1147         }
1148
1149         ret_val = e1000_get_auto_rd_done_generic(hw);
1150         if (ret_val)
1151                 /* We don't want to continue accessing MAC registers. */
1152                 return ret_val;
1153
1154         /*
1155          * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1156          * Need to wait for Phy configuration completion before accessing
1157          * NVM and Phy.
1158          */
1159
1160         switch (hw->mac.type) {
1161         case e1000_82571:
1162         case e1000_82572:
1163                 /*
1164                  * REQ and GNT bits need to be cleared when using AUTO_RD
1165                  * to access the EEPROM.
1166                  */
1167                 eecd = E1000_READ_REG(hw, E1000_EECD);
1168                 eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);
1169                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
1170                 break;
1171         case e1000_82573:
1172         case e1000_82574:
1173         case e1000_82583:
1174                 msec_delay(25);
1175                 break;
1176         default:
1177                 break;
1178         }
1179
1180         /* Clear any pending interrupt events. */
1181         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1182         E1000_READ_REG(hw, E1000_ICR);
1183
1184         if (hw->mac.type == e1000_82571) {
1185                 /* Install any alternate MAC address into RAR0 */
1186                 ret_val = e1000_check_alt_mac_addr_generic(hw);
1187                 if (ret_val)
1188                         return ret_val;
1189
1190                 e1000_set_laa_state_82571(hw, true);
1191         }
1192
1193         /* Reinitialize the 82571 serdes link state machine */
1194         if (hw->phy.media_type == e1000_media_type_internal_serdes)
1195                 hw->mac.serdes_link_state = e1000_serdes_link_down;
1196
1197         return E1000_SUCCESS;
1198 }
1199
1200 /**
1201  *  e1000_init_hw_82571 - Initialize hardware
1202  *  @hw: pointer to the HW structure
1203  *
1204  *  This inits the hardware readying it for operation.
1205  **/
1206 STATIC s32 e1000_init_hw_82571(struct e1000_hw *hw)
1207 {
1208         struct e1000_mac_info *mac = &hw->mac;
1209         u32 reg_data;
1210         s32 ret_val;
1211         u16 i, rar_count = mac->rar_entry_count;
1212
1213         DEBUGFUNC("e1000_init_hw_82571");
1214
1215         e1000_initialize_hw_bits_82571(hw);
1216
1217         /* Initialize identification LED */
1218         ret_val = mac->ops.id_led_init(hw);
1219         if (ret_val)
1220                 DEBUGOUT("Error initializing identification LED\n");
1221                 /* This is not fatal and we should not stop init due to this */
1222
1223         /* Disabling VLAN filtering */
1224         DEBUGOUT("Initializing the IEEE VLAN\n");
1225         mac->ops.clear_vfta(hw);
1226
1227         /* Setup the receive address. */
1228         /*
1229          * If, however, a locally administered address was assigned to the
1230          * 82571, we must reserve a RAR for it to work around an issue where
1231          * resetting one port will reload the MAC on the other port.
1232          */
1233         if (e1000_get_laa_state_82571(hw))
1234                 rar_count--;
1235         e1000_init_rx_addrs_generic(hw, rar_count);
1236
1237         /* Zero out the Multicast HASH table */
1238         DEBUGOUT("Zeroing the MTA\n");
1239         for (i = 0; i < mac->mta_reg_count; i++)
1240                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1241
1242         /* Setup link and flow control */
1243         ret_val = mac->ops.setup_link(hw);
1244
1245         /* Set the transmit descriptor write-back policy */
1246         reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
1247         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1248                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
1249         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
1250
1251         /* ...for both queues. */
1252         switch (mac->type) {
1253         case e1000_82573:
1254                 e1000_enable_tx_pkt_filtering_generic(hw);
1255                 /* fall through */
1256         case e1000_82574:
1257         case e1000_82583:
1258                 reg_data = E1000_READ_REG(hw, E1000_GCR);
1259                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1260                 E1000_WRITE_REG(hw, E1000_GCR, reg_data);
1261                 break;
1262         default:
1263                 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
1264                 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1265                            E1000_TXDCTL_FULL_TX_DESC_WB |
1266                            E1000_TXDCTL_COUNT_DESC;
1267                 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
1268                 break;
1269         }
1270
1271         /*
1272          * Clear all of the statistics registers (clear on read).  It is
1273          * important that we do this after we have tried to establish link
1274          * because the symbol error count will increment wildly if there
1275          * is no link.
1276          */
1277         e1000_clear_hw_cntrs_82571(hw);
1278
1279         return ret_val;
1280 }
1281
1282 /**
1283  *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1284  *  @hw: pointer to the HW structure
1285  *
1286  *  Initializes required hardware-dependent bits needed for normal operation.
1287  **/
1288 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1289 {
1290         u32 reg;
1291
1292         DEBUGFUNC("e1000_initialize_hw_bits_82571");
1293
1294         /* Transmit Descriptor Control 0 */
1295         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1296         reg |= (1 << 22);
1297         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1298
1299         /* Transmit Descriptor Control 1 */
1300         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1301         reg |= (1 << 22);
1302         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1303
1304         /* Transmit Arbitration Control 0 */
1305         reg = E1000_READ_REG(hw, E1000_TARC(0));
1306         reg &= ~(0xF << 27); /* 30:27 */
1307         switch (hw->mac.type) {
1308         case e1000_82571:
1309         case e1000_82572:
1310                 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1311                 break;
1312         case e1000_82574:
1313         case e1000_82583:
1314                 reg |= (1 << 26);
1315                 break;
1316         default:
1317                 break;
1318         }
1319         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1320
1321         /* Transmit Arbitration Control 1 */
1322         reg = E1000_READ_REG(hw, E1000_TARC(1));
1323         switch (hw->mac.type) {
1324         case e1000_82571:
1325         case e1000_82572:
1326                 reg &= ~((1 << 29) | (1 << 30));
1327                 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1328                 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1329                         reg &= ~(1 << 28);
1330                 else
1331                         reg |= (1 << 28);
1332                 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1333                 break;
1334         default:
1335                 break;
1336         }
1337
1338         /* Device Control */
1339         switch (hw->mac.type) {
1340         case e1000_82573:
1341         case e1000_82574:
1342         case e1000_82583:
1343                 reg = E1000_READ_REG(hw, E1000_CTRL);
1344                 reg &= ~(1 << 29);
1345                 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1346                 break;
1347         default:
1348                 break;
1349         }
1350
1351         /* Extended Device Control */
1352         switch (hw->mac.type) {
1353         case e1000_82573:
1354         case e1000_82574:
1355         case e1000_82583:
1356                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1357                 reg &= ~(1 << 23);
1358                 reg |= (1 << 22);
1359                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1360                 break;
1361         default:
1362                 break;
1363         }
1364
1365         if (hw->mac.type == e1000_82571) {
1366                 reg = E1000_READ_REG(hw, E1000_PBA_ECC);
1367                 reg |= E1000_PBA_ECC_CORR_EN;
1368                 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg);
1369         }
1370
1371         /*
1372          * Workaround for hardware errata.
1373          * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1374          */
1375         if ((hw->mac.type == e1000_82571) ||
1376            (hw->mac.type == e1000_82572)) {
1377                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1378                 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1379                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1380         }
1381
1382         /*
1383          * Disable IPv6 extension header parsing because some malformed
1384          * IPv6 headers can hang the Rx.
1385          */
1386         if (hw->mac.type <= e1000_82573) {
1387                 reg = E1000_READ_REG(hw, E1000_RFCTL);
1388                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1389                 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
1390         }
1391
1392         /* PCI-Ex Control Registers */
1393         switch (hw->mac.type) {
1394         case e1000_82574:
1395         case e1000_82583:
1396                 reg = E1000_READ_REG(hw, E1000_GCR);
1397                 reg |= (1 << 22);
1398                 E1000_WRITE_REG(hw, E1000_GCR, reg);
1399
1400                 /*
1401                  * Workaround for hardware errata.
1402                  * apply workaround for hardware errata documented in errata
1403                  * docs Fixes issue where some error prone or unreliable PCIe
1404                  * completions are occurring, particularly with ASPM enabled.
1405                  * Without fix, issue can cause Tx timeouts.
1406                  */
1407                 reg = E1000_READ_REG(hw, E1000_GCR2);
1408                 reg |= 1;
1409                 E1000_WRITE_REG(hw, E1000_GCR2, reg);
1410                 break;
1411         default:
1412                 break;
1413         }
1414
1415         return;
1416 }
1417
1418 /**
1419  *  e1000_clear_vfta_82571 - Clear VLAN filter table
1420  *  @hw: pointer to the HW structure
1421  *
1422  *  Clears the register array which contains the VLAN filter table by
1423  *  setting all the values to 0.
1424  **/
1425 STATIC void e1000_clear_vfta_82571(struct e1000_hw *hw)
1426 {
1427         u32 offset;
1428         u32 vfta_value = 0;
1429         u32 vfta_offset = 0;
1430         u32 vfta_bit_in_reg = 0;
1431
1432         DEBUGFUNC("e1000_clear_vfta_82571");
1433
1434         switch (hw->mac.type) {
1435         case e1000_82573:
1436         case e1000_82574:
1437         case e1000_82583:
1438                 if (hw->mng_cookie.vlan_id != 0) {
1439                         /*
1440                          * The VFTA is a 4096b bit-field, each identifying
1441                          * a single VLAN ID.  The following operations
1442                          * determine which 32b entry (i.e. offset) into the
1443                          * array we want to set the VLAN ID (i.e. bit) of
1444                          * the manageability unit.
1445                          */
1446                         vfta_offset = (hw->mng_cookie.vlan_id >>
1447                                        E1000_VFTA_ENTRY_SHIFT) &
1448                             E1000_VFTA_ENTRY_MASK;
1449                         vfta_bit_in_reg =
1450                             1 << (hw->mng_cookie.vlan_id &
1451                                   E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1452                 }
1453                 break;
1454         default:
1455                 break;
1456         }
1457         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1458                 /*
1459                  * If the offset we want to clear is the same offset of the
1460                  * manageability VLAN ID, then clear all bits except that of
1461                  * the manageability unit.
1462                  */
1463                 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1464                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1465                 E1000_WRITE_FLUSH(hw);
1466         }
1467 }
1468
1469 /**
1470  *  e1000_check_mng_mode_82574 - Check manageability is enabled
1471  *  @hw: pointer to the HW structure
1472  *
1473  *  Reads the NVM Initialization Control Word 2 and returns true
1474  *  (>0) if any manageability is enabled, else false (0).
1475  **/
1476 STATIC bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1477 {
1478         u16 data;
1479
1480         DEBUGFUNC("e1000_check_mng_mode_82574");
1481
1482         hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1483         return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1484 }
1485
1486 /**
1487  *  e1000_led_on_82574 - Turn LED on
1488  *  @hw: pointer to the HW structure
1489  *
1490  *  Turn LED on.
1491  **/
1492 STATIC s32 e1000_led_on_82574(struct e1000_hw *hw)
1493 {
1494         u32 ctrl;
1495         u32 i;
1496
1497         DEBUGFUNC("e1000_led_on_82574");
1498
1499         ctrl = hw->mac.ledctl_mode2;
1500         if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) {
1501                 /*
1502                  * If no link, then turn LED on by setting the invert bit
1503                  * for each LED that's "on" (0x0E) in ledctl_mode2.
1504                  */
1505                 for (i = 0; i < 4; i++)
1506                         if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1507                             E1000_LEDCTL_MODE_LED_ON)
1508                                 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1509         }
1510         E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl);
1511
1512         return E1000_SUCCESS;
1513 }
1514
1515 /**
1516  *  e1000_check_phy_82574 - check 82574 phy hung state
1517  *  @hw: pointer to the HW structure
1518  *
1519  *  Returns whether phy is hung or not
1520  **/
1521 bool e1000_check_phy_82574(struct e1000_hw *hw)
1522 {
1523         u16 status_1kbt = 0;
1524         u16 receive_errors = 0;
1525         s32 ret_val = E1000_SUCCESS;
1526
1527         DEBUGFUNC("e1000_check_phy_82574");
1528
1529         /*
1530          * Read PHY Receive Error counter first, if its is max - all F's then
1531          * read the Base1000T status register If both are max then PHY is hung.
1532          */
1533         ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,
1534                                        &receive_errors);
1535         if (ret_val)
1536                 return false;
1537         if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1538                 ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,
1539                                                &status_1kbt);
1540                 if (ret_val)
1541                         return false;
1542                 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1543                     E1000_IDLE_ERROR_COUNT_MASK)
1544                         return true;
1545         }
1546
1547         return false;
1548 }
1549
1550
1551 /**
1552  *  e1000_setup_link_82571 - Setup flow control and link settings
1553  *  @hw: pointer to the HW structure
1554  *
1555  *  Determines which flow control settings to use, then configures flow
1556  *  control.  Calls the appropriate media-specific link configuration
1557  *  function.  Assuming the adapter has a valid link partner, a valid link
1558  *  should be established.  Assumes the hardware has previously been reset
1559  *  and the transmitter and receiver are not enabled.
1560  **/
1561 STATIC s32 e1000_setup_link_82571(struct e1000_hw *hw)
1562 {
1563         DEBUGFUNC("e1000_setup_link_82571");
1564
1565         /*
1566          * 82573 does not have a word in the NVM to determine
1567          * the default flow control setting, so we explicitly
1568          * set it to full.
1569          */
1570         switch (hw->mac.type) {
1571         case e1000_82573:
1572         case e1000_82574:
1573         case e1000_82583:
1574                 if (hw->fc.requested_mode == e1000_fc_default)
1575                         hw->fc.requested_mode = e1000_fc_full;
1576                 break;
1577         default:
1578                 break;
1579         }
1580
1581         return e1000_setup_link_generic(hw);
1582 }
1583
1584 /**
1585  *  e1000_setup_copper_link_82571 - Configure copper link settings
1586  *  @hw: pointer to the HW structure
1587  *
1588  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1589  *  for link, once link is established calls to configure collision distance
1590  *  and flow control are called.
1591  **/
1592 STATIC s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1593 {
1594         u32 ctrl;
1595         s32 ret_val;
1596
1597         DEBUGFUNC("e1000_setup_copper_link_82571");
1598
1599         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1600         ctrl |= E1000_CTRL_SLU;
1601         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1602         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1603
1604         switch (hw->phy.type) {
1605         case e1000_phy_m88:
1606         case e1000_phy_bm:
1607                 ret_val = e1000_copper_link_setup_m88(hw);
1608                 break;
1609         case e1000_phy_igp_2:
1610                 ret_val = e1000_copper_link_setup_igp(hw);
1611                 break;
1612         default:
1613                 return -E1000_ERR_PHY;
1614                 break;
1615         }
1616
1617         if (ret_val)
1618                 return ret_val;
1619
1620         return e1000_setup_copper_link_generic(hw);
1621 }
1622
1623 /**
1624  *  e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1625  *  @hw: pointer to the HW structure
1626  *
1627  *  Configures collision distance and flow control for fiber and serdes links.
1628  *  Upon successful setup, poll for link.
1629  **/
1630 STATIC s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1631 {
1632         DEBUGFUNC("e1000_setup_fiber_serdes_link_82571");
1633
1634         switch (hw->mac.type) {
1635         case e1000_82571:
1636         case e1000_82572:
1637                 /*
1638                  * If SerDes loopback mode is entered, there is no form
1639                  * of reset to take the adapter out of that mode.  So we
1640                  * have to explicitly take the adapter out of loopback
1641                  * mode.  This prevents drivers from twiddling their thumbs
1642                  * if another tool failed to take it out of loopback mode.
1643                  */
1644                 E1000_WRITE_REG(hw, E1000_SCTL,
1645                                 E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1646                 break;
1647         default:
1648                 break;
1649         }
1650
1651         return e1000_setup_fiber_serdes_link_generic(hw);
1652 }
1653
1654 /**
1655  *  e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1656  *  @hw: pointer to the HW structure
1657  *
1658  *  Reports the link state as up or down.
1659  *
1660  *  If autonegotiation is supported by the link partner, the link state is
1661  *  determined by the result of autonegotiation. This is the most likely case.
1662  *  If autonegotiation is not supported by the link partner, and the link
1663  *  has a valid signal, force the link up.
1664  *
1665  *  The link state is represented internally here by 4 states:
1666  *
1667  *  1) down
1668  *  2) autoneg_progress
1669  *  3) autoneg_complete (the link successfully autonegotiated)
1670  *  4) forced_up (the link has been forced up, it did not autonegotiate)
1671  *
1672  **/
1673 STATIC s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1674 {
1675         struct e1000_mac_info *mac = &hw->mac;
1676         u32 rxcw;
1677         u32 ctrl;
1678         u32 status;
1679         u32 txcw;
1680         u32 i;
1681         s32 ret_val = E1000_SUCCESS;
1682
1683         DEBUGFUNC("e1000_check_for_serdes_link_82571");
1684
1685         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1686         status = E1000_READ_REG(hw, E1000_STATUS);
1687         rxcw = E1000_READ_REG(hw, E1000_RXCW);
1688         /* SYNCH bit and IV bit are sticky */
1689         usec_delay(10);
1690         rxcw = E1000_READ_REG(hw, E1000_RXCW);
1691
1692         if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1693
1694                 /* Receiver is synchronized with no invalid bits.  */
1695                 switch (mac->serdes_link_state) {
1696                 case e1000_serdes_link_autoneg_complete:
1697                         if (!(status & E1000_STATUS_LU)) {
1698                                 /*
1699                                  * We have lost link, retry autoneg before
1700                                  * reporting link failure
1701                                  */
1702                                 mac->serdes_link_state =
1703                                     e1000_serdes_link_autoneg_progress;
1704                                 mac->serdes_has_link = false;
1705                                 DEBUGOUT("AN_UP     -> AN_PROG\n");
1706                         } else {
1707                                 mac->serdes_has_link = true;
1708                         }
1709                         break;
1710
1711                 case e1000_serdes_link_forced_up:
1712                         /*
1713                          * If we are receiving /C/ ordered sets, re-enable
1714                          * auto-negotiation in the TXCW register and disable
1715                          * forced link in the Device Control register in an
1716                          * attempt to auto-negotiate with our link partner.
1717                          */
1718                         if (rxcw & E1000_RXCW_C) {
1719                                 /* Enable autoneg, and unforce link up */
1720                                 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1721                                 E1000_WRITE_REG(hw, E1000_CTRL,
1722                                     (ctrl & ~E1000_CTRL_SLU));
1723                                 mac->serdes_link_state =
1724                                     e1000_serdes_link_autoneg_progress;
1725                                 mac->serdes_has_link = false;
1726                                 DEBUGOUT("FORCED_UP -> AN_PROG\n");
1727                         } else {
1728                                 mac->serdes_has_link = true;
1729                         }
1730                         break;
1731
1732                 case e1000_serdes_link_autoneg_progress:
1733                         if (rxcw & E1000_RXCW_C) {
1734                                 /*
1735                                  * We received /C/ ordered sets, meaning the
1736                                  * link partner has autonegotiated, and we can
1737                                  * trust the Link Up (LU) status bit.
1738                                  */
1739                                 if (status & E1000_STATUS_LU) {
1740                                         mac->serdes_link_state =
1741                                             e1000_serdes_link_autoneg_complete;
1742                                         DEBUGOUT("AN_PROG   -> AN_UP\n");
1743                                         mac->serdes_has_link = true;
1744                                 } else {
1745                                         /* Autoneg completed, but failed. */
1746                                         mac->serdes_link_state =
1747                                             e1000_serdes_link_down;
1748                                         DEBUGOUT("AN_PROG   -> DOWN\n");
1749                                 }
1750                         } else {
1751                                 /*
1752                                  * The link partner did not autoneg.
1753                                  * Force link up and full duplex, and change
1754                                  * state to forced.
1755                                  */
1756                                 E1000_WRITE_REG(hw, E1000_TXCW,
1757                                 (mac->txcw & ~E1000_TXCW_ANE));
1758                                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1759                                 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1760
1761                                 /* Configure Flow Control after link up. */
1762                                 ret_val =
1763                                     e1000_config_fc_after_link_up_generic(hw);
1764                                 if (ret_val) {
1765                                         DEBUGOUT("Error config flow control\n");
1766                                         break;
1767                                 }
1768                                 mac->serdes_link_state =
1769                                                 e1000_serdes_link_forced_up;
1770                                 mac->serdes_has_link = true;
1771                                 DEBUGOUT("AN_PROG   -> FORCED_UP\n");
1772                         }
1773                         break;
1774
1775                 case e1000_serdes_link_down:
1776                 default:
1777                         /*
1778                          * The link was down but the receiver has now gained
1779                          * valid sync, so lets see if we can bring the link
1780                          * up.
1781                          */
1782                         E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1783                         E1000_WRITE_REG(hw, E1000_CTRL, (ctrl &
1784                                         ~E1000_CTRL_SLU));
1785                         mac->serdes_link_state =
1786                                         e1000_serdes_link_autoneg_progress;
1787                         mac->serdes_has_link = false;
1788                         DEBUGOUT("DOWN      -> AN_PROG\n");
1789                         break;
1790                 }
1791         } else {
1792                 if (!(rxcw & E1000_RXCW_SYNCH)) {
1793                         mac->serdes_has_link = false;
1794                         mac->serdes_link_state = e1000_serdes_link_down;
1795                         DEBUGOUT("ANYSTATE  -> DOWN\n");
1796                 } else {
1797                         /*
1798                          * Check several times, if SYNCH bit and CONFIG
1799                          * bit both are consistently 1 then simply ignore
1800                          * the IV bit and restart Autoneg
1801                          */
1802                         for (i = 0; i < AN_RETRY_COUNT; i++) {
1803                                 usec_delay(10);
1804                                 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1805                                 if ((rxcw & E1000_RXCW_SYNCH) &&
1806                                     (rxcw & E1000_RXCW_C))
1807                                         continue;
1808
1809                                 if (rxcw & E1000_RXCW_IV) {
1810                                         mac->serdes_has_link = false;
1811                                         mac->serdes_link_state =
1812                                                         e1000_serdes_link_down;
1813                                         DEBUGOUT("ANYSTATE  -> DOWN\n");
1814                                         break;
1815                                 }
1816                         }
1817
1818                         if (i == AN_RETRY_COUNT) {
1819                                 txcw = E1000_READ_REG(hw, E1000_TXCW);
1820                                 txcw |= E1000_TXCW_ANE;
1821                                 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1822                                 mac->serdes_link_state =
1823                                         e1000_serdes_link_autoneg_progress;
1824                                 mac->serdes_has_link = false;
1825                                 DEBUGOUT("ANYSTATE  -> AN_PROG\n");
1826                         }
1827                 }
1828         }
1829
1830         return ret_val;
1831 }
1832
1833 /**
1834  *  e1000_valid_led_default_82571 - Verify a valid default LED config
1835  *  @hw: pointer to the HW structure
1836  *  @data: pointer to the NVM (EEPROM)
1837  *
1838  *  Read the EEPROM for the current default LED configuration.  If the
1839  *  LED configuration is not valid, set to a valid LED configuration.
1840  **/
1841 STATIC s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1842 {
1843         s32 ret_val;
1844
1845         DEBUGFUNC("e1000_valid_led_default_82571");
1846
1847         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1848         if (ret_val) {
1849                 DEBUGOUT("NVM Read Error\n");
1850                 return ret_val;
1851         }
1852
1853         switch (hw->mac.type) {
1854         case e1000_82573:
1855         case e1000_82574:
1856         case e1000_82583:
1857                 if (*data == ID_LED_RESERVED_F746)
1858                         *data = ID_LED_DEFAULT_82573;
1859                 break;
1860         default:
1861                 if (*data == ID_LED_RESERVED_0000 ||
1862                     *data == ID_LED_RESERVED_FFFF)
1863                         *data = ID_LED_DEFAULT;
1864                 break;
1865         }
1866
1867         return E1000_SUCCESS;
1868 }
1869
1870 /**
1871  *  e1000_get_laa_state_82571 - Get locally administered address state
1872  *  @hw: pointer to the HW structure
1873  *
1874  *  Retrieve and return the current locally administered address state.
1875  **/
1876 bool e1000_get_laa_state_82571(struct e1000_hw *hw)
1877 {
1878         DEBUGFUNC("e1000_get_laa_state_82571");
1879
1880         if (hw->mac.type != e1000_82571)
1881                 return false;
1882
1883         return hw->dev_spec._82571.laa_is_present;
1884 }
1885
1886 /**
1887  *  e1000_set_laa_state_82571 - Set locally administered address state
1888  *  @hw: pointer to the HW structure
1889  *  @state: enable/disable locally administered address
1890  *
1891  *  Enable/Disable the current locally administered address state.
1892  **/
1893 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state)
1894 {
1895         DEBUGFUNC("e1000_set_laa_state_82571");
1896
1897         if (hw->mac.type != e1000_82571)
1898                 return;
1899
1900         hw->dev_spec._82571.laa_is_present = state;
1901
1902         /* If workaround is activated... */
1903         if (state)
1904                 /*
1905                  * Hold a copy of the LAA in RAR[14] This is done so that
1906                  * between the time RAR[0] gets clobbered and the time it
1907                  * gets fixed, the actual LAA is in one of the RARs and no
1908                  * incoming packets directed to this port are dropped.
1909                  * Eventually the LAA will be in RAR[0] and RAR[14].
1910                  */
1911                 hw->mac.ops.rar_set(hw, hw->mac.addr,
1912                                     hw->mac.rar_entry_count - 1);
1913         return;
1914 }
1915
1916 /**
1917  *  e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1918  *  @hw: pointer to the HW structure
1919  *
1920  *  Verifies that the EEPROM has completed the update.  After updating the
1921  *  EEPROM, we need to check bit 15 in work 0x23 for the checksum fix.  If
1922  *  the checksum fix is not implemented, we need to set the bit and update
1923  *  the checksum.  Otherwise, if bit 15 is set and the checksum is incorrect,
1924  *  we need to return bad checksum.
1925  **/
1926 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1927 {
1928         struct e1000_nvm_info *nvm = &hw->nvm;
1929         s32 ret_val;
1930         u16 data;
1931
1932         DEBUGFUNC("e1000_fix_nvm_checksum_82571");
1933
1934         if (nvm->type != e1000_nvm_flash_hw)
1935                 return E1000_SUCCESS;
1936
1937         /*
1938          * Check bit 4 of word 10h.  If it is 0, firmware is done updating
1939          * 10h-12h.  Checksum may need to be fixed.
1940          */
1941         ret_val = nvm->ops.read(hw, 0x10, 1, &data);
1942         if (ret_val)
1943                 return ret_val;
1944
1945         if (!(data & 0x10)) {
1946                 /*
1947                  * Read 0x23 and check bit 15.  This bit is a 1
1948                  * when the checksum has already been fixed.  If
1949                  * the checksum is still wrong and this bit is a
1950                  * 1, we need to return bad checksum.  Otherwise,
1951                  * we need to set this bit to a 1 and update the
1952                  * checksum.
1953                  */
1954                 ret_val = nvm->ops.read(hw, 0x23, 1, &data);
1955                 if (ret_val)
1956                         return ret_val;
1957
1958                 if (!(data & 0x8000)) {
1959                         data |= 0x8000;
1960                         ret_val = nvm->ops.write(hw, 0x23, 1, &data);
1961                         if (ret_val)
1962                                 return ret_val;
1963                         ret_val = nvm->ops.update(hw);
1964                 }
1965         }
1966
1967         return E1000_SUCCESS;
1968 }
1969
1970
1971 /**
1972  *  e1000_read_mac_addr_82571 - Read device MAC address
1973  *  @hw: pointer to the HW structure
1974  **/
1975 STATIC s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1976 {
1977         DEBUGFUNC("e1000_read_mac_addr_82571");
1978
1979         if (hw->mac.type == e1000_82571) {
1980                 s32 ret_val = E1000_SUCCESS;
1981
1982                 /*
1983                  * If there's an alternate MAC address place it in RAR0
1984                  * so that it will override the Si installed default perm
1985                  * address.
1986                  */
1987                 ret_val = e1000_check_alt_mac_addr_generic(hw);
1988                 if (ret_val)
1989                         return ret_val;
1990         }
1991
1992         return e1000_read_mac_addr_generic(hw);
1993 }
1994
1995 /**
1996  * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1997  * @hw: pointer to the HW structure
1998  *
1999  * In the case of a PHY power down to save power, or to turn off link during a
2000  * driver unload, or wake on lan is not enabled, remove the link.
2001  **/
2002 STATIC void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
2003 {
2004         struct e1000_phy_info *phy = &hw->phy;
2005         struct e1000_mac_info *mac = &hw->mac;
2006
2007         if (!phy->ops.check_reset_block)
2008                 return;
2009
2010         /* If the management interface is not enabled, then power down */
2011         if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
2012                 e1000_power_down_phy_copper(hw);
2013
2014         return;
2015 }
2016
2017 /**
2018  *  e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
2019  *  @hw: pointer to the HW structure
2020  *
2021  *  Clears the hardware counters by reading the counter registers.
2022  **/
2023 STATIC void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
2024 {
2025         DEBUGFUNC("e1000_clear_hw_cntrs_82571");
2026
2027         e1000_clear_hw_cntrs_base_generic(hw);
2028
2029         E1000_READ_REG(hw, E1000_PRC64);
2030         E1000_READ_REG(hw, E1000_PRC127);
2031         E1000_READ_REG(hw, E1000_PRC255);
2032         E1000_READ_REG(hw, E1000_PRC511);
2033         E1000_READ_REG(hw, E1000_PRC1023);
2034         E1000_READ_REG(hw, E1000_PRC1522);
2035         E1000_READ_REG(hw, E1000_PTC64);
2036         E1000_READ_REG(hw, E1000_PTC127);
2037         E1000_READ_REG(hw, E1000_PTC255);
2038         E1000_READ_REG(hw, E1000_PTC511);
2039         E1000_READ_REG(hw, E1000_PTC1023);
2040         E1000_READ_REG(hw, E1000_PTC1522);
2041
2042         E1000_READ_REG(hw, E1000_ALGNERRC);
2043         E1000_READ_REG(hw, E1000_RXERRC);
2044         E1000_READ_REG(hw, E1000_TNCRS);
2045         E1000_READ_REG(hw, E1000_CEXTERR);
2046         E1000_READ_REG(hw, E1000_TSCTC);
2047         E1000_READ_REG(hw, E1000_TSCTFC);
2048
2049         E1000_READ_REG(hw, E1000_MGTPRC);
2050         E1000_READ_REG(hw, E1000_MGTPDC);
2051         E1000_READ_REG(hw, E1000_MGTPTC);
2052
2053         E1000_READ_REG(hw, E1000_IAC);
2054         E1000_READ_REG(hw, E1000_ICRXOC);
2055
2056         E1000_READ_REG(hw, E1000_ICRXPTC);
2057         E1000_READ_REG(hw, E1000_ICRXATC);
2058         E1000_READ_REG(hw, E1000_ICTXPTC);
2059         E1000_READ_REG(hw, E1000_ICTXATC);
2060         E1000_READ_REG(hw, E1000_ICTXQEC);
2061         E1000_READ_REG(hw, E1000_ICTXQMTC);
2062         E1000_READ_REG(hw, E1000_ICRXDMTC);
2063 }