lib/librte_pmd_e1000/e1000/e1000_82571.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2012, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 /* 82571EB Gigabit Ethernet Controller
  35  * 82571EB Gigabit Ethernet Controller (Copper)
  36  * 82571EB Gigabit Ethernet Controller (Fiber)
  37  * 82571EB Dual Port Gigabit Mezzanine Adapter
  38  * 82571EB Quad Port Gigabit Mezzanine Adapter
  39  * 82571PT Gigabit PT Quad Port Server ExpressModule
  40  * 82572EI Gigabit Ethernet Controller (Copper)
  41  * 82572EI Gigabit Ethernet Controller (Fiber)
  42  * 82572EI Gigabit Ethernet Controller
  43  * 82573V Gigabit Ethernet Controller (Copper)
  44  * 82573E Gigabit Ethernet Controller (Copper)
  45  * 82573L Gigabit Ethernet Controller
  46  * 82574L Gigabit Network Connection
  47  * 82583V Gigabit Network Connection
  48  */
  49
  50 #include "e1000_api.h"
  51
  52 STATIC s32  e1000_acquire_nvm_82571(struct e1000_hw *hw);
  53 STATIC void e1000_release_nvm_82571(struct e1000_hw *hw);
  54 STATIC s32  e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
  55                                   u16 words, u16 *data);
  56 STATIC s32  e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
  57 STATIC s32  e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
  58 STATIC s32  e1000_get_cfg_done_82571(struct e1000_hw *hw);
  59 STATIC s32  e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
  60                                           bool active);
  61 STATIC s32  e1000_reset_hw_82571(struct e1000_hw *hw);
  62 STATIC s32  e1000_init_hw_82571(struct e1000_hw *hw);
  63 STATIC void e1000_clear_vfta_82571(struct e1000_hw *hw);
  64 STATIC bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
  65 STATIC s32 e1000_led_on_82574(struct e1000_hw *hw);
  66 STATIC s32  e1000_setup_link_82571(struct e1000_hw *hw);
  67 STATIC s32  e1000_setup_copper_link_82571(struct e1000_hw *hw);
  68 STATIC s32  e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
  69 STATIC s32  e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
  70 STATIC s32  e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
  71 STATIC void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
  72 static s32  e1000_get_hw_semaphore_82571(struct e1000_hw *hw);
  73 static s32  e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
  74 static s32  e1000_get_phy_id_82571(struct e1000_hw *hw);
  75 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
  76 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
  77 static s32  e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
  78 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
  79 STATIC s32  e1000_set_d0_lplu_state_82574(struct e1000_hw *hw,
  80                                           bool active);
  81 STATIC s32  e1000_set_d3_lplu_state_82574(struct e1000_hw *hw,
  82                                           bool active);
  83 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
  84 static s32  e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
  85                                        u16 words, u16 *data);
  86 STATIC s32  e1000_read_mac_addr_82571(struct e1000_hw *hw);
  87 STATIC void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
  88
  89 /**
  90  *  e1000_init_phy_params_82571 - Init PHY func ptrs.
  91  *  @hw: pointer to the HW structure
  92  **/
  93 STATIC s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
  94 {
  95         struct e1000_phy_info *phy = &hw->phy;
  96         s32 ret_val;
  97
  98         DEBUGFUNC("e1000_init_phy_params_82571");
  99
 100         if (hw->phy.media_type != e1000_media_type_copper) {
 101                 phy->type = e1000_phy_none;
 102                 return E1000_SUCCESS;
 103         }
 104
 105         phy->addr                       = 1;
 106         phy->autoneg_mask               = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 107         phy->reset_delay_us             = 100;
 108
 109         phy->ops.check_reset_block      = e1000_check_reset_block_generic;
 110         phy->ops.reset                  = e1000_phy_hw_reset_generic;
 111         phy->ops.set_d0_lplu_state      = e1000_set_d0_lplu_state_82571;
 112         phy->ops.set_d3_lplu_state      = e1000_set_d3_lplu_state_generic;
 113         phy->ops.power_up               = e1000_power_up_phy_copper;
 114         phy->ops.power_down             = e1000_power_down_phy_copper_82571;
 115
 116         switch (hw->mac.type) {
 117         case e1000_82571:
 118         case e1000_82572:
 119                 phy->type               = e1000_phy_igp_2;
 120                 phy->ops.get_cfg_done   = e1000_get_cfg_done_82571;
 121                 phy->ops.get_info       = e1000_get_phy_info_igp;
 122                 phy->ops.check_polarity = e1000_check_polarity_igp;
 123                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 124                 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 125                 phy->ops.read_reg       = e1000_read_phy_reg_igp;
 126                 phy->ops.write_reg      = e1000_write_phy_reg_igp;
 127                 phy->ops.acquire        = e1000_get_hw_semaphore_82571;
 128                 phy->ops.release        = e1000_put_hw_semaphore_82571;
 129                 break;
 130         case e1000_82573:
 131                 phy->type               = e1000_phy_m88;
 132                 phy->ops.get_cfg_done   = e1000_get_cfg_done_generic;
 133                 phy->ops.get_info       = e1000_get_phy_info_m88;
 134                 phy->ops.check_polarity = e1000_check_polarity_m88;
 135                 phy->ops.commit         = e1000_phy_sw_reset_generic;
 136                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 137                 phy->ops.get_cable_length = e1000_get_cable_length_m88;
 138                 phy->ops.read_reg       = e1000_read_phy_reg_m88;
 139                 phy->ops.write_reg      = e1000_write_phy_reg_m88;
 140                 phy->ops.acquire        = e1000_get_hw_semaphore_82571;
 141                 phy->ops.release        = e1000_put_hw_semaphore_82571;
 142                 break;
 143         case e1000_82574:
 144         case e1000_82583:
 145                 E1000_MUTEX_INIT(&hw->dev_spec._82571.swflag_mutex);
 146
 147                 phy->type               = e1000_phy_bm;
 148                 phy->ops.get_cfg_done   = e1000_get_cfg_done_generic;
 149                 phy->ops.get_info       = e1000_get_phy_info_m88;
 150                 phy->ops.check_polarity = e1000_check_polarity_m88;
 151                 phy->ops.commit         = e1000_phy_sw_reset_generic;
 152                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 153                 phy->ops.get_cable_length = e1000_get_cable_length_m88;
 154                 phy->ops.read_reg       = e1000_read_phy_reg_bm2;
 155                 phy->ops.write_reg      = e1000_write_phy_reg_bm2;
 156                 phy->ops.acquire        = e1000_get_hw_semaphore_82574;
 157                 phy->ops.release        = e1000_put_hw_semaphore_82574;
 158                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
 159                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
 160                 break;
 161         default:
 162                 return -E1000_ERR_PHY;
 163                 break;
 164         }
 165
 166         /* This can only be done after all function pointers are setup. */
 167         ret_val = e1000_get_phy_id_82571(hw);
 168         if (ret_val) {
 169                 DEBUGOUT("Error getting PHY ID\n");
 170                 return ret_val;
 171         }
 172
 173         /* Verify phy id */
 174         switch (hw->mac.type) {
 175         case e1000_82571:
 176         case e1000_82572:
 177                 if (phy->id != IGP01E1000_I_PHY_ID)
 178                         ret_val = -E1000_ERR_PHY;
 179                 break;
 180         case e1000_82573:
 181                 if (phy->id != M88E1111_I_PHY_ID)
 182                         ret_val = -E1000_ERR_PHY;
 183                 break;
 184         case e1000_82574:
 185         case e1000_82583:
 186                 if (phy->id != BME1000_E_PHY_ID_R2)
 187                         ret_val = -E1000_ERR_PHY;
 188                 break;
 189         default:
 190                 ret_val = -E1000_ERR_PHY;
 191                 break;
 192         }
 193
 194         if (ret_val)
 195                 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
 196
 197         return ret_val;
 198 }
 199
 200 /**
 201  *  e1000_init_nvm_params_82571 - Init NVM func ptrs.
 202  *  @hw: pointer to the HW structure
 203  **/
 204 STATIC s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
 205 {
 206         struct e1000_nvm_info *nvm = &hw->nvm;
 207         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 208         u16 size;
 209
 210         DEBUGFUNC("e1000_init_nvm_params_82571");
 211
 212         nvm->opcode_bits = 8;
 213         nvm->delay_usec = 1;
 214         switch (nvm->override) {
 215         case e1000_nvm_override_spi_large:
 216                 nvm->page_size = 32;
 217                 nvm->address_bits = 16;
 218                 break;
 219         case e1000_nvm_override_spi_small:
 220                 nvm->page_size = 8;
 221                 nvm->address_bits = 8;
 222                 break;
 223         default:
 224                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 225                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 226                 break;
 227         }
 228
 229         switch (hw->mac.type) {
 230         case e1000_82573:
 231         case e1000_82574:
 232         case e1000_82583:
 233                 if (((eecd >> 15) & 0x3) == 0x3) {
 234                         nvm->type = e1000_nvm_flash_hw;
 235                         nvm->word_size = 2048;
 236                         /* Autonomous Flash update bit must be cleared due
 237                          * to Flash update issue.
 238                          */
 239                         eecd &= ~E1000_EECD_AUPDEN;
 240                         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 241                         break;
 242                 }
 243                 /* Fall Through */
 244         default:
 245                 nvm->type = e1000_nvm_eeprom_spi;
 246                 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 247                              E1000_EECD_SIZE_EX_SHIFT);
 248                 /* Added to a constant, "size" becomes the left-shift value
 249                  * for setting word_size.
 250                  */
 251                 size += NVM_WORD_SIZE_BASE_SHIFT;
 252
 253                 /* EEPROM access above 16k is unsupported */
 254                 if (size > 14)
 255                         size = 14;
 256                 nvm->word_size = 1 << size;
 257                 break;
 258         }
 259
 260         /* Function Pointers */
 261         switch (hw->mac.type) {
 262         case e1000_82574:
 263         case e1000_82583:
 264                 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
 265                 nvm->ops.release = e1000_put_hw_semaphore_82574;
 266                 break;
 267         default:
 268                 nvm->ops.acquire = e1000_acquire_nvm_82571;
 269                 nvm->ops.release = e1000_release_nvm_82571;
 270                 break;
 271         }
 272         nvm->ops.read = e1000_read_nvm_eerd;
 273         nvm->ops.update = e1000_update_nvm_checksum_82571;
 274         nvm->ops.validate = e1000_validate_nvm_checksum_82571;
 275         nvm->ops.valid_led_default = e1000_valid_led_default_82571;
 276         nvm->ops.write = e1000_write_nvm_82571;
 277
 278         return E1000_SUCCESS;
 279 }
 280
 281 /**
 282  *  e1000_init_mac_params_82571 - Init MAC func ptrs.
 283  *  @hw: pointer to the HW structure
 284  **/
 285 STATIC s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
 286 {
 287         struct e1000_mac_info *mac = &hw->mac;
 288         u32 swsm = 0;
 289         u32 swsm2 = 0;
 290         bool force_clear_smbi = false;
 291
 292         DEBUGFUNC("e1000_init_mac_params_82571");
 293
 294         /* Set media type and media-dependent function pointers */
 295         switch (hw->device_id) {
 296         case E1000_DEV_ID_82571EB_FIBER:
 297         case E1000_DEV_ID_82572EI_FIBER:
 298         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 299                 hw->phy.media_type = e1000_media_type_fiber;
 300                 mac->ops.setup_physical_interface =
 301                         e1000_setup_fiber_serdes_link_82571;
 302                 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
 303                 mac->ops.get_link_up_info =
 304                         e1000_get_speed_and_duplex_fiber_serdes_generic;
 305                 break;
 306         case E1000_DEV_ID_82571EB_SERDES:
 307         case E1000_DEV_ID_82571EB_SERDES_DUAL:
 308         case E1000_DEV_ID_82571EB_SERDES_QUAD:
 309         case E1000_DEV_ID_82572EI_SERDES:
 310                 hw->phy.media_type = e1000_media_type_internal_serdes;
 311                 mac->ops.setup_physical_interface =
 312                         e1000_setup_fiber_serdes_link_82571;
 313                 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
 314                 mac->ops.get_link_up_info =
 315                         e1000_get_speed_and_duplex_fiber_serdes_generic;
 316                 break;
 317         default:
 318                 hw->phy.media_type = e1000_media_type_copper;
 319                 mac->ops.setup_physical_interface =
 320                         e1000_setup_copper_link_82571;
 321                 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
 322                 mac->ops.get_link_up_info =
 323                         e1000_get_speed_and_duplex_copper_generic;
 324                 break;
 325         }
 326
 327         /* Set mta register count */
 328         mac->mta_reg_count = 128;
 329         /* Set rar entry count */
 330         mac->rar_entry_count = E1000_RAR_ENTRIES;
 331         /* Set if part includes ASF firmware */
 332         mac->asf_firmware_present = true;
 333         /* Adaptive IFS supported */
 334         mac->adaptive_ifs = true;
 335
 336         /* Function pointers */
 337
 338         /* bus type/speed/width */
 339         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 340         /* reset */
 341         mac->ops.reset_hw = e1000_reset_hw_82571;
 342         /* hw initialization */
 343         mac->ops.init_hw = e1000_init_hw_82571;
 344         /* link setup */
 345         mac->ops.setup_link = e1000_setup_link_82571;
 346         /* multicast address update */
 347         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 348         /* writing VFTA */
 349         mac->ops.write_vfta = e1000_write_vfta_generic;
 350         /* clearing VFTA */
 351         mac->ops.clear_vfta = e1000_clear_vfta_82571;
 352         /* read mac address */
 353         mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
 354         /* ID LED init */
 355         mac->ops.id_led_init = e1000_id_led_init_generic;
 356         /* setup LED */
 357         mac->ops.setup_led = e1000_setup_led_generic;
 358         /* cleanup LED */
 359         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 360         /* turn off LED */
 361         mac->ops.led_off = e1000_led_off_generic;
 362         /* clear hardware counters */
 363         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
 364
 365         /* MAC-specific function pointers */
 366         switch (hw->mac.type) {
 367         case e1000_82573:
 368                 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 369                 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 370                 mac->ops.led_on = e1000_led_on_generic;
 371                 mac->ops.blink_led = e1000_blink_led_generic;
 372
 373                 /* FWSM register */
 374                 mac->has_fwsm = true;
 375                 /* ARC supported; valid only if manageability features are
 376                  * enabled.
 377                  */
 378                 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) &
 379                                               E1000_FWSM_MODE_MASK);
 380                 break;
 381         case e1000_82574:
 382         case e1000_82583:
 383                 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 384                 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
 385                 mac->ops.led_on = e1000_led_on_82574;
 386                 break;
 387         default:
 388                 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 389                 mac->ops.led_on = e1000_led_on_generic;
 390                 mac->ops.blink_led = e1000_blink_led_generic;
 391
 392                 /* FWSM register */
 393                 mac->has_fwsm = true;
 394                 break;
 395         }
 396
 397         /* Ensure that the inter-port SWSM.SMBI lock bit is clear before
 398          * first NVM or PHY acess. This should be done for single-port
 399          * devices, and for one port only on dual-port devices so that
 400          * for those devices we can still use the SMBI lock to synchronize
 401          * inter-port accesses to the PHY & NVM.
 402          */
 403         switch (hw->mac.type) {
 404         case e1000_82571:
 405         case e1000_82572:
 406                 swsm2 = E1000_READ_REG(hw, E1000_SWSM2);
 407
 408                 if (!(swsm2 & E1000_SWSM2_LOCK)) {
 409                         /* Only do this for the first interface on this card */
 410                         E1000_WRITE_REG(hw, E1000_SWSM2, swsm2 |
 411                                         E1000_SWSM2_LOCK);
 412                         force_clear_smbi = true;
 413                 } else {
 414                         force_clear_smbi = false;
 415                 }
 416                 break;
 417         default:
 418                 force_clear_smbi = true;
 419                 break;
 420         }
 421
 422         if (force_clear_smbi) {
 423                 /* Make sure SWSM.SMBI is clear */
 424                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 425                 if (swsm & E1000_SWSM_SMBI) {
 426                         /* This bit should not be set on a first interface, and
 427                          * indicates that the bootagent or EFI code has
 428                          * improperly left this bit enabled
 429                          */
 430                         DEBUGOUT("Please update your 82571 Bootagent\n");
 431                 }
 432                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI);
 433         }
 434
 435         /* Initialze device specific counter of SMBI acquisition timeouts. */
 436          hw->dev_spec._82571.smb_counter = 0;
 437
 438         return E1000_SUCCESS;
 439 }
 440
 441 /**
 442  *  e1000_init_function_pointers_82571 - Init func ptrs.
 443  *  @hw: pointer to the HW structure
 444  *
 445  *  Called to initialize all function pointers and parameters.
 446  **/
 447 void e1000_init_function_pointers_82571(struct e1000_hw *hw)
 448 {
 449         DEBUGFUNC("e1000_init_function_pointers_82571");
 450
 451         hw->mac.ops.init_params = e1000_init_mac_params_82571;
 452         hw->nvm.ops.init_params = e1000_init_nvm_params_82571;
 453         hw->phy.ops.init_params = e1000_init_phy_params_82571;
 454 }
 455
 456 /**
 457  *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
 458  *  @hw: pointer to the HW structure
 459  *
 460  *  Reads the PHY registers and stores the PHY ID and possibly the PHY
 461  *  revision in the hardware structure.
 462  **/
 463 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
 464 {
 465         struct e1000_phy_info *phy = &hw->phy;
 466         s32 ret_val;
 467         u16 phy_id = 0;
 468
 469         DEBUGFUNC("e1000_get_phy_id_82571");
 470
 471         switch (hw->mac.type) {
 472         case e1000_82571:
 473         case e1000_82572:
 474                 /* The 82571 firmware may still be configuring the PHY.
 475                  * In this case, we cannot access the PHY until the
 476                  * configuration is done.  So we explicitly set the
 477                  * PHY ID.
 478                  */
 479                 phy->id = IGP01E1000_I_PHY_ID;
 480                 break;
 481         case e1000_82573:
 482                 return e1000_get_phy_id(hw);
 483                 break;
 484         case e1000_82574:
 485         case e1000_82583:
 486                 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
 487                 if (ret_val)
 488                         return ret_val;
 489
 490                 phy->id = (u32)(phy_id << 16);
 491                 usec_delay(20);
 492                 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
 493                 if (ret_val)
 494                         return ret_val;
 495
 496                 phy->id |= (u32)(phy_id);
 497                 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
 498                 break;
 499         default:
 500                 return -E1000_ERR_PHY;
 501                 break;
 502         }
 503
 504         return E1000_SUCCESS;
 505 }
 506
 507 /**
 508  *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
 509  *  @hw: pointer to the HW structure
 510  *
 511  *  Acquire the HW semaphore to access the PHY or NVM
 512  **/
 513 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
 514 {
 515         u32 swsm;
 516         s32 sw_timeout = hw->nvm.word_size + 1;
 517         s32 fw_timeout = hw->nvm.word_size + 1;
 518         s32 i = 0;
 519
 520         DEBUGFUNC("e1000_get_hw_semaphore_82571");
 521
 522         /* If we have timedout 3 times on trying to acquire
 523          * the inter-port SMBI semaphore, there is old code
 524          * operating on the other port, and it is not
 525          * releasing SMBI. Modify the number of times that
 526          * we try for the semaphore to interwork with this
 527          * older code.
 528          */
 529         if (hw->dev_spec._82571.smb_counter > 2)
 530                 sw_timeout = 1;
 531
 532         /* Get the SW semaphore */
 533         while (i < sw_timeout) {
 534                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 535                 if (!(swsm & E1000_SWSM_SMBI))
 536                         break;
 537
 538                 usec_delay(50);
 539                 i++;
 540         }
 541
 542         if (i == sw_timeout) {
 543                 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
 544                 hw->dev_spec._82571.smb_counter++;
 545         }
 546         /* Get the FW semaphore. */
 547         for (i = 0; i < fw_timeout; i++) {
 548                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 549                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
 550
 551                 /* Semaphore acquired if bit latched */
 552                 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
 553                         break;
 554
 555                 usec_delay(50);
 556         }
 557
 558         if (i == fw_timeout) {
 559                 /* Release semaphores */
 560                 e1000_put_hw_semaphore_82571(hw);
 561                 DEBUGOUT("Driver can't access the NVM\n");
 562                 return -E1000_ERR_NVM;
 563         }
 564
 565         return E1000_SUCCESS;
 566 }
 567
 568 /**
 569  *  e1000_put_hw_semaphore_82571 - Release hardware semaphore
 570  *  @hw: pointer to the HW structure
 571  *
 572  *  Release hardware semaphore used to access the PHY or NVM
 573  **/
 574 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
 575 {
 576         u32 swsm;
 577
 578         DEBUGFUNC("e1000_put_hw_semaphore_generic");
 579
 580         swsm = E1000_READ_REG(hw, E1000_SWSM);
 581
 582         swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
 583
 584         E1000_WRITE_REG(hw, E1000_SWSM, swsm);
 585 }
 586
 587 /**
 588  *  e1000_get_hw_semaphore_82573 - Acquire hardware semaphore
 589  *  @hw: pointer to the HW structure
 590  *
 591  *  Acquire the HW semaphore during reset.
 592  *
 593  **/
 594 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
 595 {
 596         u32 extcnf_ctrl;
 597         s32 i = 0;
 598
 599         DEBUGFUNC("e1000_get_hw_semaphore_82573");
 600
 601         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 602         do {
 603                 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 604                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
 605                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 606
 607                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
 608                         break;
 609
 610                 msec_delay(2);
 611                 i++;
 612         } while (i < MDIO_OWNERSHIP_TIMEOUT);
 613
 614         if (i == MDIO_OWNERSHIP_TIMEOUT) {
 615                 /* Release semaphores */
 616                 e1000_put_hw_semaphore_82573(hw);
 617                 DEBUGOUT("Driver can't access the PHY\n");
 618                 return -E1000_ERR_PHY;
 619         }
 620
 621         return E1000_SUCCESS;
 622 }
 623
 624 /**
 625  *  e1000_put_hw_semaphore_82573 - Release hardware semaphore
 626  *  @hw: pointer to the HW structure
 627  *
 628  *  Release hardware semaphore used during reset.
 629  *
 630  **/
 631 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
 632 {
 633         u32 extcnf_ctrl;
 634
 635         DEBUGFUNC("e1000_put_hw_semaphore_82573");
 636
 637         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 638         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 639         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
 640 }
 641
 642 /**
 643  *  e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
 644  *  @hw: pointer to the HW structure
 645  *
 646  *  Acquire the HW semaphore to access the PHY or NVM.
 647  *
 648  **/
 649 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
 650 {
 651         s32 ret_val;
 652
 653         DEBUGFUNC("e1000_get_hw_semaphore_82574");
 654
 655         E1000_MUTEX_LOCK(&hw->dev_spec._82571.swflag_mutex);
 656         ret_val = e1000_get_hw_semaphore_82573(hw);
 657         if (ret_val)
 658                 E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex);
 659         return ret_val;
 660 }
 661
 662 /**
 663  *  e1000_put_hw_semaphore_82574 - Release hardware semaphore
 664  *  @hw: pointer to the HW structure
 665  *
 666  *  Release hardware semaphore used to access the PHY or NVM
 667  *
 668  **/
 669 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
 670 {
 671         DEBUGFUNC("e1000_put_hw_semaphore_82574");
 672
 673         e1000_put_hw_semaphore_82573(hw);
 674         E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex);
 675 }
 676
 677 /**
 678  *  e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state
 679  *  @hw: pointer to the HW structure
 680  *  @active: true to enable LPLU, false to disable
 681  *
 682  *  Sets the LPLU D0 state according to the active flag.
 683  *  LPLU will not be activated unless the
 684  *  device autonegotiation advertisement meets standards of
 685  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 686  *  This is a function pointer entry point only called by
 687  *  PHY setup routines.
 688  **/
 689 STATIC s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
 690 {
 691         u32 data = E1000_READ_REG(hw, E1000_POEMB);
 692
 693         DEBUGFUNC("e1000_set_d0_lplu_state_82574");
 694
 695         if (active)
 696                 data |= E1000_PHY_CTRL_D0A_LPLU;
 697         else
 698                 data &= ~E1000_PHY_CTRL_D0A_LPLU;
 699
 700         E1000_WRITE_REG(hw, E1000_POEMB, data);
 701         return E1000_SUCCESS;
 702 }
 703
 704 /**
 705  *  e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3
 706  *  @hw: pointer to the HW structure
 707  *  @active: boolean used to enable/disable lplu
 708  *
 709  *  The low power link up (lplu) state is set to the power management level D3
 710  *  when active is true, else clear lplu for D3. LPLU
 711  *  is used during Dx states where the power conservation is most important.
 712  *  During driver activity, SmartSpeed should be enabled so performance is
 713  *  maintained.
 714  **/
 715 STATIC s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
 716 {
 717         u32 data = E1000_READ_REG(hw, E1000_POEMB);
 718
 719         DEBUGFUNC("e1000_set_d3_lplu_state_82574");
 720
 721         if (!active) {
 722                 data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
 723         } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 724                    (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
 725                    (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
 726                 data |= E1000_PHY_CTRL_NOND0A_LPLU;
 727         }
 728
 729         E1000_WRITE_REG(hw, E1000_POEMB, data);
 730         return E1000_SUCCESS;
 731 }
 732
 733 /**
 734  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
 735  *  @hw: pointer to the HW structure
 736  *
 737  *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
 738  *  Then for non-82573 hardware, set the EEPROM access request bit and wait
 739  *  for EEPROM access grant bit.  If the access grant bit is not set, release
 740  *  hardware semaphore.
 741  **/
 742 STATIC s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
 743 {
 744         s32 ret_val;
 745
 746         DEBUGFUNC("e1000_acquire_nvm_82571");
 747
 748         ret_val = e1000_get_hw_semaphore_82571(hw);
 749         if (ret_val)
 750                 return ret_val;
 751
 752         switch (hw->mac.type) {
 753         case e1000_82573:
 754                 break;
 755         default:
 756                 ret_val = e1000_acquire_nvm_generic(hw);
 757                 break;
 758         }
 759
 760         if (ret_val)
 761                 e1000_put_hw_semaphore_82571(hw);
 762
 763         return ret_val;
 764 }
 765
 766 /**
 767  *  e1000_release_nvm_82571 - Release exclusive access to EEPROM
 768  *  @hw: pointer to the HW structure
 769  *
 770  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 771  **/
 772 STATIC void e1000_release_nvm_82571(struct e1000_hw *hw)
 773 {
 774         DEBUGFUNC("e1000_release_nvm_82571");
 775
 776         e1000_release_nvm_generic(hw);
 777         e1000_put_hw_semaphore_82571(hw);
 778 }
 779
 780 /**
 781  *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
 782  *  @hw: pointer to the HW structure
 783  *  @offset: offset within the EEPROM to be written to
 784  *  @words: number of words to write
 785  *  @data: 16 bit word(s) to be written to the EEPROM
 786  *
 787  *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
 788  *
 789  *  If e1000_update_nvm_checksum is not called after this function, the
 790  *  EEPROM will most likely contain an invalid checksum.
 791  **/
 792 STATIC s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
 793                                  u16 *data)
 794 {
 795         s32 ret_val;
 796
 797         DEBUGFUNC("e1000_write_nvm_82571");
 798
 799         switch (hw->mac.type) {
 800         case e1000_82573:
 801         case e1000_82574:
 802         case e1000_82583:
 803                 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
 804                 break;
 805         case e1000_82571:
 806         case e1000_82572:
 807                 ret_val = e1000_write_nvm_spi(hw, offset, words, data);
 808                 break;
 809         default:
 810                 ret_val = -E1000_ERR_NVM;
 811                 break;
 812         }
 813
 814         return ret_val;
 815 }
 816
 817 /**
 818  *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum
 819  *  @hw: pointer to the HW structure
 820  *
 821  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 822  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 823  *  value to the EEPROM.
 824  **/
 825 STATIC s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
 826 {
 827         u32 eecd;
 828         s32 ret_val;
 829         u16 i;
 830
 831         DEBUGFUNC("e1000_update_nvm_checksum_82571");
 832
 833         ret_val = e1000_update_nvm_checksum_generic(hw);
 834         if (ret_val)
 835                 return ret_val;
 836
 837         /* If our nvm is an EEPROM, then we're done
 838          * otherwise, commit the checksum to the flash NVM.
 839          */
 840         if (hw->nvm.type != e1000_nvm_flash_hw)
 841                 return E1000_SUCCESS;
 842
 843         /* Check for pending operations. */
 844         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 845                 msec_delay(1);
 846                 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
 847                         break;
 848         }
 849
 850         if (i == E1000_FLASH_UPDATES)
 851                 return -E1000_ERR_NVM;
 852
 853         /* Reset the firmware if using STM opcode. */
 854         if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) {
 855                 /* The enabling of and the actual reset must be done
 856                  * in two write cycles.
 857                  */
 858                 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE);
 859                 E1000_WRITE_FLUSH(hw);
 860                 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET);
 861         }
 862
 863         /* Commit the write to flash */
 864         eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD;
 865         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 866
 867         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 868                 msec_delay(1);
 869                 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
 870                         break;
 871         }
 872
 873         if (i == E1000_FLASH_UPDATES)
 874                 return -E1000_ERR_NVM;
 875
 876         return E1000_SUCCESS;
 877 }
 878
 879 /**
 880  *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
 881  *  @hw: pointer to the HW structure
 882  *
 883  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
 884  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
 885  **/
 886 STATIC s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
 887 {
 888         DEBUGFUNC("e1000_validate_nvm_checksum_82571");
 889
 890         if (hw->nvm.type == e1000_nvm_flash_hw)
 891                 e1000_fix_nvm_checksum_82571(hw);
 892
 893         return e1000_validate_nvm_checksum_generic(hw);
 894 }
 895
 896 /**
 897  *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
 898  *  @hw: pointer to the HW structure
 899  *  @offset: offset within the EEPROM to be written to
 900  *  @words: number of words to write
 901  *  @data: 16 bit word(s) to be written to the EEPROM
 902  *
 903  *  After checking for invalid values, poll the EEPROM to ensure the previous
 904  *  command has completed before trying to write the next word.  After write
 905  *  poll for completion.
 906  *
 907  *  If e1000_update_nvm_checksum is not called after this function, the
 908  *  EEPROM will most likely contain an invalid checksum.
 909  **/
 910 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
 911                                       u16 words, u16 *data)
 912 {
 913         struct e1000_nvm_info *nvm = &hw->nvm;
 914         u32 i, eewr = 0;
 915         s32 ret_val = E1000_SUCCESS;
 916
 917         DEBUGFUNC("e1000_write_nvm_eewr_82571");
 918
 919         /* A check for invalid values:  offset too large, too many words,
 920          * and not enough words.
 921          */
 922         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 923             (words == 0)) {
 924                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 925                 return -E1000_ERR_NVM;
 926         }
 927
 928         for (i = 0; i < words; i++) {
 929                 eewr = ((data[i] << E1000_NVM_RW_REG_DATA) |
 930                         ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) |
 931                         E1000_NVM_RW_REG_START);
 932
 933                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 934                 if (ret_val)
 935                         break;
 936
 937                 E1000_WRITE_REG(hw, E1000_EEWR, eewr);
 938
 939                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 940                 if (ret_val)
 941                         break;
 942         }
 943
 944         return ret_val;
 945 }
 946
 947 /**
 948  *  e1000_get_cfg_done_82571 - Poll for configuration done
 949  *  @hw: pointer to the HW structure
 950  *
 951  *  Reads the management control register for the config done bit to be set.
 952  **/
 953 STATIC s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
 954 {
 955         s32 timeout = PHY_CFG_TIMEOUT;
 956
 957         DEBUGFUNC("e1000_get_cfg_done_82571");
 958
 959         while (timeout) {
 960                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) &
 961                     E1000_NVM_CFG_DONE_PORT_0)
 962                         break;
 963                 msec_delay(1);
 964                 timeout--;
 965         }
 966         if (!timeout) {
 967                 DEBUGOUT("MNG configuration cycle has not completed.\n");
 968                 return -E1000_ERR_RESET;
 969         }
 970
 971         return E1000_SUCCESS;
 972 }
 973
 974 /**
 975  *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
 976  *  @hw: pointer to the HW structure
 977  *  @active: true to enable LPLU, false to disable
 978  *
 979  *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
 980  *  this function also disables smart speed and vice versa.  LPLU will not be
 981  *  activated unless the device autonegotiation advertisement meets standards
 982  *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
 983  *  pointer entry point only called by PHY setup routines.
 984  **/
 985 STATIC s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
 986 {
 987         struct e1000_phy_info *phy = &hw->phy;
 988         s32 ret_val;
 989         u16 data;
 990
 991         DEBUGFUNC("e1000_set_d0_lplu_state_82571");
 992
 993         if (!(phy->ops.read_reg))
 994                 return E1000_SUCCESS;
 995
 996         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 997         if (ret_val)
 998                 return ret_val;
 999
1000         if (active) {
1001                 data |= IGP02E1000_PM_D0_LPLU;
1002                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1003                                              data);
1004                 if (ret_val)
1005                         return ret_val;
1006
1007                 /* When LPLU is enabled, we should disable SmartSpeed */
1008                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1009                                             &data);
1010                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1011                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1012                                              data);
1013                 if (ret_val)
1014                         return ret_val;
1015         } else {
1016                 data &= ~IGP02E1000_PM_D0_LPLU;
1017                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1018                                              data);
1019                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1020                  * during Dx states where the power conservation is most
1021                  * important.  During driver activity we should enable
1022                  * SmartSpeed, so performance is maintained.
1023                  */
1024                 if (phy->smart_speed == e1000_smart_speed_on) {
1025                         ret_val = phy->ops.read_reg(hw,
1026                                                     IGP01E1000_PHY_PORT_CONFIG,
1027                                                     &data);
1028                         if (ret_val)
1029                                 return ret_val;
1030
1031                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1032                         ret_val = phy->ops.write_reg(hw,
1033                                                      IGP01E1000_PHY_PORT_CONFIG,
1034                                                      data);
1035                         if (ret_val)
1036                                 return ret_val;
1037                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1038                         ret_val = phy->ops.read_reg(hw,
1039                                                     IGP01E1000_PHY_PORT_CONFIG,
1040                                                     &data);
1041                         if (ret_val)
1042                                 return ret_val;
1043
1044                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1045                         ret_val = phy->ops.write_reg(hw,
1046                                                      IGP01E1000_PHY_PORT_CONFIG,
1047                                                      data);
1048                         if (ret_val)
1049                                 return ret_val;
1050                 }
1051         }
1052
1053         return E1000_SUCCESS;
1054 }
1055
1056 /**
1057  *  e1000_reset_hw_82571 - Reset hardware
1058  *  @hw: pointer to the HW structure
1059  *
1060  *  This resets the hardware into a known state.
1061  **/
1062 STATIC s32 e1000_reset_hw_82571(struct e1000_hw *hw)
1063 {
1064         u32 ctrl, ctrl_ext, eecd, tctl;
1065         s32 ret_val;
1066
1067         DEBUGFUNC("e1000_reset_hw_82571");
1068
1069         /* Prevent the PCI-E bus from sticking if there is no TLP connection
1070          * on the last TLP read/write transaction when MAC is reset.
1071          */
1072         ret_val = e1000_disable_pcie_master_generic(hw);
1073         if (ret_val)
1074                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1075
1076         DEBUGOUT("Masking off all interrupts\n");
1077         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1078
1079         E1000_WRITE_REG(hw, E1000_RCTL, 0);
1080         tctl = E1000_READ_REG(hw, E1000_TCTL);
1081         tctl &= ~E1000_TCTL_EN;
1082         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1083         E1000_WRITE_FLUSH(hw);
1084
1085         msec_delay(10);
1086
1087         /* Must acquire the MDIO ownership before MAC reset.
1088          * Ownership defaults to firmware after a reset.
1089          */
1090         switch (hw->mac.type) {
1091         case e1000_82573:
1092                 ret_val = e1000_get_hw_semaphore_82573(hw);
1093                 break;
1094         case e1000_82574:
1095         case e1000_82583:
1096                 ret_val = e1000_get_hw_semaphore_82574(hw);
1097                 break;
1098         default:
1099                 break;
1100         }
1101         if (ret_val)
1102                 DEBUGOUT("Cannot acquire MDIO ownership\n");
1103
1104         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1105
1106         DEBUGOUT("Issuing a global reset to MAC\n");
1107         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1108
1109         /* Must release MDIO ownership and mutex after MAC reset. */
1110         switch (hw->mac.type) {
1111         case e1000_82574:
1112         case e1000_82583:
1113                 e1000_put_hw_semaphore_82574(hw);
1114                 break;
1115         default:
1116                 break;
1117         }
1118
1119         if (hw->nvm.type == e1000_nvm_flash_hw) {
1120                 usec_delay(10);
1121                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1122                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1123                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1124                 E1000_WRITE_FLUSH(hw);
1125         }
1126
1127         ret_val = e1000_get_auto_rd_done_generic(hw);
1128         if (ret_val)
1129                 /* We don't want to continue accessing MAC registers. */
1130                 return ret_val;
1131
1132         /* Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1133          * Need to wait for Phy configuration completion before accessing
1134          * NVM and Phy.
1135          */
1136
1137         switch (hw->mac.type) {
1138         case e1000_82571:
1139         case e1000_82572:
1140                 /* REQ and GNT bits need to be cleared when using AUTO_RD
1141                  * to access the EEPROM.
1142                  */
1143                 eecd = E1000_READ_REG(hw, E1000_EECD);
1144                 eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);
1145                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
1146                 break;
1147         case e1000_82573:
1148         case e1000_82574:
1149         case e1000_82583:
1150                 msec_delay(25);
1151                 break;
1152         default:
1153                 break;
1154         }
1155
1156         /* Clear any pending interrupt events. */
1157         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1158         E1000_READ_REG(hw, E1000_ICR);
1159
1160         if (hw->mac.type == e1000_82571) {
1161                 /* Install any alternate MAC address into RAR0 */
1162                 ret_val = e1000_check_alt_mac_addr_generic(hw);
1163                 if (ret_val)
1164                         return ret_val;
1165
1166                 e1000_set_laa_state_82571(hw, true);
1167         }
1168
1169         /* Reinitialize the 82571 serdes link state machine */
1170         if (hw->phy.media_type == e1000_media_type_internal_serdes)
1171                 hw->mac.serdes_link_state = e1000_serdes_link_down;
1172
1173         return E1000_SUCCESS;
1174 }
1175
1176 /**
1177  *  e1000_init_hw_82571 - Initialize hardware
1178  *  @hw: pointer to the HW structure
1179  *
1180  *  This inits the hardware readying it for operation.
1181  **/
1182 STATIC s32 e1000_init_hw_82571(struct e1000_hw *hw)
1183 {
1184         struct e1000_mac_info *mac = &hw->mac;
1185         u32 reg_data;
1186         s32 ret_val;
1187         u16 i, rar_count = mac->rar_entry_count;
1188
1189         DEBUGFUNC("e1000_init_hw_82571");
1190
1191         e1000_initialize_hw_bits_82571(hw);
1192
1193         /* Initialize identification LED */
1194         ret_val = mac->ops.id_led_init(hw);
1195         /* An error is not fatal and we should not stop init due to this */
1196         if (ret_val)
1197                 DEBUGOUT("Error initializing identification LED\n");
1198
1199         /* Disabling VLAN filtering */
1200         DEBUGOUT("Initializing the IEEE VLAN\n");
1201         mac->ops.clear_vfta(hw);
1202
1203         /* Setup the receive address.
1204          * If, however, a locally administered address was assigned to the
1205          * 82571, we must reserve a RAR for it to work around an issue where
1206          * resetting one port will reload the MAC on the other port.
1207          */
1208         if (e1000_get_laa_state_82571(hw))
1209                 rar_count--;
1210         e1000_init_rx_addrs_generic(hw, rar_count);
1211
1212         /* Zero out the Multicast HASH table */
1213         DEBUGOUT("Zeroing the MTA\n");
1214         for (i = 0; i < mac->mta_reg_count; i++)
1215                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1216
1217         /* Setup link and flow control */
1218         ret_val = mac->ops.setup_link(hw);
1219
1220         /* Set the transmit descriptor write-back policy */
1221         reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
1222         reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1223                     E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
1224         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
1225
1226         /* ...for both queues. */
1227         switch (mac->type) {
1228         case e1000_82573:
1229                 e1000_enable_tx_pkt_filtering_generic(hw);
1230                 /* fall through */
1231         case e1000_82574:
1232         case e1000_82583:
1233                 reg_data = E1000_READ_REG(hw, E1000_GCR);
1234                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1235                 E1000_WRITE_REG(hw, E1000_GCR, reg_data);
1236                 break;
1237         default:
1238                 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
1239                 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1240                             E1000_TXDCTL_FULL_TX_DESC_WB |
1241                             E1000_TXDCTL_COUNT_DESC);
1242                 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
1243                 break;
1244         }
1245
1246         /* Clear all of the statistics registers (clear on read).  It is
1247          * important that we do this after we have tried to establish link
1248          * because the symbol error count will increment wildly if there
1249          * is no link.
1250          */
1251         e1000_clear_hw_cntrs_82571(hw);
1252
1253         return ret_val;
1254 }
1255
1256 /**
1257  *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1258  *  @hw: pointer to the HW structure
1259  *
1260  *  Initializes required hardware-dependent bits needed for normal operation.
1261  **/
1262 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1263 {
1264         u32 reg;
1265
1266         DEBUGFUNC("e1000_initialize_hw_bits_82571");
1267
1268         /* Transmit Descriptor Control 0 */
1269         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1270         reg |= (1 << 22);
1271         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1272
1273         /* Transmit Descriptor Control 1 */
1274         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1275         reg |= (1 << 22);
1276         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1277
1278         /* Transmit Arbitration Control 0 */
1279         reg = E1000_READ_REG(hw, E1000_TARC(0));
1280         reg &= ~(0xF << 27); /* 30:27 */
1281         switch (hw->mac.type) {
1282         case e1000_82571:
1283         case e1000_82572:
1284                 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1285                 break;
1286         case e1000_82574:
1287         case e1000_82583:
1288                 reg |= (1 << 26);
1289                 break;
1290         default:
1291                 break;
1292         }
1293         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1294
1295         /* Transmit Arbitration Control 1 */
1296         reg = E1000_READ_REG(hw, E1000_TARC(1));
1297         switch (hw->mac.type) {
1298         case e1000_82571:
1299         case e1000_82572:
1300                 reg &= ~((1 << 29) | (1 << 30));
1301                 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1302                 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1303                         reg &= ~(1 << 28);
1304                 else
1305                         reg |= (1 << 28);
1306                 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1307                 break;
1308         default:
1309                 break;
1310         }
1311
1312         /* Device Control */
1313         switch (hw->mac.type) {
1314         case e1000_82573:
1315         case e1000_82574:
1316         case e1000_82583:
1317                 reg = E1000_READ_REG(hw, E1000_CTRL);
1318                 reg &= ~(1 << 29);
1319                 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1320                 break;
1321         default:
1322                 break;
1323         }
1324
1325         /* Extended Device Control */
1326         switch (hw->mac.type) {
1327         case e1000_82573:
1328         case e1000_82574:
1329         case e1000_82583:
1330                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1331                 reg &= ~(1 << 23);
1332                 reg |= (1 << 22);
1333                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1334                 break;
1335         default:
1336                 break;
1337         }
1338
1339         if (hw->mac.type == e1000_82571) {
1340                 reg = E1000_READ_REG(hw, E1000_PBA_ECC);
1341                 reg |= E1000_PBA_ECC_CORR_EN;
1342                 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg);
1343         }
1344
1345         /* Workaround for hardware errata.
1346          * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1347          */
1348         if ((hw->mac.type == e1000_82571) ||
1349            (hw->mac.type == e1000_82572)) {
1350                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1351                 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1352                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1353         }
1354
1355         /* Disable IPv6 extension header parsing because some malformed
1356          * IPv6 headers can hang the Rx.
1357          */
1358         if (hw->mac.type <= e1000_82573) {
1359                 reg = E1000_READ_REG(hw, E1000_RFCTL);
1360                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1361                 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
1362         }
1363
1364         /* PCI-Ex Control Registers */
1365         switch (hw->mac.type) {
1366         case e1000_82574:
1367         case e1000_82583:
1368                 reg = E1000_READ_REG(hw, E1000_GCR);
1369                 reg |= (1 << 22);
1370                 E1000_WRITE_REG(hw, E1000_GCR, reg);
1371
1372                 /* Workaround for hardware errata.
1373                  * apply workaround for hardware errata documented in errata
1374                  * docs Fixes issue where some error prone or unreliable PCIe
1375                  * completions are occurring, particularly with ASPM enabled.
1376                  * Without fix, issue can cause Tx timeouts.
1377                  */
1378                 reg = E1000_READ_REG(hw, E1000_GCR2);
1379                 reg |= 1;
1380                 E1000_WRITE_REG(hw, E1000_GCR2, reg);
1381                 break;
1382         default:
1383                 break;
1384         }
1385
1386         return;
1387 }
1388
1389 /**
1390  *  e1000_clear_vfta_82571 - Clear VLAN filter table
1391  *  @hw: pointer to the HW structure
1392  *
1393  *  Clears the register array which contains the VLAN filter table by
1394  *  setting all the values to 0.
1395  **/
1396 STATIC void e1000_clear_vfta_82571(struct e1000_hw *hw)
1397 {
1398         u32 offset;
1399         u32 vfta_value = 0;
1400         u32 vfta_offset = 0;
1401         u32 vfta_bit_in_reg = 0;
1402
1403         DEBUGFUNC("e1000_clear_vfta_82571");
1404
1405         switch (hw->mac.type) {
1406         case e1000_82573:
1407         case e1000_82574:
1408         case e1000_82583:
1409                 if (hw->mng_cookie.vlan_id != 0) {
1410                         /* The VFTA is a 4096b bit-field, each identifying
1411                          * a single VLAN ID.  The following operations
1412                          * determine which 32b entry (i.e. offset) into the
1413                          * array we want to set the VLAN ID (i.e. bit) of
1414                          * the manageability unit.
1415                          */
1416                         vfta_offset = (hw->mng_cookie.vlan_id >>
1417                                        E1000_VFTA_ENTRY_SHIFT) &
1418                             E1000_VFTA_ENTRY_MASK;
1419                         vfta_bit_in_reg =
1420                             1 << (hw->mng_cookie.vlan_id &
1421                                   E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1422                 }
1423                 break;
1424         default:
1425                 break;
1426         }
1427         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1428                 /* If the offset we want to clear is the same offset of the
1429                  * manageability VLAN ID, then clear all bits except that of
1430                  * the manageability unit.
1431                  */
1432                 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1433                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1434                 E1000_WRITE_FLUSH(hw);
1435         }
1436 }
1437
1438 /**
1439  *  e1000_check_mng_mode_82574 - Check manageability is enabled
1440  *  @hw: pointer to the HW structure
1441  *
1442  *  Reads the NVM Initialization Control Word 2 and returns true
1443  *  (>0) if any manageability is enabled, else false (0).
1444  **/
1445 STATIC bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1446 {
1447         u16 data;
1448
1449         DEBUGFUNC("e1000_check_mng_mode_82574");
1450
1451         hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1452         return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1453 }
1454
1455 /**
1456  *  e1000_led_on_82574 - Turn LED on
1457  *  @hw: pointer to the HW structure
1458  *
1459  *  Turn LED on.
1460  **/
1461 STATIC s32 e1000_led_on_82574(struct e1000_hw *hw)
1462 {
1463         u32 ctrl;
1464         u32 i;
1465
1466         DEBUGFUNC("e1000_led_on_82574");
1467
1468         ctrl = hw->mac.ledctl_mode2;
1469         if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) {
1470                 /* If no link, then turn LED on by setting the invert bit
1471                  * for each LED that's "on" (0x0E) in ledctl_mode2.
1472                  */
1473                 for (i = 0; i < 4; i++)
1474                         if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1475                             E1000_LEDCTL_MODE_LED_ON)
1476                                 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1477         }
1478         E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl);
1479
1480         return E1000_SUCCESS;
1481 }
1482
1483 /**
1484  *  e1000_check_phy_82574 - check 82574 phy hung state
1485  *  @hw: pointer to the HW structure
1486  *
1487  *  Returns whether phy is hung or not
1488  **/
1489 bool e1000_check_phy_82574(struct e1000_hw *hw)
1490 {
1491         u16 status_1kbt = 0;
1492         u16 receive_errors = 0;
1493         s32 ret_val;
1494
1495         DEBUGFUNC("e1000_check_phy_82574");
1496
1497         /* Read PHY Receive Error counter first, if its is max - all F's then
1498          * read the Base1000T status register If both are max then PHY is hung.
1499          */
1500         ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,
1501                                        &receive_errors);
1502         if (ret_val)
1503                 return false;
1504         if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1505                 ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,
1506                                                &status_1kbt);
1507                 if (ret_val)
1508                         return false;
1509                 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1510                     E1000_IDLE_ERROR_COUNT_MASK)
1511                         return true;
1512         }
1513
1514         return false;
1515 }
1516
1517
1518 /**
1519  *  e1000_setup_link_82571 - Setup flow control and link settings
1520  *  @hw: pointer to the HW structure
1521  *
1522  *  Determines which flow control settings to use, then configures flow
1523  *  control.  Calls the appropriate media-specific link configuration
1524  *  function.  Assuming the adapter has a valid link partner, a valid link
1525  *  should be established.  Assumes the hardware has previously been reset
1526  *  and the transmitter and receiver are not enabled.
1527  **/
1528 STATIC s32 e1000_setup_link_82571(struct e1000_hw *hw)
1529 {
1530         DEBUGFUNC("e1000_setup_link_82571");
1531
1532         /* 82573 does not have a word in the NVM to determine
1533          * the default flow control setting, so we explicitly
1534          * set it to full.
1535          */
1536         switch (hw->mac.type) {
1537         case e1000_82573:
1538         case e1000_82574:
1539         case e1000_82583:
1540                 if (hw->fc.requested_mode == e1000_fc_default)
1541                         hw->fc.requested_mode = e1000_fc_full;
1542                 break;
1543         default:
1544                 break;
1545         }
1546
1547         return e1000_setup_link_generic(hw);
1548 }
1549
1550 /**
1551  *  e1000_setup_copper_link_82571 - Configure copper link settings
1552  *  @hw: pointer to the HW structure
1553  *
1554  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1555  *  for link, once link is established calls to configure collision distance
1556  *  and flow control are called.
1557  **/
1558 STATIC s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1559 {
1560         u32 ctrl;
1561         s32 ret_val;
1562
1563         DEBUGFUNC("e1000_setup_copper_link_82571");
1564
1565         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1566         ctrl |= E1000_CTRL_SLU;
1567         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1568         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1569
1570         switch (hw->phy.type) {
1571         case e1000_phy_m88:
1572         case e1000_phy_bm:
1573                 ret_val = e1000_copper_link_setup_m88(hw);
1574                 break;
1575         case e1000_phy_igp_2:
1576                 ret_val = e1000_copper_link_setup_igp(hw);
1577                 break;
1578         default:
1579                 return -E1000_ERR_PHY;
1580                 break;
1581         }
1582
1583         if (ret_val)
1584                 return ret_val;
1585
1586         return e1000_setup_copper_link_generic(hw);
1587 }
1588
1589 /**
1590  *  e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1591  *  @hw: pointer to the HW structure
1592  *
1593  *  Configures collision distance and flow control for fiber and serdes links.
1594  *  Upon successful setup, poll for link.
1595  **/
1596 STATIC s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1597 {
1598         DEBUGFUNC("e1000_setup_fiber_serdes_link_82571");
1599
1600         switch (hw->mac.type) {
1601         case e1000_82571:
1602         case e1000_82572:
1603                 /* If SerDes loopback mode is entered, there is no form
1604                  * of reset to take the adapter out of that mode.  So we
1605                  * have to explicitly take the adapter out of loopback
1606                  * mode.  This prevents drivers from twiddling their thumbs
1607                  * if another tool failed to take it out of loopback mode.
1608                  */
1609                 E1000_WRITE_REG(hw, E1000_SCTL,
1610                                 E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1611                 break;
1612         default:
1613                 break;
1614         }
1615
1616         return e1000_setup_fiber_serdes_link_generic(hw);
1617 }
1618
1619 /**
1620  *  e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1621  *  @hw: pointer to the HW structure
1622  *
1623  *  Reports the link state as up or down.
1624  *
1625  *  If autonegotiation is supported by the link partner, the link state is
1626  *  determined by the result of autonegotiation. This is the most likely case.
1627  *  If autonegotiation is not supported by the link partner, and the link
1628  *  has a valid signal, force the link up.
1629  *
1630  *  The link state is represented internally here by 4 states:
1631  *
1632  *  1) down
1633  *  2) autoneg_progress
1634  *  3) autoneg_complete (the link successfully autonegotiated)
1635  *  4) forced_up (the link has been forced up, it did not autonegotiate)
1636  *
1637  **/
1638 STATIC s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1639 {
1640         struct e1000_mac_info *mac = &hw->mac;
1641         u32 rxcw;
1642         u32 ctrl;
1643         u32 status;
1644         u32 txcw;
1645         u32 i;
1646         s32 ret_val = E1000_SUCCESS;
1647
1648         DEBUGFUNC("e1000_check_for_serdes_link_82571");
1649
1650         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1651         status = E1000_READ_REG(hw, E1000_STATUS);
1652         E1000_READ_REG(hw, E1000_RXCW);
1653         /* SYNCH bit and IV bit are sticky */
1654         usec_delay(10);
1655         rxcw = E1000_READ_REG(hw, E1000_RXCW);
1656
1657         if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1658                 /* Receiver is synchronized with no invalid bits.  */
1659                 switch (mac->serdes_link_state) {
1660                 case e1000_serdes_link_autoneg_complete:
1661                         if (!(status & E1000_STATUS_LU)) {
1662                                 /* We have lost link, retry autoneg before
1663                                  * reporting link failure
1664                                  */
1665                                 mac->serdes_link_state =
1666                                     e1000_serdes_link_autoneg_progress;
1667                                 mac->serdes_has_link = false;
1668                                 DEBUGOUT("AN_UP     -> AN_PROG\n");
1669                         } else {
1670                                 mac->serdes_has_link = true;
1671                         }
1672                         break;
1673
1674                 case e1000_serdes_link_forced_up:
1675                         /* If we are receiving /C/ ordered sets, re-enable
1676                          * auto-negotiation in the TXCW register and disable
1677                          * forced link in the Device Control register in an
1678                          * attempt to auto-negotiate with our link partner.
1679                          */
1680                         if (rxcw & E1000_RXCW_C) {
1681                                 /* Enable autoneg, and unforce link up */
1682                                 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1683                                 E1000_WRITE_REG(hw, E1000_CTRL,
1684                                     (ctrl & ~E1000_CTRL_SLU));
1685                                 mac->serdes_link_state =
1686                                     e1000_serdes_link_autoneg_progress;
1687                                 mac->serdes_has_link = false;
1688                                 DEBUGOUT("FORCED_UP -> AN_PROG\n");
1689                         } else {
1690                                 mac->serdes_has_link = true;
1691                         }
1692                         break;
1693
1694                 case e1000_serdes_link_autoneg_progress:
1695                         if (rxcw & E1000_RXCW_C) {
1696                                 /* We received /C/ ordered sets, meaning the
1697                                  * link partner has autonegotiated, and we can
1698                                  * trust the Link Up (LU) status bit.
1699                                  */
1700                                 if (status & E1000_STATUS_LU) {
1701                                         mac->serdes_link_state =
1702                                             e1000_serdes_link_autoneg_complete;
1703                                         DEBUGOUT("AN_PROG   -> AN_UP\n");
1704                                         mac->serdes_has_link = true;
1705                                 } else {
1706                                         /* Autoneg completed, but failed. */
1707                                         mac->serdes_link_state =
1708                                             e1000_serdes_link_down;
1709                                         DEBUGOUT("AN_PROG   -> DOWN\n");
1710                                 }
1711                         } else {
1712                                 /* The link partner did not autoneg.
1713                                  * Force link up and full duplex, and change
1714                                  * state to forced.
1715                                  */
1716                                 E1000_WRITE_REG(hw, E1000_TXCW,
1717                                 (mac->txcw & ~E1000_TXCW_ANE));
1718                                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1719                                 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1720
1721                                 /* Configure Flow Control after link up. */
1722                                 ret_val =
1723                                     e1000_config_fc_after_link_up_generic(hw);
1724                                 if (ret_val) {
1725                                         DEBUGOUT("Error config flow control\n");
1726                                         break;
1727                                 }
1728                                 mac->serdes_link_state =
1729                                                 e1000_serdes_link_forced_up;
1730                                 mac->serdes_has_link = true;
1731                                 DEBUGOUT("AN_PROG   -> FORCED_UP\n");
1732                         }
1733                         break;
1734
1735                 case e1000_serdes_link_down:
1736                 default:
1737                         /* The link was down but the receiver has now gained
1738                          * valid sync, so lets see if we can bring the link
1739                          * up.
1740                          */
1741                         E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1742                         E1000_WRITE_REG(hw, E1000_CTRL, (ctrl &
1743                                         ~E1000_CTRL_SLU));
1744                         mac->serdes_link_state =
1745                                         e1000_serdes_link_autoneg_progress;
1746                         mac->serdes_has_link = false;
1747                         DEBUGOUT("DOWN      -> AN_PROG\n");
1748                         break;
1749                 }
1750         } else {
1751                 if (!(rxcw & E1000_RXCW_SYNCH)) {
1752                         mac->serdes_has_link = false;
1753                         mac->serdes_link_state = e1000_serdes_link_down;
1754                         DEBUGOUT("ANYSTATE  -> DOWN\n");
1755                 } else {
1756                         /* Check several times, if SYNCH bit and CONFIG
1757                          * bit both are consistently 1 then simply ignore
1758                          * the IV bit and restart Autoneg
1759                          */
1760                         for (i = 0; i < AN_RETRY_COUNT; i++) {
1761                                 usec_delay(10);
1762                                 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1763                                 if ((rxcw & E1000_RXCW_SYNCH) &&
1764                                     (rxcw & E1000_RXCW_C))
1765                                         continue;
1766
1767                                 if (rxcw & E1000_RXCW_IV) {
1768                                         mac->serdes_has_link = false;
1769                                         mac->serdes_link_state =
1770                                                         e1000_serdes_link_down;
1771                                         DEBUGOUT("ANYSTATE  -> DOWN\n");
1772                                         break;
1773                                 }
1774                         }
1775
1776                         if (i == AN_RETRY_COUNT) {
1777                                 txcw = E1000_READ_REG(hw, E1000_TXCW);
1778                                 txcw |= E1000_TXCW_ANE;
1779                                 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1780                                 mac->serdes_link_state =
1781                                         e1000_serdes_link_autoneg_progress;
1782                                 mac->serdes_has_link = false;
1783                                 DEBUGOUT("ANYSTATE  -> AN_PROG\n");
1784                         }
1785                 }
1786         }
1787
1788         return ret_val;
1789 }
1790
1791 /**
1792  *  e1000_valid_led_default_82571 - Verify a valid default LED config
1793  *  @hw: pointer to the HW structure
1794  *  @data: pointer to the NVM (EEPROM)
1795  *
1796  *  Read the EEPROM for the current default LED configuration.  If the
1797  *  LED configuration is not valid, set to a valid LED configuration.
1798  **/
1799 STATIC s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1800 {
1801         s32 ret_val;
1802
1803         DEBUGFUNC("e1000_valid_led_default_82571");
1804
1805         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1806         if (ret_val) {
1807                 DEBUGOUT("NVM Read Error\n");
1808                 return ret_val;
1809         }
1810
1811         switch (hw->mac.type) {
1812         case e1000_82573:
1813         case e1000_82574:
1814         case e1000_82583:
1815                 if (*data == ID_LED_RESERVED_F746)
1816                         *data = ID_LED_DEFAULT_82573;
1817                 break;
1818         default:
1819                 if (*data == ID_LED_RESERVED_0000 ||
1820                     *data == ID_LED_RESERVED_FFFF)
1821                         *data = ID_LED_DEFAULT;
1822                 break;
1823         }
1824
1825         return E1000_SUCCESS;
1826 }
1827
1828 /**
1829  *  e1000_get_laa_state_82571 - Get locally administered address state
1830  *  @hw: pointer to the HW structure
1831  *
1832  *  Retrieve and return the current locally administered address state.
1833  **/
1834 bool e1000_get_laa_state_82571(struct e1000_hw *hw)
1835 {
1836         DEBUGFUNC("e1000_get_laa_state_82571");
1837
1838         if (hw->mac.type != e1000_82571)
1839                 return false;
1840
1841         return hw->dev_spec._82571.laa_is_present;
1842 }
1843
1844 /**
1845  *  e1000_set_laa_state_82571 - Set locally administered address state
1846  *  @hw: pointer to the HW structure
1847  *  @state: enable/disable locally administered address
1848  *
1849  *  Enable/Disable the current locally administered address state.
1850  **/
1851 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state)
1852 {
1853         DEBUGFUNC("e1000_set_laa_state_82571");
1854
1855         if (hw->mac.type != e1000_82571)
1856                 return;
1857
1858         hw->dev_spec._82571.laa_is_present = state;
1859
1860         /* If workaround is activated... */
1861         if (state)
1862                 /* Hold a copy of the LAA in RAR[14] This is done so that
1863                  * between the time RAR[0] gets clobbered and the time it
1864                  * gets fixed, the actual LAA is in one of the RARs and no
1865                  * incoming packets directed to this port are dropped.
1866                  * Eventually the LAA will be in RAR[0] and RAR[14].
1867                  */
1868                 hw->mac.ops.rar_set(hw, hw->mac.addr,
1869                                     hw->mac.rar_entry_count - 1);
1870         return;
1871 }
1872
1873 /**
1874  *  e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1875  *  @hw: pointer to the HW structure
1876  *
1877  *  Verifies that the EEPROM has completed the update.  After updating the
1878  *  EEPROM, we need to check bit 15 in work 0x23 for the checksum fix.  If
1879  *  the checksum fix is not implemented, we need to set the bit and update
1880  *  the checksum.  Otherwise, if bit 15 is set and the checksum is incorrect,
1881  *  we need to return bad checksum.
1882  **/
1883 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1884 {
1885         struct e1000_nvm_info *nvm = &hw->nvm;
1886         s32 ret_val;
1887         u16 data;
1888
1889         DEBUGFUNC("e1000_fix_nvm_checksum_82571");
1890
1891         if (nvm->type != e1000_nvm_flash_hw)
1892                 return E1000_SUCCESS;
1893
1894         /* Check bit 4 of word 10h.  If it is 0, firmware is done updating
1895          * 10h-12h.  Checksum may need to be fixed.
1896          */
1897         ret_val = nvm->ops.read(hw, 0x10, 1, &data);
1898         if (ret_val)
1899                 return ret_val;
1900
1901         if (!(data & 0x10)) {
1902                 /* Read 0x23 and check bit 15.  This bit is a 1
1903                  * when the checksum has already been fixed.  If
1904                  * the checksum is still wrong and this bit is a
1905                  * 1, we need to return bad checksum.  Otherwise,
1906                  * we need to set this bit to a 1 and update the
1907                  * checksum.
1908                  */
1909                 ret_val = nvm->ops.read(hw, 0x23, 1, &data);
1910                 if (ret_val)
1911                         return ret_val;
1912
1913                 if (!(data & 0x8000)) {
1914                         data |= 0x8000;
1915                         ret_val = nvm->ops.write(hw, 0x23, 1, &data);
1916                         if (ret_val)
1917                                 return ret_val;
1918                         ret_val = nvm->ops.update(hw);
1919                 }
1920         }
1921
1922         return E1000_SUCCESS;
1923 }
1924
1925
1926 /**
1927  *  e1000_read_mac_addr_82571 - Read device MAC address
1928  *  @hw: pointer to the HW structure
1929  **/
1930 STATIC s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1931 {
1932         DEBUGFUNC("e1000_read_mac_addr_82571");
1933
1934         if (hw->mac.type == e1000_82571) {
1935                 s32 ret_val;
1936
1937                 /* If there's an alternate MAC address place it in RAR0
1938                  * so that it will override the Si installed default perm
1939                  * address.
1940                  */
1941                 ret_val = e1000_check_alt_mac_addr_generic(hw);
1942                 if (ret_val)
1943                         return ret_val;
1944         }
1945
1946         return e1000_read_mac_addr_generic(hw);
1947 }
1948
1949 /**
1950  * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1951  * @hw: pointer to the HW structure
1952  *
1953  * In the case of a PHY power down to save power, or to turn off link during a
1954  * driver unload, or wake on lan is not enabled, remove the link.
1955  **/
1956 STATIC void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1957 {
1958         struct e1000_phy_info *phy = &hw->phy;
1959         struct e1000_mac_info *mac = &hw->mac;
1960
1961         if (!phy->ops.check_reset_block)
1962                 return;
1963
1964         /* If the management interface is not enabled, then power down */
1965         if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1966                 e1000_power_down_phy_copper(hw);
1967
1968         return;
1969 }
1970
1971 /**
1972  *  e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1973  *  @hw: pointer to the HW structure
1974  *
1975  *  Clears the hardware counters by reading the counter registers.
1976  **/
1977 STATIC void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1978 {
1979         DEBUGFUNC("e1000_clear_hw_cntrs_82571");
1980
1981         e1000_clear_hw_cntrs_base_generic(hw);
1982
1983         E1000_READ_REG(hw, E1000_PRC64);
1984         E1000_READ_REG(hw, E1000_PRC127);
1985         E1000_READ_REG(hw, E1000_PRC255);
1986         E1000_READ_REG(hw, E1000_PRC511);
1987         E1000_READ_REG(hw, E1000_PRC1023);
1988         E1000_READ_REG(hw, E1000_PRC1522);
1989         E1000_READ_REG(hw, E1000_PTC64);
1990         E1000_READ_REG(hw, E1000_PTC127);
1991         E1000_READ_REG(hw, E1000_PTC255);
1992         E1000_READ_REG(hw, E1000_PTC511);
1993         E1000_READ_REG(hw, E1000_PTC1023);
1994         E1000_READ_REG(hw, E1000_PTC1522);
1995
1996         E1000_READ_REG(hw, E1000_ALGNERRC);
1997         E1000_READ_REG(hw, E1000_RXERRC);
1998         E1000_READ_REG(hw, E1000_TNCRS);
1999         E1000_READ_REG(hw, E1000_CEXTERR);
2000         E1000_READ_REG(hw, E1000_TSCTC);
2001         E1000_READ_REG(hw, E1000_TSCTFC);
2002
2003         E1000_READ_REG(hw, E1000_MGTPRC);
2004         E1000_READ_REG(hw, E1000_MGTPDC);
2005         E1000_READ_REG(hw, E1000_MGTPTC);
2006
2007         E1000_READ_REG(hw, E1000_IAC);
2008         E1000_READ_REG(hw, E1000_ICRXOC);
2009
2010         E1000_READ_REG(hw, E1000_ICRXPTC);
2011         E1000_READ_REG(hw, E1000_ICRXATC);
2012         E1000_READ_REG(hw, E1000_ICTXPTC);
2013         E1000_READ_REG(hw, E1000_ICTXATC);
2014         E1000_READ_REG(hw, E1000_ICTXQEC);
2015         E1000_READ_REG(hw, E1000_ICTXQMTC);
2016         E1000_READ_REG(hw, E1000_ICRXDMTC);
2017 }