lib/librte_pmd_e1000/e1000/e1000_82571.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2012, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 /* 82571EB Gigabit Ethernet Controller
  35  * 82571EB Gigabit Ethernet Controller (Copper)
  36  * 82571EB Gigabit Ethernet Controller (Fiber)
  37  * 82571EB Dual Port Gigabit Mezzanine Adapter
  38  * 82571EB Quad Port Gigabit Mezzanine Adapter
  39  * 82571PT Gigabit PT Quad Port Server ExpressModule
  40  * 82572EI Gigabit Ethernet Controller (Copper)
  41  * 82572EI Gigabit Ethernet Controller (Fiber)
  42  * 82572EI Gigabit Ethernet Controller
  43  * 82573V Gigabit Ethernet Controller (Copper)
  44  * 82573E Gigabit Ethernet Controller (Copper)
  45  * 82573L Gigabit Ethernet Controller
  46  * 82574L Gigabit Network Connection
  47  * 82583V Gigabit Network Connection
  48  */
  49
  50 #include "e1000_api.h"
  51
  52 STATIC s32  e1000_init_phy_params_82571(struct e1000_hw *hw);
  53 STATIC s32  e1000_init_nvm_params_82571(struct e1000_hw *hw);
  54 STATIC s32  e1000_init_mac_params_82571(struct e1000_hw *hw);
  55 STATIC s32  e1000_acquire_nvm_82571(struct e1000_hw *hw);
  56 STATIC void e1000_release_nvm_82571(struct e1000_hw *hw);
  57 STATIC s32  e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
  58                                   u16 words, u16 *data);
  59 STATIC s32  e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
  60 STATIC s32  e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
  61 STATIC s32  e1000_get_cfg_done_82571(struct e1000_hw *hw);
  62 STATIC s32  e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
  63                                           bool active);
  64 STATIC s32  e1000_reset_hw_82571(struct e1000_hw *hw);
  65 STATIC s32  e1000_init_hw_82571(struct e1000_hw *hw);
  66 STATIC void e1000_clear_vfta_82571(struct e1000_hw *hw);
  67 STATIC bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
  68 STATIC s32 e1000_led_on_82574(struct e1000_hw *hw);
  69 STATIC s32  e1000_setup_link_82571(struct e1000_hw *hw);
  70 STATIC s32  e1000_setup_copper_link_82571(struct e1000_hw *hw);
  71 STATIC s32  e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
  72 STATIC s32  e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
  73 STATIC s32  e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
  74 STATIC void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
  75 static s32  e1000_get_hw_semaphore_82571(struct e1000_hw *hw);
  76 static s32  e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
  77 static s32  e1000_get_phy_id_82571(struct e1000_hw *hw);
  78 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
  79 static s32  e1000_get_hw_semaphore_82573(struct e1000_hw *hw);
  80 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
  81 static s32  e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
  82 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
  83 STATIC s32  e1000_set_d0_lplu_state_82574(struct e1000_hw *hw,
  84                                           bool active);
  85 STATIC s32  e1000_set_d3_lplu_state_82574(struct e1000_hw *hw,
  86                                           bool active);
  87 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
  88 static s32  e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
  89                                        u16 words, u16 *data);
  90 STATIC s32  e1000_read_mac_addr_82571(struct e1000_hw *hw);
  91 STATIC void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
  92
  93 /**
  94  *  e1000_init_phy_params_82571 - Init PHY func ptrs.
  95  *  @hw: pointer to the HW structure
  96  **/
  97 STATIC s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
  98 {
  99         struct e1000_phy_info *phy = &hw->phy;
 100         s32 ret_val;
 101
 102         DEBUGFUNC("e1000_init_phy_params_82571");
 103
 104         if (hw->phy.media_type != e1000_media_type_copper) {
 105                 phy->type = e1000_phy_none;
 106                 return E1000_SUCCESS;
 107         }
 108
 109         phy->addr                       = 1;
 110         phy->autoneg_mask               = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 111         phy->reset_delay_us             = 100;
 112
 113         phy->ops.check_reset_block      = e1000_check_reset_block_generic;
 114         phy->ops.reset                  = e1000_phy_hw_reset_generic;
 115         phy->ops.set_d0_lplu_state      = e1000_set_d0_lplu_state_82571;
 116         phy->ops.set_d3_lplu_state      = e1000_set_d3_lplu_state_generic;
 117         phy->ops.power_up               = e1000_power_up_phy_copper;
 118         phy->ops.power_down             = e1000_power_down_phy_copper_82571;
 119
 120         switch (hw->mac.type) {
 121         case e1000_82571:
 122         case e1000_82572:
 123                 phy->type               = e1000_phy_igp_2;
 124                 phy->ops.get_cfg_done   = e1000_get_cfg_done_82571;
 125                 phy->ops.get_info       = e1000_get_phy_info_igp;
 126                 phy->ops.check_polarity = e1000_check_polarity_igp;
 127                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 128                 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 129                 phy->ops.read_reg       = e1000_read_phy_reg_igp;
 130                 phy->ops.write_reg      = e1000_write_phy_reg_igp;
 131                 phy->ops.acquire        = e1000_get_hw_semaphore_82571;
 132                 phy->ops.release        = e1000_put_hw_semaphore_82571;
 133                 break;
 134         case e1000_82573:
 135                 phy->type               = e1000_phy_m88;
 136                 phy->ops.get_cfg_done   = e1000_get_cfg_done_generic;
 137                 phy->ops.get_info       = e1000_get_phy_info_m88;
 138                 phy->ops.check_polarity = e1000_check_polarity_m88;
 139                 phy->ops.commit         = e1000_phy_sw_reset_generic;
 140                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 141                 phy->ops.get_cable_length = e1000_get_cable_length_m88;
 142                 phy->ops.read_reg       = e1000_read_phy_reg_m88;
 143                 phy->ops.write_reg      = e1000_write_phy_reg_m88;
 144                 phy->ops.acquire        = e1000_get_hw_semaphore_82571;
 145                 phy->ops.release        = e1000_put_hw_semaphore_82571;
 146                 break;
 147         case e1000_82574:
 148         case e1000_82583:
 149                 E1000_MUTEX_INIT(&hw->dev_spec._82571.swflag_mutex);
 150
 151                 phy->type               = e1000_phy_bm;
 152                 phy->ops.get_cfg_done   = e1000_get_cfg_done_generic;
 153                 phy->ops.get_info       = e1000_get_phy_info_m88;
 154                 phy->ops.check_polarity = e1000_check_polarity_m88;
 155                 phy->ops.commit         = e1000_phy_sw_reset_generic;
 156                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 157                 phy->ops.get_cable_length = e1000_get_cable_length_m88;
 158                 phy->ops.read_reg       = e1000_read_phy_reg_bm2;
 159                 phy->ops.write_reg      = e1000_write_phy_reg_bm2;
 160                 phy->ops.acquire        = e1000_get_hw_semaphore_82574;
 161                 phy->ops.release        = e1000_put_hw_semaphore_82574;
 162                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
 163                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
 164                 break;
 165         default:
 166                 return -E1000_ERR_PHY;
 167                 break;
 168         }
 169
 170         /* This can only be done after all function pointers are setup. */
 171         ret_val = e1000_get_phy_id_82571(hw);
 172         if (ret_val) {
 173                 DEBUGOUT("Error getting PHY ID\n");
 174                 return ret_val;
 175         }
 176
 177         /* Verify phy id */
 178         switch (hw->mac.type) {
 179         case e1000_82571:
 180         case e1000_82572:
 181                 if (phy->id != IGP01E1000_I_PHY_ID)
 182                         ret_val = -E1000_ERR_PHY;
 183                 break;
 184         case e1000_82573:
 185                 if (phy->id != M88E1111_I_PHY_ID)
 186                         ret_val = -E1000_ERR_PHY;
 187                 break;
 188         case e1000_82574:
 189         case e1000_82583:
 190                 if (phy->id != BME1000_E_PHY_ID_R2)
 191                         ret_val = -E1000_ERR_PHY;
 192                 break;
 193         default:
 194                 ret_val = -E1000_ERR_PHY;
 195                 break;
 196         }
 197
 198         if (ret_val)
 199                 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
 200
 201         return ret_val;
 202 }
 203
 204 /**
 205  *  e1000_init_nvm_params_82571 - Init NVM func ptrs.
 206  *  @hw: pointer to the HW structure
 207  **/
 208 STATIC s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
 209 {
 210         struct e1000_nvm_info *nvm = &hw->nvm;
 211         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 212         u16 size;
 213
 214         DEBUGFUNC("e1000_init_nvm_params_82571");
 215
 216         nvm->opcode_bits = 8;
 217         nvm->delay_usec = 1;
 218         switch (nvm->override) {
 219         case e1000_nvm_override_spi_large:
 220                 nvm->page_size = 32;
 221                 nvm->address_bits = 16;
 222                 break;
 223         case e1000_nvm_override_spi_small:
 224                 nvm->page_size = 8;
 225                 nvm->address_bits = 8;
 226                 break;
 227         default:
 228                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 229                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 230                 break;
 231         }
 232
 233         switch (hw->mac.type) {
 234         case e1000_82573:
 235         case e1000_82574:
 236         case e1000_82583:
 237                 if (((eecd >> 15) & 0x3) == 0x3) {
 238                         nvm->type = e1000_nvm_flash_hw;
 239                         nvm->word_size = 2048;
 240                         /* Autonomous Flash update bit must be cleared due
 241                          * to Flash update issue.
 242                          */
 243                         eecd &= ~E1000_EECD_AUPDEN;
 244                         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 245                         break;
 246                 }
 247                 /* Fall Through */
 248         default:
 249                 nvm->type = e1000_nvm_eeprom_spi;
 250                 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 251                              E1000_EECD_SIZE_EX_SHIFT);
 252                 /* Added to a constant, "size" becomes the left-shift value
 253                  * for setting word_size.
 254                  */
 255                 size += NVM_WORD_SIZE_BASE_SHIFT;
 256
 257                 /* EEPROM access above 16k is unsupported */
 258                 if (size > 14)
 259                         size = 14;
 260                 nvm->word_size = 1 << size;
 261                 break;
 262         }
 263
 264         /* Function Pointers */
 265         switch (hw->mac.type) {
 266         case e1000_82574:
 267         case e1000_82583:
 268                 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
 269                 nvm->ops.release = e1000_put_hw_semaphore_82574;
 270                 break;
 271         default:
 272                 nvm->ops.acquire = e1000_acquire_nvm_82571;
 273                 nvm->ops.release = e1000_release_nvm_82571;
 274                 break;
 275         }
 276         nvm->ops.read = e1000_read_nvm_eerd;
 277         nvm->ops.update = e1000_update_nvm_checksum_82571;
 278         nvm->ops.validate = e1000_validate_nvm_checksum_82571;
 279         nvm->ops.valid_led_default = e1000_valid_led_default_82571;
 280         nvm->ops.write = e1000_write_nvm_82571;
 281
 282         return E1000_SUCCESS;
 283 }
 284
 285 /**
 286  *  e1000_init_mac_params_82571 - Init MAC func ptrs.
 287  *  @hw: pointer to the HW structure
 288  **/
 289 STATIC s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
 290 {
 291         struct e1000_mac_info *mac = &hw->mac;
 292         u32 swsm = 0;
 293         u32 swsm2 = 0;
 294         bool force_clear_smbi = false;
 295
 296         DEBUGFUNC("e1000_init_mac_params_82571");
 297
 298         /* Set media type and media-dependent function pointers */
 299         switch (hw->device_id) {
 300         case E1000_DEV_ID_82571EB_FIBER:
 301         case E1000_DEV_ID_82572EI_FIBER:
 302         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 303                 hw->phy.media_type = e1000_media_type_fiber;
 304                 mac->ops.setup_physical_interface =
 305                         e1000_setup_fiber_serdes_link_82571;
 306                 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
 307                 mac->ops.get_link_up_info =
 308                         e1000_get_speed_and_duplex_fiber_serdes_generic;
 309                 break;
 310         case E1000_DEV_ID_82571EB_SERDES:
 311         case E1000_DEV_ID_82571EB_SERDES_DUAL:
 312         case E1000_DEV_ID_82571EB_SERDES_QUAD:
 313         case E1000_DEV_ID_82572EI_SERDES:
 314                 hw->phy.media_type = e1000_media_type_internal_serdes;
 315                 mac->ops.setup_physical_interface =
 316                         e1000_setup_fiber_serdes_link_82571;
 317                 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
 318                 mac->ops.get_link_up_info =
 319                         e1000_get_speed_and_duplex_fiber_serdes_generic;
 320                 break;
 321         default:
 322                 hw->phy.media_type = e1000_media_type_copper;
 323                 mac->ops.setup_physical_interface =
 324                         e1000_setup_copper_link_82571;
 325                 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
 326                 mac->ops.get_link_up_info =
 327                         e1000_get_speed_and_duplex_copper_generic;
 328                 break;
 329         }
 330
 331         /* Set mta register count */
 332         mac->mta_reg_count = 128;
 333         /* Set rar entry count */
 334         mac->rar_entry_count = E1000_RAR_ENTRIES;
 335         /* Set if part includes ASF firmware */
 336         mac->asf_firmware_present = true;
 337         /* Adaptive IFS supported */
 338         mac->adaptive_ifs = true;
 339
 340         /* Function pointers */
 341
 342         /* bus type/speed/width */
 343         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 344         /* reset */
 345         mac->ops.reset_hw = e1000_reset_hw_82571;
 346         /* hw initialization */
 347         mac->ops.init_hw = e1000_init_hw_82571;
 348         /* link setup */
 349         mac->ops.setup_link = e1000_setup_link_82571;
 350         /* multicast address update */
 351         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 352         /* writing VFTA */
 353         mac->ops.write_vfta = e1000_write_vfta_generic;
 354         /* clearing VFTA */
 355         mac->ops.clear_vfta = e1000_clear_vfta_82571;
 356         /* read mac address */
 357         mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
 358         /* ID LED init */
 359         mac->ops.id_led_init = e1000_id_led_init_generic;
 360         /* setup LED */
 361         mac->ops.setup_led = e1000_setup_led_generic;
 362         /* cleanup LED */
 363         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 364         /* turn off LED */
 365         mac->ops.led_off = e1000_led_off_generic;
 366         /* clear hardware counters */
 367         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
 368
 369         /* MAC-specific function pointers */
 370         switch (hw->mac.type) {
 371         case e1000_82573:
 372                 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 373                 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 374                 mac->ops.led_on = e1000_led_on_generic;
 375                 mac->ops.blink_led = e1000_blink_led_generic;
 376
 377                 /* FWSM register */
 378                 mac->has_fwsm = true;
 379                 /* ARC supported; valid only if manageability features are
 380                  * enabled.
 381                  */
 382                 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) &
 383                                               E1000_FWSM_MODE_MASK);
 384                 break;
 385         case e1000_82574:
 386         case e1000_82583:
 387                 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 388                 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
 389                 mac->ops.led_on = e1000_led_on_82574;
 390                 break;
 391         default:
 392                 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 393                 mac->ops.led_on = e1000_led_on_generic;
 394                 mac->ops.blink_led = e1000_blink_led_generic;
 395
 396                 /* FWSM register */
 397                 mac->has_fwsm = true;
 398                 break;
 399         }
 400
 401         /* Ensure that the inter-port SWSM.SMBI lock bit is clear before
 402          * first NVM or PHY acess. This should be done for single-port
 403          * devices, and for one port only on dual-port devices so that
 404          * for those devices we can still use the SMBI lock to synchronize
 405          * inter-port accesses to the PHY & NVM.
 406          */
 407         switch (hw->mac.type) {
 408         case e1000_82571:
 409         case e1000_82572:
 410                 swsm2 = E1000_READ_REG(hw, E1000_SWSM2);
 411
 412                 if (!(swsm2 & E1000_SWSM2_LOCK)) {
 413                         /* Only do this for the first interface on this card */
 414                         E1000_WRITE_REG(hw, E1000_SWSM2, swsm2 |
 415                                         E1000_SWSM2_LOCK);
 416                         force_clear_smbi = true;
 417                 } else {
 418                         force_clear_smbi = false;
 419                 }
 420                 break;
 421         default:
 422                 force_clear_smbi = true;
 423                 break;
 424         }
 425
 426         if (force_clear_smbi) {
 427                 /* Make sure SWSM.SMBI is clear */
 428                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 429                 if (swsm & E1000_SWSM_SMBI) {
 430                         /* This bit should not be set on a first interface, and
 431                          * indicates that the bootagent or EFI code has
 432                          * improperly left this bit enabled
 433                          */
 434                         DEBUGOUT("Please update your 82571 Bootagent\n");
 435                 }
 436                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI);
 437         }
 438
 439         /* Initialze device specific counter of SMBI acquisition timeouts. */
 440          hw->dev_spec._82571.smb_counter = 0;
 441
 442         return E1000_SUCCESS;
 443 }
 444
 445 /**
 446  *  e1000_init_function_pointers_82571 - Init func ptrs.
 447  *  @hw: pointer to the HW structure
 448  *
 449  *  Called to initialize all function pointers and parameters.
 450  **/
 451 void e1000_init_function_pointers_82571(struct e1000_hw *hw)
 452 {
 453         DEBUGFUNC("e1000_init_function_pointers_82571");
 454
 455         hw->mac.ops.init_params = e1000_init_mac_params_82571;
 456         hw->nvm.ops.init_params = e1000_init_nvm_params_82571;
 457         hw->phy.ops.init_params = e1000_init_phy_params_82571;
 458 }
 459
 460 /**
 461  *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
 462  *  @hw: pointer to the HW structure
 463  *
 464  *  Reads the PHY registers and stores the PHY ID and possibly the PHY
 465  *  revision in the hardware structure.
 466  **/
 467 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
 468 {
 469         struct e1000_phy_info *phy = &hw->phy;
 470         s32 ret_val;
 471         u16 phy_id = 0;
 472
 473         DEBUGFUNC("e1000_get_phy_id_82571");
 474
 475         switch (hw->mac.type) {
 476         case e1000_82571:
 477         case e1000_82572:
 478                 /* The 82571 firmware may still be configuring the PHY.
 479                  * In this case, we cannot access the PHY until the
 480                  * configuration is done.  So we explicitly set the
 481                  * PHY ID.
 482                  */
 483                 phy->id = IGP01E1000_I_PHY_ID;
 484                 break;
 485         case e1000_82573:
 486                 return e1000_get_phy_id(hw);
 487                 break;
 488         case e1000_82574:
 489         case e1000_82583:
 490                 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
 491                 if (ret_val)
 492                         return ret_val;
 493
 494                 phy->id = (u32)(phy_id << 16);
 495                 usec_delay(20);
 496                 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
 497                 if (ret_val)
 498                         return ret_val;
 499
 500                 phy->id |= (u32)(phy_id);
 501                 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
 502                 break;
 503         default:
 504                 return -E1000_ERR_PHY;
 505                 break;
 506         }
 507
 508         return E1000_SUCCESS;
 509 }
 510
 511 /**
 512  *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
 513  *  @hw: pointer to the HW structure
 514  *
 515  *  Acquire the HW semaphore to access the PHY or NVM
 516  **/
 517 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
 518 {
 519         u32 swsm;
 520         s32 sw_timeout = hw->nvm.word_size + 1;
 521         s32 fw_timeout = hw->nvm.word_size + 1;
 522         s32 i = 0;
 523
 524         DEBUGFUNC("e1000_get_hw_semaphore_82571");
 525
 526         /* If we have timedout 3 times on trying to acquire
 527          * the inter-port SMBI semaphore, there is old code
 528          * operating on the other port, and it is not
 529          * releasing SMBI. Modify the number of times that
 530          * we try for the semaphore to interwork with this
 531          * older code.
 532          */
 533         if (hw->dev_spec._82571.smb_counter > 2)
 534                 sw_timeout = 1;
 535
 536         /* Get the SW semaphore */
 537         while (i < sw_timeout) {
 538                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 539                 if (!(swsm & E1000_SWSM_SMBI))
 540                         break;
 541
 542                 usec_delay(50);
 543                 i++;
 544         }
 545
 546         if (i == sw_timeout) {
 547                 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
 548                 hw->dev_spec._82571.smb_counter++;
 549         }
 550         /* Get the FW semaphore. */
 551         for (i = 0; i < fw_timeout; i++) {
 552                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 553                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
 554
 555                 /* Semaphore acquired if bit latched */
 556                 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
 557                         break;
 558
 559                 usec_delay(50);
 560         }
 561
 562         if (i == fw_timeout) {
 563                 /* Release semaphores */
 564                 e1000_put_hw_semaphore_82571(hw);
 565                 DEBUGOUT("Driver can't access the NVM\n");
 566                 return -E1000_ERR_NVM;
 567         }
 568
 569         return E1000_SUCCESS;
 570 }
 571
 572 /**
 573  *  e1000_put_hw_semaphore_82571 - Release hardware semaphore
 574  *  @hw: pointer to the HW structure
 575  *
 576  *  Release hardware semaphore used to access the PHY or NVM
 577  **/
 578 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
 579 {
 580         u32 swsm;
 581
 582         DEBUGFUNC("e1000_put_hw_semaphore_generic");
 583
 584         swsm = E1000_READ_REG(hw, E1000_SWSM);
 585
 586         swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
 587
 588         E1000_WRITE_REG(hw, E1000_SWSM, swsm);
 589 }
 590
 591 /**
 592  *  e1000_get_hw_semaphore_82573 - Acquire hardware semaphore
 593  *  @hw: pointer to the HW structure
 594  *
 595  *  Acquire the HW semaphore during reset.
 596  *
 597  **/
 598 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
 599 {
 600         u32 extcnf_ctrl;
 601         s32 i = 0;
 602
 603         DEBUGFUNC("e1000_get_hw_semaphore_82573");
 604
 605         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 606         extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 607         do {
 608                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
 609                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 610
 611                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
 612                         break;
 613
 614                 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 615
 616                 msec_delay(2);
 617                 i++;
 618         } while (i < MDIO_OWNERSHIP_TIMEOUT);
 619
 620         if (i == MDIO_OWNERSHIP_TIMEOUT) {
 621                 /* Release semaphores */
 622                 e1000_put_hw_semaphore_82573(hw);
 623                 DEBUGOUT("Driver can't access the PHY\n");
 624                 return -E1000_ERR_PHY;
 625         }
 626
 627         return E1000_SUCCESS;
 628 }
 629
 630 /**
 631  *  e1000_put_hw_semaphore_82573 - Release hardware semaphore
 632  *  @hw: pointer to the HW structure
 633  *
 634  *  Release hardware semaphore used during reset.
 635  *
 636  **/
 637 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
 638 {
 639         u32 extcnf_ctrl;
 640
 641         DEBUGFUNC("e1000_put_hw_semaphore_82573");
 642
 643         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 644         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 645         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
 646 }
 647
 648 /**
 649  *  e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
 650  *  @hw: pointer to the HW structure
 651  *
 652  *  Acquire the HW semaphore to access the PHY or NVM.
 653  *
 654  **/
 655 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
 656 {
 657         s32 ret_val;
 658
 659         DEBUGFUNC("e1000_get_hw_semaphore_82574");
 660
 661         E1000_MUTEX_LOCK(&hw->dev_spec._82571.swflag_mutex);
 662         ret_val = e1000_get_hw_semaphore_82573(hw);
 663         if (ret_val)
 664                 E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex);
 665         return ret_val;
 666 }
 667
 668 /**
 669  *  e1000_put_hw_semaphore_82574 - Release hardware semaphore
 670  *  @hw: pointer to the HW structure
 671  *
 672  *  Release hardware semaphore used to access the PHY or NVM
 673  *
 674  **/
 675 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
 676 {
 677         DEBUGFUNC("e1000_put_hw_semaphore_82574");
 678
 679         e1000_put_hw_semaphore_82573(hw);
 680         E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex);
 681 }
 682
 683 /**
 684  *  e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state
 685  *  @hw: pointer to the HW structure
 686  *  @active: true to enable LPLU, false to disable
 687  *
 688  *  Sets the LPLU D0 state according to the active flag.
 689  *  LPLU will not be activated unless the
 690  *  device autonegotiation advertisement meets standards of
 691  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 692  *  This is a function pointer entry point only called by
 693  *  PHY setup routines.
 694  **/
 695 STATIC s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
 696 {
 697         u32 data = E1000_READ_REG(hw, E1000_POEMB);
 698
 699         DEBUGFUNC("e1000_set_d0_lplu_state_82574");
 700
 701         if (active)
 702                 data |= E1000_PHY_CTRL_D0A_LPLU;
 703         else
 704                 data &= ~E1000_PHY_CTRL_D0A_LPLU;
 705
 706         E1000_WRITE_REG(hw, E1000_POEMB, data);
 707         return E1000_SUCCESS;
 708 }
 709
 710 /**
 711  *  e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3
 712  *  @hw: pointer to the HW structure
 713  *  @active: boolean used to enable/disable lplu
 714  *
 715  *  The low power link up (lplu) state is set to the power management level D3
 716  *  when active is true, else clear lplu for D3. LPLU
 717  *  is used during Dx states where the power conservation is most important.
 718  *  During driver activity, SmartSpeed should be enabled so performance is
 719  *  maintained.
 720  **/
 721 STATIC s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
 722 {
 723         u32 data = E1000_READ_REG(hw, E1000_POEMB);
 724
 725         DEBUGFUNC("e1000_set_d3_lplu_state_82574");
 726
 727         if (!active) {
 728                 data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
 729         } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 730                    (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
 731                    (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
 732                 data |= E1000_PHY_CTRL_NOND0A_LPLU;
 733         }
 734
 735         E1000_WRITE_REG(hw, E1000_POEMB, data);
 736         return E1000_SUCCESS;
 737 }
 738
 739 /**
 740  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
 741  *  @hw: pointer to the HW structure
 742  *
 743  *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
 744  *  Then for non-82573 hardware, set the EEPROM access request bit and wait
 745  *  for EEPROM access grant bit.  If the access grant bit is not set, release
 746  *  hardware semaphore.
 747  **/
 748 STATIC s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
 749 {
 750         s32 ret_val;
 751
 752         DEBUGFUNC("e1000_acquire_nvm_82571");
 753
 754         ret_val = e1000_get_hw_semaphore_82571(hw);
 755         if (ret_val)
 756                 return ret_val;
 757
 758         switch (hw->mac.type) {
 759         case e1000_82573:
 760                 break;
 761         default:
 762                 ret_val = e1000_acquire_nvm_generic(hw);
 763                 break;
 764         }
 765
 766         if (ret_val)
 767                 e1000_put_hw_semaphore_82571(hw);
 768
 769         return ret_val;
 770 }
 771
 772 /**
 773  *  e1000_release_nvm_82571 - Release exclusive access to EEPROM
 774  *  @hw: pointer to the HW structure
 775  *
 776  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 777  **/
 778 STATIC void e1000_release_nvm_82571(struct e1000_hw *hw)
 779 {
 780         DEBUGFUNC("e1000_release_nvm_82571");
 781
 782         e1000_release_nvm_generic(hw);
 783         e1000_put_hw_semaphore_82571(hw);
 784 }
 785
 786 /**
 787  *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
 788  *  @hw: pointer to the HW structure
 789  *  @offset: offset within the EEPROM to be written to
 790  *  @words: number of words to write
 791  *  @data: 16 bit word(s) to be written to the EEPROM
 792  *
 793  *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
 794  *
 795  *  If e1000_update_nvm_checksum is not called after this function, the
 796  *  EEPROM will most likely contain an invalid checksum.
 797  **/
 798 STATIC s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
 799                                  u16 *data)
 800 {
 801         s32 ret_val;
 802
 803         DEBUGFUNC("e1000_write_nvm_82571");
 804
 805         switch (hw->mac.type) {
 806         case e1000_82573:
 807         case e1000_82574:
 808         case e1000_82583:
 809                 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
 810                 break;
 811         case e1000_82571:
 812         case e1000_82572:
 813                 ret_val = e1000_write_nvm_spi(hw, offset, words, data);
 814                 break;
 815         default:
 816                 ret_val = -E1000_ERR_NVM;
 817                 break;
 818         }
 819
 820         return ret_val;
 821 }
 822
 823 /**
 824  *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum
 825  *  @hw: pointer to the HW structure
 826  *
 827  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 828  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 829  *  value to the EEPROM.
 830  **/
 831 STATIC s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
 832 {
 833         u32 eecd;
 834         s32 ret_val;
 835         u16 i;
 836
 837         DEBUGFUNC("e1000_update_nvm_checksum_82571");
 838
 839         ret_val = e1000_update_nvm_checksum_generic(hw);
 840         if (ret_val)
 841                 return ret_val;
 842
 843         /* If our nvm is an EEPROM, then we're done
 844          * otherwise, commit the checksum to the flash NVM.
 845          */
 846         if (hw->nvm.type != e1000_nvm_flash_hw)
 847                 return E1000_SUCCESS;
 848
 849         /* Check for pending operations. */
 850         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 851                 msec_delay(1);
 852                 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
 853                         break;
 854         }
 855
 856         if (i == E1000_FLASH_UPDATES)
 857                 return -E1000_ERR_NVM;
 858
 859         /* Reset the firmware if using STM opcode. */
 860         if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) {
 861                 /* The enabling of and the actual reset must be done
 862                  * in two write cycles.
 863                  */
 864                 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE);
 865                 E1000_WRITE_FLUSH(hw);
 866                 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET);
 867         }
 868
 869         /* Commit the write to flash */
 870         eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD;
 871         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 872
 873         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 874                 msec_delay(1);
 875                 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
 876                         break;
 877         }
 878
 879         if (i == E1000_FLASH_UPDATES)
 880                 return -E1000_ERR_NVM;
 881
 882         return E1000_SUCCESS;
 883 }
 884
 885 /**
 886  *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
 887  *  @hw: pointer to the HW structure
 888  *
 889  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
 890  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
 891  **/
 892 STATIC s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
 893 {
 894         DEBUGFUNC("e1000_validate_nvm_checksum_82571");
 895
 896         if (hw->nvm.type == e1000_nvm_flash_hw)
 897                 e1000_fix_nvm_checksum_82571(hw);
 898
 899         return e1000_validate_nvm_checksum_generic(hw);
 900 }
 901
 902 /**
 903  *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
 904  *  @hw: pointer to the HW structure
 905  *  @offset: offset within the EEPROM to be written to
 906  *  @words: number of words to write
 907  *  @data: 16 bit word(s) to be written to the EEPROM
 908  *
 909  *  After checking for invalid values, poll the EEPROM to ensure the previous
 910  *  command has completed before trying to write the next word.  After write
 911  *  poll for completion.
 912  *
 913  *  If e1000_update_nvm_checksum is not called after this function, the
 914  *  EEPROM will most likely contain an invalid checksum.
 915  **/
 916 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
 917                                       u16 words, u16 *data)
 918 {
 919         struct e1000_nvm_info *nvm = &hw->nvm;
 920         u32 i, eewr = 0;
 921         s32 ret_val = E1000_SUCCESS;
 922
 923         DEBUGFUNC("e1000_write_nvm_eewr_82571");
 924
 925         /* A check for invalid values:  offset too large, too many words,
 926          * and not enough words.
 927          */
 928         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 929             (words == 0)) {
 930                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 931                 return -E1000_ERR_NVM;
 932         }
 933
 934         for (i = 0; i < words; i++) {
 935                 eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
 936                        ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
 937                        E1000_NVM_RW_REG_START;
 938
 939                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 940                 if (ret_val)
 941                         break;
 942
 943                 E1000_WRITE_REG(hw, E1000_EEWR, eewr);
 944
 945                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 946                 if (ret_val)
 947                         break;
 948         }
 949
 950         return ret_val;
 951 }
 952
 953 /**
 954  *  e1000_get_cfg_done_82571 - Poll for configuration done
 955  *  @hw: pointer to the HW structure
 956  *
 957  *  Reads the management control register for the config done bit to be set.
 958  **/
 959 STATIC s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
 960 {
 961         s32 timeout = PHY_CFG_TIMEOUT;
 962
 963         DEBUGFUNC("e1000_get_cfg_done_82571");
 964
 965         while (timeout) {
 966                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) &
 967                     E1000_NVM_CFG_DONE_PORT_0)
 968                         break;
 969                 msec_delay(1);
 970                 timeout--;
 971         }
 972         if (!timeout) {
 973                 DEBUGOUT("MNG configuration cycle has not completed.\n");
 974                 return -E1000_ERR_RESET;
 975         }
 976
 977         return E1000_SUCCESS;
 978 }
 979
 980 /**
 981  *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
 982  *  @hw: pointer to the HW structure
 983  *  @active: true to enable LPLU, false to disable
 984  *
 985  *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
 986  *  this function also disables smart speed and vice versa.  LPLU will not be
 987  *  activated unless the device autonegotiation advertisement meets standards
 988  *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
 989  *  pointer entry point only called by PHY setup routines.
 990  **/
 991 STATIC s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
 992 {
 993         struct e1000_phy_info *phy = &hw->phy;
 994         s32 ret_val;
 995         u16 data;
 996
 997         DEBUGFUNC("e1000_set_d0_lplu_state_82571");
 998
 999         if (!(phy->ops.read_reg))
1000                 return E1000_SUCCESS;
1001
1002         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1003         if (ret_val)
1004                 return ret_val;
1005
1006         if (active) {
1007                 data |= IGP02E1000_PM_D0_LPLU;
1008                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1009                                              data);
1010                 if (ret_val)
1011                         return ret_val;
1012
1013                 /* When LPLU is enabled, we should disable SmartSpeed */
1014                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1015                                             &data);
1016                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1017                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1018                                              data);
1019                 if (ret_val)
1020                         return ret_val;
1021         } else {
1022                 data &= ~IGP02E1000_PM_D0_LPLU;
1023                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1024                                              data);
1025                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1026                  * during Dx states where the power conservation is most
1027                  * important.  During driver activity we should enable
1028                  * SmartSpeed, so performance is maintained.
1029                  */
1030                 if (phy->smart_speed == e1000_smart_speed_on) {
1031                         ret_val = phy->ops.read_reg(hw,
1032                                                     IGP01E1000_PHY_PORT_CONFIG,
1033                                                     &data);
1034                         if (ret_val)
1035                                 return ret_val;
1036
1037                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1038                         ret_val = phy->ops.write_reg(hw,
1039                                                      IGP01E1000_PHY_PORT_CONFIG,
1040                                                      data);
1041                         if (ret_val)
1042                                 return ret_val;
1043                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1044                         ret_val = phy->ops.read_reg(hw,
1045                                                     IGP01E1000_PHY_PORT_CONFIG,
1046                                                     &data);
1047                         if (ret_val)
1048                                 return ret_val;
1049
1050                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1051                         ret_val = phy->ops.write_reg(hw,
1052                                                      IGP01E1000_PHY_PORT_CONFIG,
1053                                                      data);
1054                         if (ret_val)
1055                                 return ret_val;
1056                 }
1057         }
1058
1059         return E1000_SUCCESS;
1060 }
1061
1062 /**
1063  *  e1000_reset_hw_82571 - Reset hardware
1064  *  @hw: pointer to the HW structure
1065  *
1066  *  This resets the hardware into a known state.
1067  **/
1068 STATIC s32 e1000_reset_hw_82571(struct e1000_hw *hw)
1069 {
1070         u32 ctrl, ctrl_ext, eecd, tctl;
1071         s32 ret_val;
1072
1073         DEBUGFUNC("e1000_reset_hw_82571");
1074
1075         /* Prevent the PCI-E bus from sticking if there is no TLP connection
1076          * on the last TLP read/write transaction when MAC is reset.
1077          */
1078         ret_val = e1000_disable_pcie_master_generic(hw);
1079         if (ret_val)
1080                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1081
1082         DEBUGOUT("Masking off all interrupts\n");
1083         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1084
1085         E1000_WRITE_REG(hw, E1000_RCTL, 0);
1086         tctl = E1000_READ_REG(hw, E1000_TCTL);
1087         tctl &= ~E1000_TCTL_EN;
1088         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1089         E1000_WRITE_FLUSH(hw);
1090
1091         msec_delay(10);
1092
1093         /* Must acquire the MDIO ownership before MAC reset.
1094          * Ownership defaults to firmware after a reset.
1095          */
1096         switch (hw->mac.type) {
1097         case e1000_82573:
1098                 ret_val = e1000_get_hw_semaphore_82573(hw);
1099                 break;
1100         case e1000_82574:
1101         case e1000_82583:
1102                 ret_val = e1000_get_hw_semaphore_82574(hw);
1103                 break;
1104         default:
1105                 break;
1106         }
1107         if (ret_val)
1108                 DEBUGOUT("Cannot acquire MDIO ownership\n");
1109
1110         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1111
1112         DEBUGOUT("Issuing a global reset to MAC\n");
1113         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1114
1115         /* Must release MDIO ownership and mutex after MAC reset. */
1116         switch (hw->mac.type) {
1117         case e1000_82574:
1118         case e1000_82583:
1119                 e1000_put_hw_semaphore_82574(hw);
1120                 break;
1121         default:
1122                 break;
1123         }
1124
1125         if (hw->nvm.type == e1000_nvm_flash_hw) {
1126                 usec_delay(10);
1127                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1128                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1129                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1130                 E1000_WRITE_FLUSH(hw);
1131         }
1132
1133         ret_val = e1000_get_auto_rd_done_generic(hw);
1134         if (ret_val)
1135                 /* We don't want to continue accessing MAC registers. */
1136                 return ret_val;
1137
1138         /* Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1139          * Need to wait for Phy configuration completion before accessing
1140          * NVM and Phy.
1141          */
1142
1143         switch (hw->mac.type) {
1144         case e1000_82571:
1145         case e1000_82572:
1146                 /* REQ and GNT bits need to be cleared when using AUTO_RD
1147                  * to access the EEPROM.
1148                  */
1149                 eecd = E1000_READ_REG(hw, E1000_EECD);
1150                 eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);
1151                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
1152                 break;
1153         case e1000_82573:
1154         case e1000_82574:
1155         case e1000_82583:
1156                 msec_delay(25);
1157                 break;
1158         default:
1159                 break;
1160         }
1161
1162         /* Clear any pending interrupt events. */
1163         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1164         E1000_READ_REG(hw, E1000_ICR);
1165
1166         if (hw->mac.type == e1000_82571) {
1167                 /* Install any alternate MAC address into RAR0 */
1168                 ret_val = e1000_check_alt_mac_addr_generic(hw);
1169                 if (ret_val)
1170                         return ret_val;
1171
1172                 e1000_set_laa_state_82571(hw, true);
1173         }
1174
1175         /* Reinitialize the 82571 serdes link state machine */
1176         if (hw->phy.media_type == e1000_media_type_internal_serdes)
1177                 hw->mac.serdes_link_state = e1000_serdes_link_down;
1178
1179         return E1000_SUCCESS;
1180 }
1181
1182 /**
1183  *  e1000_init_hw_82571 - Initialize hardware
1184  *  @hw: pointer to the HW structure
1185  *
1186  *  This inits the hardware readying it for operation.
1187  **/
1188 STATIC s32 e1000_init_hw_82571(struct e1000_hw *hw)
1189 {
1190         struct e1000_mac_info *mac = &hw->mac;
1191         u32 reg_data;
1192         s32 ret_val;
1193         u16 i, rar_count = mac->rar_entry_count;
1194
1195         DEBUGFUNC("e1000_init_hw_82571");
1196
1197         e1000_initialize_hw_bits_82571(hw);
1198
1199         /* Initialize identification LED */
1200         ret_val = mac->ops.id_led_init(hw);
1201         if (ret_val)
1202                 DEBUGOUT("Error initializing identification LED\n");
1203                 /* This is not fatal and we should not stop init due to this */
1204
1205         /* Disabling VLAN filtering */
1206         DEBUGOUT("Initializing the IEEE VLAN\n");
1207         mac->ops.clear_vfta(hw);
1208
1209         /* Setup the receive address.
1210          * If, however, a locally administered address was assigned to the
1211          * 82571, we must reserve a RAR for it to work around an issue where
1212          * resetting one port will reload the MAC on the other port.
1213          */
1214         if (e1000_get_laa_state_82571(hw))
1215                 rar_count--;
1216         e1000_init_rx_addrs_generic(hw, rar_count);
1217
1218         /* Zero out the Multicast HASH table */
1219         DEBUGOUT("Zeroing the MTA\n");
1220         for (i = 0; i < mac->mta_reg_count; i++)
1221                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1222
1223         /* Setup link and flow control */
1224         ret_val = mac->ops.setup_link(hw);
1225
1226         /* Set the transmit descriptor write-back policy */
1227         reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
1228         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1229                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
1230         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
1231
1232         /* ...for both queues. */
1233         switch (mac->type) {
1234         case e1000_82573:
1235                 e1000_enable_tx_pkt_filtering_generic(hw);
1236                 /* fall through */
1237         case e1000_82574:
1238         case e1000_82583:
1239                 reg_data = E1000_READ_REG(hw, E1000_GCR);
1240                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1241                 E1000_WRITE_REG(hw, E1000_GCR, reg_data);
1242                 break;
1243         default:
1244                 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
1245                 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1246                            E1000_TXDCTL_FULL_TX_DESC_WB |
1247                            E1000_TXDCTL_COUNT_DESC;
1248                 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
1249                 break;
1250         }
1251
1252         /* Clear all of the statistics registers (clear on read).  It is
1253          * important that we do this after we have tried to establish link
1254          * because the symbol error count will increment wildly if there
1255          * is no link.
1256          */
1257         e1000_clear_hw_cntrs_82571(hw);
1258
1259         return ret_val;
1260 }
1261
1262 /**
1263  *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1264  *  @hw: pointer to the HW structure
1265  *
1266  *  Initializes required hardware-dependent bits needed for normal operation.
1267  **/
1268 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1269 {
1270         u32 reg;
1271
1272         DEBUGFUNC("e1000_initialize_hw_bits_82571");
1273
1274         /* Transmit Descriptor Control 0 */
1275         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1276         reg |= (1 << 22);
1277         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1278
1279         /* Transmit Descriptor Control 1 */
1280         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1281         reg |= (1 << 22);
1282         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1283
1284         /* Transmit Arbitration Control 0 */
1285         reg = E1000_READ_REG(hw, E1000_TARC(0));
1286         reg &= ~(0xF << 27); /* 30:27 */
1287         switch (hw->mac.type) {
1288         case e1000_82571:
1289         case e1000_82572:
1290                 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1291                 break;
1292         case e1000_82574:
1293         case e1000_82583:
1294                 reg |= (1 << 26);
1295                 break;
1296         default:
1297                 break;
1298         }
1299         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1300
1301         /* Transmit Arbitration Control 1 */
1302         reg = E1000_READ_REG(hw, E1000_TARC(1));
1303         switch (hw->mac.type) {
1304         case e1000_82571:
1305         case e1000_82572:
1306                 reg &= ~((1 << 29) | (1 << 30));
1307                 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1308                 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1309                         reg &= ~(1 << 28);
1310                 else
1311                         reg |= (1 << 28);
1312                 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1313                 break;
1314         default:
1315                 break;
1316         }
1317
1318         /* Device Control */
1319         switch (hw->mac.type) {
1320         case e1000_82573:
1321         case e1000_82574:
1322         case e1000_82583:
1323                 reg = E1000_READ_REG(hw, E1000_CTRL);
1324                 reg &= ~(1 << 29);
1325                 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1326                 break;
1327         default:
1328                 break;
1329         }
1330
1331         /* Extended Device Control */
1332         switch (hw->mac.type) {
1333         case e1000_82573:
1334         case e1000_82574:
1335         case e1000_82583:
1336                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1337                 reg &= ~(1 << 23);
1338                 reg |= (1 << 22);
1339                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1340                 break;
1341         default:
1342                 break;
1343         }
1344
1345         if (hw->mac.type == e1000_82571) {
1346                 reg = E1000_READ_REG(hw, E1000_PBA_ECC);
1347                 reg |= E1000_PBA_ECC_CORR_EN;
1348                 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg);
1349         }
1350
1351         /* Workaround for hardware errata.
1352          * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1353          */
1354         if ((hw->mac.type == e1000_82571) ||
1355            (hw->mac.type == e1000_82572)) {
1356                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1357                 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1358                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1359         }
1360
1361         /* Disable IPv6 extension header parsing because some malformed
1362          * IPv6 headers can hang the Rx.
1363          */
1364         if (hw->mac.type <= e1000_82573) {
1365                 reg = E1000_READ_REG(hw, E1000_RFCTL);
1366                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1367                 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
1368         }
1369
1370         /* PCI-Ex Control Registers */
1371         switch (hw->mac.type) {
1372         case e1000_82574:
1373         case e1000_82583:
1374                 reg = E1000_READ_REG(hw, E1000_GCR);
1375                 reg |= (1 << 22);
1376                 E1000_WRITE_REG(hw, E1000_GCR, reg);
1377
1378                 /* Workaround for hardware errata.
1379                  * apply workaround for hardware errata documented in errata
1380                  * docs Fixes issue where some error prone or unreliable PCIe
1381                  * completions are occurring, particularly with ASPM enabled.
1382                  * Without fix, issue can cause Tx timeouts.
1383                  */
1384                 reg = E1000_READ_REG(hw, E1000_GCR2);
1385                 reg |= 1;
1386                 E1000_WRITE_REG(hw, E1000_GCR2, reg);
1387                 break;
1388         default:
1389                 break;
1390         }
1391
1392         return;
1393 }
1394
1395 /**
1396  *  e1000_clear_vfta_82571 - Clear VLAN filter table
1397  *  @hw: pointer to the HW structure
1398  *
1399  *  Clears the register array which contains the VLAN filter table by
1400  *  setting all the values to 0.
1401  **/
1402 STATIC void e1000_clear_vfta_82571(struct e1000_hw *hw)
1403 {
1404         u32 offset;
1405         u32 vfta_value = 0;
1406         u32 vfta_offset = 0;
1407         u32 vfta_bit_in_reg = 0;
1408
1409         DEBUGFUNC("e1000_clear_vfta_82571");
1410
1411         switch (hw->mac.type) {
1412         case e1000_82573:
1413         case e1000_82574:
1414         case e1000_82583:
1415                 if (hw->mng_cookie.vlan_id != 0) {
1416                         /* The VFTA is a 4096b bit-field, each identifying
1417                          * a single VLAN ID.  The following operations
1418                          * determine which 32b entry (i.e. offset) into the
1419                          * array we want to set the VLAN ID (i.e. bit) of
1420                          * the manageability unit.
1421                          */
1422                         vfta_offset = (hw->mng_cookie.vlan_id >>
1423                                        E1000_VFTA_ENTRY_SHIFT) &
1424                             E1000_VFTA_ENTRY_MASK;
1425                         vfta_bit_in_reg =
1426                             1 << (hw->mng_cookie.vlan_id &
1427                                   E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1428                 }
1429                 break;
1430         default:
1431                 break;
1432         }
1433         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1434                 /* If the offset we want to clear is the same offset of the
1435                  * manageability VLAN ID, then clear all bits except that of
1436                  * the manageability unit.
1437                  */
1438                 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1439                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1440                 E1000_WRITE_FLUSH(hw);
1441         }
1442 }
1443
1444 /**
1445  *  e1000_check_mng_mode_82574 - Check manageability is enabled
1446  *  @hw: pointer to the HW structure
1447  *
1448  *  Reads the NVM Initialization Control Word 2 and returns true
1449  *  (>0) if any manageability is enabled, else false (0).
1450  **/
1451 STATIC bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1452 {
1453         u16 data;
1454
1455         DEBUGFUNC("e1000_check_mng_mode_82574");
1456
1457         hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1458         return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1459 }
1460
1461 /**
1462  *  e1000_led_on_82574 - Turn LED on
1463  *  @hw: pointer to the HW structure
1464  *
1465  *  Turn LED on.
1466  **/
1467 STATIC s32 e1000_led_on_82574(struct e1000_hw *hw)
1468 {
1469         u32 ctrl;
1470         u32 i;
1471
1472         DEBUGFUNC("e1000_led_on_82574");
1473
1474         ctrl = hw->mac.ledctl_mode2;
1475         if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) {
1476                 /* If no link, then turn LED on by setting the invert bit
1477                  * for each LED that's "on" (0x0E) in ledctl_mode2.
1478                  */
1479                 for (i = 0; i < 4; i++)
1480                         if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1481                             E1000_LEDCTL_MODE_LED_ON)
1482                                 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1483         }
1484         E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl);
1485
1486         return E1000_SUCCESS;
1487 }
1488
1489 /**
1490  *  e1000_check_phy_82574 - check 82574 phy hung state
1491  *  @hw: pointer to the HW structure
1492  *
1493  *  Returns whether phy is hung or not
1494  **/
1495 bool e1000_check_phy_82574(struct e1000_hw *hw)
1496 {
1497         u16 status_1kbt = 0;
1498         u16 receive_errors = 0;
1499         s32 ret_val = E1000_SUCCESS;
1500
1501         DEBUGFUNC("e1000_check_phy_82574");
1502
1503         /* Read PHY Receive Error counter first, if its is max - all F's then
1504          * read the Base1000T status register If both are max then PHY is hung.
1505          */
1506         ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,
1507                                        &receive_errors);
1508         if (ret_val)
1509                 return false;
1510         if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1511                 ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,
1512                                                &status_1kbt);
1513                 if (ret_val)
1514                         return false;
1515                 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1516                     E1000_IDLE_ERROR_COUNT_MASK)
1517                         return true;
1518         }
1519
1520         return false;
1521 }
1522
1523
1524 /**
1525  *  e1000_setup_link_82571 - Setup flow control and link settings
1526  *  @hw: pointer to the HW structure
1527  *
1528  *  Determines which flow control settings to use, then configures flow
1529  *  control.  Calls the appropriate media-specific link configuration
1530  *  function.  Assuming the adapter has a valid link partner, a valid link
1531  *  should be established.  Assumes the hardware has previously been reset
1532  *  and the transmitter and receiver are not enabled.
1533  **/
1534 STATIC s32 e1000_setup_link_82571(struct e1000_hw *hw)
1535 {
1536         DEBUGFUNC("e1000_setup_link_82571");
1537
1538         /* 82573 does not have a word in the NVM to determine
1539          * the default flow control setting, so we explicitly
1540          * set it to full.
1541          */
1542         switch (hw->mac.type) {
1543         case e1000_82573:
1544         case e1000_82574:
1545         case e1000_82583:
1546                 if (hw->fc.requested_mode == e1000_fc_default)
1547                         hw->fc.requested_mode = e1000_fc_full;
1548                 break;
1549         default:
1550                 break;
1551         }
1552
1553         return e1000_setup_link_generic(hw);
1554 }
1555
1556 /**
1557  *  e1000_setup_copper_link_82571 - Configure copper link settings
1558  *  @hw: pointer to the HW structure
1559  *
1560  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1561  *  for link, once link is established calls to configure collision distance
1562  *  and flow control are called.
1563  **/
1564 STATIC s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1565 {
1566         u32 ctrl;
1567         s32 ret_val;
1568
1569         DEBUGFUNC("e1000_setup_copper_link_82571");
1570
1571         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1572         ctrl |= E1000_CTRL_SLU;
1573         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1574         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1575
1576         switch (hw->phy.type) {
1577         case e1000_phy_m88:
1578         case e1000_phy_bm:
1579                 ret_val = e1000_copper_link_setup_m88(hw);
1580                 break;
1581         case e1000_phy_igp_2:
1582                 ret_val = e1000_copper_link_setup_igp(hw);
1583                 break;
1584         default:
1585                 return -E1000_ERR_PHY;
1586                 break;
1587         }
1588
1589         if (ret_val)
1590                 return ret_val;
1591
1592         return e1000_setup_copper_link_generic(hw);
1593 }
1594
1595 /**
1596  *  e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1597  *  @hw: pointer to the HW structure
1598  *
1599  *  Configures collision distance and flow control for fiber and serdes links.
1600  *  Upon successful setup, poll for link.
1601  **/
1602 STATIC s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1603 {
1604         DEBUGFUNC("e1000_setup_fiber_serdes_link_82571");
1605
1606         switch (hw->mac.type) {
1607         case e1000_82571:
1608         case e1000_82572:
1609                 /* If SerDes loopback mode is entered, there is no form
1610                  * of reset to take the adapter out of that mode.  So we
1611                  * have to explicitly take the adapter out of loopback
1612                  * mode.  This prevents drivers from twiddling their thumbs
1613                  * if another tool failed to take it out of loopback mode.
1614                  */
1615                 E1000_WRITE_REG(hw, E1000_SCTL,
1616                                 E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1617                 break;
1618         default:
1619                 break;
1620         }
1621
1622         return e1000_setup_fiber_serdes_link_generic(hw);
1623 }
1624
1625 /**
1626  *  e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1627  *  @hw: pointer to the HW structure
1628  *
1629  *  Reports the link state as up or down.
1630  *
1631  *  If autonegotiation is supported by the link partner, the link state is
1632  *  determined by the result of autonegotiation. This is the most likely case.
1633  *  If autonegotiation is not supported by the link partner, and the link
1634  *  has a valid signal, force the link up.
1635  *
1636  *  The link state is represented internally here by 4 states:
1637  *
1638  *  1) down
1639  *  2) autoneg_progress
1640  *  3) autoneg_complete (the link successfully autonegotiated)
1641  *  4) forced_up (the link has been forced up, it did not autonegotiate)
1642  *
1643  **/
1644 STATIC s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1645 {
1646         struct e1000_mac_info *mac = &hw->mac;
1647         u32 rxcw;
1648         u32 ctrl;
1649         u32 status;
1650         u32 txcw;
1651         u32 i;
1652         s32 ret_val = E1000_SUCCESS;
1653
1654         DEBUGFUNC("e1000_check_for_serdes_link_82571");
1655
1656         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1657         status = E1000_READ_REG(hw, E1000_STATUS);
1658         rxcw = E1000_READ_REG(hw, E1000_RXCW);
1659         /* SYNCH bit and IV bit are sticky */
1660         usec_delay(10);
1661         rxcw = E1000_READ_REG(hw, E1000_RXCW);
1662
1663         if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1664
1665                 /* Receiver is synchronized with no invalid bits.  */
1666                 switch (mac->serdes_link_state) {
1667                 case e1000_serdes_link_autoneg_complete:
1668                         if (!(status & E1000_STATUS_LU)) {
1669                                 /* We have lost link, retry autoneg before
1670                                  * reporting link failure
1671                                  */
1672                                 mac->serdes_link_state =
1673                                     e1000_serdes_link_autoneg_progress;
1674                                 mac->serdes_has_link = false;
1675                                 DEBUGOUT("AN_UP     -> AN_PROG\n");
1676                         } else {
1677                                 mac->serdes_has_link = true;
1678                         }
1679                         break;
1680
1681                 case e1000_serdes_link_forced_up:
1682                         /* If we are receiving /C/ ordered sets, re-enable
1683                          * auto-negotiation in the TXCW register and disable
1684                          * forced link in the Device Control register in an
1685                          * attempt to auto-negotiate with our link partner.
1686                          */
1687                         if (rxcw & E1000_RXCW_C) {
1688                                 /* Enable autoneg, and unforce link up */
1689                                 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1690                                 E1000_WRITE_REG(hw, E1000_CTRL,
1691                                     (ctrl & ~E1000_CTRL_SLU));
1692                                 mac->serdes_link_state =
1693                                     e1000_serdes_link_autoneg_progress;
1694                                 mac->serdes_has_link = false;
1695                                 DEBUGOUT("FORCED_UP -> AN_PROG\n");
1696                         } else {
1697                                 mac->serdes_has_link = true;
1698                         }
1699                         break;
1700
1701                 case e1000_serdes_link_autoneg_progress:
1702                         if (rxcw & E1000_RXCW_C) {
1703                                 /* We received /C/ ordered sets, meaning the
1704                                  * link partner has autonegotiated, and we can
1705                                  * trust the Link Up (LU) status bit.
1706                                  */
1707                                 if (status & E1000_STATUS_LU) {
1708                                         mac->serdes_link_state =
1709                                             e1000_serdes_link_autoneg_complete;
1710                                         DEBUGOUT("AN_PROG   -> AN_UP\n");
1711                                         mac->serdes_has_link = true;
1712                                 } else {
1713                                         /* Autoneg completed, but failed. */
1714                                         mac->serdes_link_state =
1715                                             e1000_serdes_link_down;
1716                                         DEBUGOUT("AN_PROG   -> DOWN\n");
1717                                 }
1718                         } else {
1719                                 /* The link partner did not autoneg.
1720                                  * Force link up and full duplex, and change
1721                                  * state to forced.
1722                                  */
1723                                 E1000_WRITE_REG(hw, E1000_TXCW,
1724                                 (mac->txcw & ~E1000_TXCW_ANE));
1725                                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1726                                 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1727
1728                                 /* Configure Flow Control after link up. */
1729                                 ret_val =
1730                                     e1000_config_fc_after_link_up_generic(hw);
1731                                 if (ret_val) {
1732                                         DEBUGOUT("Error config flow control\n");
1733                                         break;
1734                                 }
1735                                 mac->serdes_link_state =
1736                                                 e1000_serdes_link_forced_up;
1737                                 mac->serdes_has_link = true;
1738                                 DEBUGOUT("AN_PROG   -> FORCED_UP\n");
1739                         }
1740                         break;
1741
1742                 case e1000_serdes_link_down:
1743                 default:
1744                         /* The link was down but the receiver has now gained
1745                          * valid sync, so lets see if we can bring the link
1746                          * up.
1747                          */
1748                         E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1749                         E1000_WRITE_REG(hw, E1000_CTRL, (ctrl &
1750                                         ~E1000_CTRL_SLU));
1751                         mac->serdes_link_state =
1752                                         e1000_serdes_link_autoneg_progress;
1753                         mac->serdes_has_link = false;
1754                         DEBUGOUT("DOWN      -> AN_PROG\n");
1755                         break;
1756                 }
1757         } else {
1758                 if (!(rxcw & E1000_RXCW_SYNCH)) {
1759                         mac->serdes_has_link = false;
1760                         mac->serdes_link_state = e1000_serdes_link_down;
1761                         DEBUGOUT("ANYSTATE  -> DOWN\n");
1762                 } else {
1763                         /* Check several times, if SYNCH bit and CONFIG
1764                          * bit both are consistently 1 then simply ignore
1765                          * the IV bit and restart Autoneg
1766                          */
1767                         for (i = 0; i < AN_RETRY_COUNT; i++) {
1768                                 usec_delay(10);
1769                                 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1770                                 if ((rxcw & E1000_RXCW_SYNCH) &&
1771                                     (rxcw & E1000_RXCW_C))
1772                                         continue;
1773
1774                                 if (rxcw & E1000_RXCW_IV) {
1775                                         mac->serdes_has_link = false;
1776                                         mac->serdes_link_state =
1777                                                         e1000_serdes_link_down;
1778                                         DEBUGOUT("ANYSTATE  -> DOWN\n");
1779                                         break;
1780                                 }
1781                         }
1782
1783                         if (i == AN_RETRY_COUNT) {
1784                                 txcw = E1000_READ_REG(hw, E1000_TXCW);
1785                                 txcw |= E1000_TXCW_ANE;
1786                                 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1787                                 mac->serdes_link_state =
1788                                         e1000_serdes_link_autoneg_progress;
1789                                 mac->serdes_has_link = false;
1790                                 DEBUGOUT("ANYSTATE  -> AN_PROG\n");
1791                         }
1792                 }
1793         }
1794
1795         return ret_val;
1796 }
1797
1798 /**
1799  *  e1000_valid_led_default_82571 - Verify a valid default LED config
1800  *  @hw: pointer to the HW structure
1801  *  @data: pointer to the NVM (EEPROM)
1802  *
1803  *  Read the EEPROM for the current default LED configuration.  If the
1804  *  LED configuration is not valid, set to a valid LED configuration.
1805  **/
1806 STATIC s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1807 {
1808         s32 ret_val;
1809
1810         DEBUGFUNC("e1000_valid_led_default_82571");
1811
1812         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1813         if (ret_val) {
1814                 DEBUGOUT("NVM Read Error\n");
1815                 return ret_val;
1816         }
1817
1818         switch (hw->mac.type) {
1819         case e1000_82573:
1820         case e1000_82574:
1821         case e1000_82583:
1822                 if (*data == ID_LED_RESERVED_F746)
1823                         *data = ID_LED_DEFAULT_82573;
1824                 break;
1825         default:
1826                 if (*data == ID_LED_RESERVED_0000 ||
1827                     *data == ID_LED_RESERVED_FFFF)
1828                         *data = ID_LED_DEFAULT;
1829                 break;
1830         }
1831
1832         return E1000_SUCCESS;
1833 }
1834
1835 /**
1836  *  e1000_get_laa_state_82571 - Get locally administered address state
1837  *  @hw: pointer to the HW structure
1838  *
1839  *  Retrieve and return the current locally administered address state.
1840  **/
1841 bool e1000_get_laa_state_82571(struct e1000_hw *hw)
1842 {
1843         DEBUGFUNC("e1000_get_laa_state_82571");
1844
1845         if (hw->mac.type != e1000_82571)
1846                 return false;
1847
1848         return hw->dev_spec._82571.laa_is_present;
1849 }
1850
1851 /**
1852  *  e1000_set_laa_state_82571 - Set locally administered address state
1853  *  @hw: pointer to the HW structure
1854  *  @state: enable/disable locally administered address
1855  *
1856  *  Enable/Disable the current locally administered address state.
1857  **/
1858 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state)
1859 {
1860         DEBUGFUNC("e1000_set_laa_state_82571");
1861
1862         if (hw->mac.type != e1000_82571)
1863                 return;
1864
1865         hw->dev_spec._82571.laa_is_present = state;
1866
1867         /* If workaround is activated... */
1868         if (state)
1869                 /* Hold a copy of the LAA in RAR[14] This is done so that
1870                  * between the time RAR[0] gets clobbered and the time it
1871                  * gets fixed, the actual LAA is in one of the RARs and no
1872                  * incoming packets directed to this port are dropped.
1873                  * Eventually the LAA will be in RAR[0] and RAR[14].
1874                  */
1875                 hw->mac.ops.rar_set(hw, hw->mac.addr,
1876                                     hw->mac.rar_entry_count - 1);
1877         return;
1878 }
1879
1880 /**
1881  *  e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1882  *  @hw: pointer to the HW structure
1883  *
1884  *  Verifies that the EEPROM has completed the update.  After updating the
1885  *  EEPROM, we need to check bit 15 in work 0x23 for the checksum fix.  If
1886  *  the checksum fix is not implemented, we need to set the bit and update
1887  *  the checksum.  Otherwise, if bit 15 is set and the checksum is incorrect,
1888  *  we need to return bad checksum.
1889  **/
1890 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1891 {
1892         struct e1000_nvm_info *nvm = &hw->nvm;
1893         s32 ret_val;
1894         u16 data;
1895
1896         DEBUGFUNC("e1000_fix_nvm_checksum_82571");
1897
1898         if (nvm->type != e1000_nvm_flash_hw)
1899                 return E1000_SUCCESS;
1900
1901         /* Check bit 4 of word 10h.  If it is 0, firmware is done updating
1902          * 10h-12h.  Checksum may need to be fixed.
1903          */
1904         ret_val = nvm->ops.read(hw, 0x10, 1, &data);
1905         if (ret_val)
1906                 return ret_val;
1907
1908         if (!(data & 0x10)) {
1909                 /* Read 0x23 and check bit 15.  This bit is a 1
1910                  * when the checksum has already been fixed.  If
1911                  * the checksum is still wrong and this bit is a
1912                  * 1, we need to return bad checksum.  Otherwise,
1913                  * we need to set this bit to a 1 and update the
1914                  * checksum.
1915                  */
1916                 ret_val = nvm->ops.read(hw, 0x23, 1, &data);
1917                 if (ret_val)
1918                         return ret_val;
1919
1920                 if (!(data & 0x8000)) {
1921                         data |= 0x8000;
1922                         ret_val = nvm->ops.write(hw, 0x23, 1, &data);
1923                         if (ret_val)
1924                                 return ret_val;
1925                         ret_val = nvm->ops.update(hw);
1926                 }
1927         }
1928
1929         return E1000_SUCCESS;
1930 }
1931
1932
1933 /**
1934  *  e1000_read_mac_addr_82571 - Read device MAC address
1935  *  @hw: pointer to the HW structure
1936  **/
1937 STATIC s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1938 {
1939         DEBUGFUNC("e1000_read_mac_addr_82571");
1940
1941         if (hw->mac.type == e1000_82571) {
1942                 s32 ret_val = E1000_SUCCESS;
1943
1944                 /* If there's an alternate MAC address place it in RAR0
1945                  * so that it will override the Si installed default perm
1946                  * address.
1947                  */
1948                 ret_val = e1000_check_alt_mac_addr_generic(hw);
1949                 if (ret_val)
1950                         return ret_val;
1951         }
1952
1953         return e1000_read_mac_addr_generic(hw);
1954 }
1955
1956 /**
1957  * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1958  * @hw: pointer to the HW structure
1959  *
1960  * In the case of a PHY power down to save power, or to turn off link during a
1961  * driver unload, or wake on lan is not enabled, remove the link.
1962  **/
1963 STATIC void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1964 {
1965         struct e1000_phy_info *phy = &hw->phy;
1966         struct e1000_mac_info *mac = &hw->mac;
1967
1968         if (!phy->ops.check_reset_block)
1969                 return;
1970
1971         /* If the management interface is not enabled, then power down */
1972         if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1973                 e1000_power_down_phy_copper(hw);
1974
1975         return;
1976 }
1977
1978 /**
1979  *  e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1980  *  @hw: pointer to the HW structure
1981  *
1982  *  Clears the hardware counters by reading the counter registers.
1983  **/
1984 STATIC void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1985 {
1986         DEBUGFUNC("e1000_clear_hw_cntrs_82571");
1987
1988         e1000_clear_hw_cntrs_base_generic(hw);
1989
1990         E1000_READ_REG(hw, E1000_PRC64);
1991         E1000_READ_REG(hw, E1000_PRC127);
1992         E1000_READ_REG(hw, E1000_PRC255);
1993         E1000_READ_REG(hw, E1000_PRC511);
1994         E1000_READ_REG(hw, E1000_PRC1023);
1995         E1000_READ_REG(hw, E1000_PRC1522);
1996         E1000_READ_REG(hw, E1000_PTC64);
1997         E1000_READ_REG(hw, E1000_PTC127);
1998         E1000_READ_REG(hw, E1000_PTC255);
1999         E1000_READ_REG(hw, E1000_PTC511);
2000         E1000_READ_REG(hw, E1000_PTC1023);
2001         E1000_READ_REG(hw, E1000_PTC1522);
2002
2003         E1000_READ_REG(hw, E1000_ALGNERRC);
2004         E1000_READ_REG(hw, E1000_RXERRC);
2005         E1000_READ_REG(hw, E1000_TNCRS);
2006         E1000_READ_REG(hw, E1000_CEXTERR);
2007         E1000_READ_REG(hw, E1000_TSCTC);
2008         E1000_READ_REG(hw, E1000_TSCTFC);
2009
2010         E1000_READ_REG(hw, E1000_MGTPRC);
2011         E1000_READ_REG(hw, E1000_MGTPDC);
2012         E1000_READ_REG(hw, E1000_MGTPTC);
2013
2014         E1000_READ_REG(hw, E1000_IAC);
2015         E1000_READ_REG(hw, E1000_ICRXOC);
2016
2017         E1000_READ_REG(hw, E1000_ICRXPTC);
2018         E1000_READ_REG(hw, E1000_ICRXATC);
2019         E1000_READ_REG(hw, E1000_ICTXPTC);
2020         E1000_READ_REG(hw, E1000_ICTXATC);
2021         E1000_READ_REG(hw, E1000_ICTXQEC);
2022         E1000_READ_REG(hw, E1000_ICTXQMTC);
2023         E1000_READ_REG(hw, E1000_ICRXDMTC);
2024 }